JP2000021914A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the cracking of passivation due to heat and pressure in mounting and to easily improve not only reliability when mounted but also that of a semiconductor device by holding the film thickness of a passivation film to be more than a specified one. SOLUTION: A pad 12 for constituting a circuit and supplying the input/ output of the circuit and power voltage is formed on a semiconductor substrate 11. Then, a passivation film 13 is formed in the range of 2.2±0.2 micro meters with silicon oxide by using a CVD method. Then, an opening 14 is formed. Then, a metallic plating bump 20 is formed on the semiconductor substrate 11. Thus, the cracking of the passivation film 13 in mounting can easily be prevented without taking a process different from a former one. Consequently, not only reliability in mounting but also that of the semiconductor device can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technology for externally connecting a semiconductor device and a technology for packaging a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, an element constituting a circuit is formed on a semiconductor substrate, and a pad for supplying input / output of the circuit and a power supply voltage is provided. An opening for passivation formed on the pad is formed on the pad. When a metal film and a metal-plated bump are formed through the interposition, it is well known that a circuit protection film is formed of a phosphorus glass film and a nitride film as disclosed in Japanese Patent Application Laid-Open No. 57-126150. Also, a method of forming a second passivation film after forming a metal plating bump according to Japanese Patent Application Laid-Open No. 1-42841 and a method of devising a structure as disclosed in Japanese Patent Application Laid-Open Nos. 60-245257 and 57-2549. Has been proposed.

[0003]

However, in the above-mentioned method of the prior art in which the passivation film is formed into two layers, if the thickness of the passivation film is unknown and the passivation film is thin, for example, a TAB ( Ta
In the case of mounting by Pe Automated Bonding, cracks may be formed in the passivation film due to a temperature and a load close to 500 ° C., so that the reliability is increased. Further, in each method described later, the structure is complicated and the cost is high. In addition, the integrity when forming each film and other defects due to defects of each film are caused and the stability is increased.

[0004]

SUMMARY OF THE INVENTION In view of the above problems, the present invention examines the passivation film thickness and determines whether the passivation film to be formed is a single layer of phosphorus glass or a two-layer film in which a nitride film is formed on phosphorus glass. By keeping the thickness of the film at 2 micrometers or more, heat during mounting,
A crack in passivation due to pressure can be prevented, and not only reliability at the time of mounting but also reliability of a semiconductor device has been achieved by a simple method.

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) An example of a semiconductor device forming process of the present invention will be described with reference to FIG. Since the steps of forming a circuit on a semiconductor substrate are the same as those of a conventional semiconductor process, a description thereof will be omitted, and a pad 12 for forming a circuit and supplying input / output of the circuit and a power supply voltage will be described. After forming the passivation film 13 on the substrate 11, the passivation film 13 of the present invention is formed in a range of 2.2 ± 0.2 μm using silicon oxide by a CVD method, and then an opening 14 is formed. Metal plated bumps are formed on the semiconductor substrate through the processes (1) to (4) in FIG. First, as shown in FIG. 1A, an adhesion metal layer 15 is formed on the semiconductor substrate 11 by continuous sputtering to a thickness of 2000 Å with TiW, and subsequently, a barrier metal layer 16 is formed of Au with a thickness of 2 Å.
000 angstroms. Next, as shown in FIG. 1 (2), after applying a photoresist 17 with a thickness of 30 μm, an opening 18 for selective plating is formed through a predetermined process. Next, as shown in FIG. 1 (3-1), the Au metal plating bump 2 is
0 is deposited and grown. Thereafter, as shown in FIG. 1 (3-2), the photoresist 17 is peeled and removed in a predetermined step, and as shown in FIG. 1 (4), the metal plating bump 20 is used as a mask to remove potassium iodide. Au as the barrier metal layer 16 is etched with a mixture of iodine, and subsequently, TiW as the adhesion metal layer 15 is etched with a mixture of hydrogen peroxide and water. Through the process described with reference to FIG. 1, the semiconductor device shown in FIG. 2 was completed.

A semiconductor device in which the thickness of the passivation film 13 is varied by the structure and the process described above is prepared, and TAB mounting is performed using the semiconductor device, and the result of the evaluation is described with reference to FIGS. 3 and 6. FIG. 3 is a sectional view of an example in which a semiconductor device effective by applying the present invention is mounted on a circuit board by TAB. The metal-plated bumps of this embodiment are formed on a substrate 21 on which a circuit is formed, and then are connected to a metal wiring 24 formed on a circuit board 23 for incorporating a product circuit through a bump 22 through one bump portion. Heating and pressing were performed at 520 ° C. and a load of 50 g per 22 pieces. As a result of the evaluation,
As shown in FIG. 6, 10 bumps were checked at a time, and good results were obtained when the silicon oxide film was 2.0 μm or more. A good result was obtained as shown in FIG. 6 for a semiconductor device similarly manufactured by using the passivation film as phosphorus glass. The semiconductor device was put into a temperature cycle test at −30 ° C. and 80 ° C., and a device having a passivation film having a thickness of 2.0 μm or more did not cause stress migration of the circuit and did not crack.

(Second Embodiment) A second embodiment will be described with reference to FIG. Pad 1 is formed on a substrate 11 on which a circuit is formed.
After the formation of No. 2, a first passivation film 13 was formed by CVD using silicon oxide, and an opening 14 was formed. CV on the first passivation film 13
After the second passivation film 25 was formed of silicon nitride by Method D, the openings 14 were formed so as to overlap. However, the first passivation film 13 and the second passivation film 25 are formed so as to overlap in the description of the present embodiment, but the opening of the first passivation film 25 is desirably at least larger than the first passivation film 13. The better the step coverage, the better. More desirably, it is better to increase the size by 3 micrometers or more. FIG. 6 shows the results of evaluating the thickness of the silicon nitride film in the structure in which the passivation films are stacked. The same good results as in the first embodiment were obtained.

(Third Embodiment) A description will be given with reference to FIG.
Metal plated bumps are formed using photosensitive polyimide instead of the photoresist described in FIG. In the present embodiment, the thickness of the photosensitive polyimide 26 is 15 micrometers, and the metal plating bump 20 is formed to 20 micrometers. The same evaluation as in the first embodiment and the second embodiment was performed, and the effect of the present invention was confirmed. It should be noted that the semiconductor device of the present invention is not limited to TAB, for example, COG (Chip
It goes without saying that there is no problem even if it is applied to (On Glass) and there is no restriction on the mounting method to be applied.

[0010]

As described above, the present invention relates to a passivation film in a semiconductor device in which elements constituting a circuit are formed on a semiconductor substrate and which has pads for supplying input / output of the circuit and power supply voltage. Investigating from a new perspective that the total thickness should be 2.0 micrometers or more even in a single layer or a laminated layer, it is possible to easily prevent cracking of the passivation film during mounting without taking a process different from the conventional one. A new effect was discovered and confirmed. According to the present invention, it has become possible to greatly improve the reliability of a semiconductor device.

[Brief description of the drawings]

FIG. 1 is a process chart showing one preferred embodiment of the process of the present invention.

FIG. 2 is a sectional structural view showing a preferred embodiment of the present invention.

FIG. 3 is a view showing a cross-sectional structure of a semiconductor device according to an embodiment of the present invention;

FIG. 4 is a sectional structural view showing a second preferred embodiment of the present invention.

FIG. 5 is a sectional structural view showing a third preferred embodiment of the present invention.

FIG. 6 is a diagram showing evaluation results when the present invention is applied.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Semiconductor substrate 12 Pad 13 Passivation film 14 Opening 15 Adhesion metal layer 16 Barrier metal layer 17 Photoresist 18 Opening for selective plating 19 Power supply for plating 20 Metal plating bump 21 Substrate on which circuit was formed 22 Bump 23 Product circuit Circuit board for embedding 24 metal wiring 25 second passivation film 26 photosensitive polyimide

Claims (5)

[Claims] An element constituting a circuit is formed on a semiconductor substrate, and a pad for supplying input / output of the circuit and a power supply voltage is provided, and a pad is formed through the passivation opening formed on the pad. A semiconductor device in which a metal film and a metal plated bump are formed, wherein the thickness of the passivation film is 2 micrometers or more. 2. The semiconductor device according to claim 1, wherein the passivation film comprises a single layer or a stack of a phosphorus glass film or a silicon oxide film and a silicon nitride film formed on the single layer or the stack of the phosphorus glass film or the silicon oxide film. A semiconductor device, comprising: 3. The semiconductor device according to claim 1, wherein Ti, TiW, Ta, Cr, Al
Any one of or a laminated adhesive metal layer and Ni,
A semiconductor device comprising a barrier metal layer formed of any one of Pt, Pd, Cu, W, and Mo or a stacked layer. 4. The semiconductor device according to claim 1, wherein said metal-plated bump is formed by forming an organic resin layer on a passivation film formed on said semiconductor substrate, and forming a metal plating on an opening of said organic resin layer. And a structure in which the organic resin layer is left. 5. The method of manufacturing a semiconductor device according to claim 1, wherein said organic resin layer is used as a mask for selective plating at the time of plating.