JP2005123649A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2005123649A
JP2005123649A JP2004372562A JP2004372562A JP2005123649A JP 2005123649 A JP2005123649 A JP 2005123649A JP 2004372562 A JP2004372562 A JP 2004372562A JP 2004372562 A JP2004372562 A JP 2004372562A JP 2005123649 A JP2005123649 A JP 2005123649A
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bump
layer
semiconductor device
forming
intermediate layer
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JP4702827B2 (en
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Goro Nakaya
吾郎 仲谷
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Rohm Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which includes a pad having a passivation structure with high resistance to moisture and high reliability. <P>SOLUTION: The semiconductor device includes a semiconductor substrate formed with a desired element region, an electrode pad formed so as to come in contact with the surface of the semiconductor substrate or a wiring layer formed on the surface of the semiconductor substrate, and a bump formed on the surface of the electrode pad via an intermediate layer, wherein a resin insulating film formed on a periphery portion of at least the bump so as to cover an interface between the bump and the intermediate layer which are exposed on the side of the bump is included. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体装置およびその製造方法に関し、特に、電極パッド上に形成されるバンプ周辺のパッシベーションに関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to passivation around a bump formed on an electrode pad.

ＶＬＳＩ（超大規模集積回路）等の半導体装置を製造する際に、電極パッド上に形成されるバンプ周辺のパッシベーション構造は極めて重要であり、信頼性を維持しつつ生産性の向上を図るために種々の努力がなされている。   When manufacturing a semiconductor device such as a VLSI (very large scale integrated circuit), the passivation structure around the bump formed on the electrode pad is extremely important, and it is various in order to improve productivity while maintaining reliability. Efforts have been made.

近年、ポリイミド樹脂をパッシベーション膜に用いた構造が、種々提案されている。その一例として、図１５に示すように、半導体基板１表面、あるいは前記半導体基板表面に形成された配線層にコンタクトするように形成されたアルミニウム層からなる電極パッド２と、この上層を覆う窒化シリコン膜３に形成されたコンタクトホールＨ内に中間層４としてのＴｉＷ層を介して金のバンプ６を形成したものがある。この金のバンプはめっきの際のシード層５となるようにスパッタリングで形成された薄い金層上に形成されており、この金のバンプ６の周りには、パッシベーション膜としてのポリイミド樹脂膜７が形成されている。   In recent years, various structures using a polyimide resin as a passivation film have been proposed. As an example, as shown in FIG. 15, an electrode pad 2 made of an aluminum layer formed so as to contact the surface of the semiconductor substrate 1 or a wiring layer formed on the surface of the semiconductor substrate, and silicon nitride covering the upper layer In some cases, gold bumps 6 are formed in a contact hole H formed in the film 3 through a TiW layer as an intermediate layer 4. This gold bump is formed on a thin gold layer formed by sputtering so as to become a seed layer 5 in plating, and a polyimide resin film 7 as a passivation film is formed around the gold bump 6. Is formed.

ところで、この構造は以下に示すような製造工程を経て形成される。   By the way, this structure is formed through the following manufacturing process.

まず、素子領域の形成されたシリコン基板１表面に配線層（図示せず）および層間絶縁膜（図示せず）を形成し、フォトリソグラフィにより、スルーホール（図示せず）を形成する。この後、アルミニウム層を蒸着し、フォトリソグラフィにより、配線（図示せず）および電極パッド２をパターニングする。そしてこの上層に窒化シリコン膜３を形成し、フォトリソグラフィにより、パターニングし、電極パッド２の周縁は窒化シリコン膜で覆われるように電極パッド２の中央部にコンタクトホールＨを形成する。（図１６）   First, a wiring layer (not shown) and an interlayer insulating film (not shown) are formed on the surface of the silicon substrate 1 where the element region is formed, and a through hole (not shown) is formed by photolithography. Thereafter, an aluminum layer is deposited, and wiring (not shown) and the electrode pad 2 are patterned by photolithography. Then, a silicon nitride film 3 is formed as an upper layer and patterned by photolithography, and a contact hole H is formed in the center of the electrode pad 2 so that the periphery of the electrode pad 2 is covered with the silicon nitride film. (Fig. 16)

この後、図１７に示すように、パッシベーション膜としてのポリイミド樹脂膜７を形成し、これをパターニングすることにより、図１８に示すように、電極パッド２を露呈せしめる。   Thereafter, as shown in FIG. 17, a polyimide resin film 7 as a passivation film is formed and patterned to expose the electrode pad 2 as shown in FIG.

そしてアルミニウム層が表面に露呈していると腐蝕しやすいため、図１９に示すように、この上層にスパッタリング法によりバリア層となるチタンタングステンＴｉＷ膜を中間層４として形成した後、ボンディングパッドとなる金層５を形成する。   Since the aluminum layer is easily corroded when exposed on the surface, as shown in FIG. 19, a titanium tungsten TiW film serving as a barrier layer is formed as an intermediate layer 4 on the upper layer by a sputtering method, and then becomes a bonding pad. A gold layer 5 is formed.

この後、図２０に示すように、フォトリソグラフィにより、この金層５および中間層４をパターニングする。従って、パッド層５の端縁とポリイミド樹脂膜７の端縁とが一致するのが望ましいが、マスク精度を考慮すると、一致させるのは難しいという問題がある。一方、パッシベーション膜７上に金層５および中間層４がのりあげるとショートなどの問題が生じ易いという問題がある。このため、フォトリソグラフィの精度を考慮して、パターニングがなされる。   Thereafter, as shown in FIG. 20, the gold layer 5 and the intermediate layer 4 are patterned by photolithography. Therefore, it is desirable that the edge of the pad layer 5 and the edge of the polyimide resin film 7 coincide with each other, but there is a problem that it is difficult to make them coincide in consideration of the mask accuracy. On the other hand, when the gold layer 5 and the intermediate layer 4 are lifted on the passivation film 7, there is a problem that a problem such as a short circuit easily occurs. For this reason, patterning is performed in consideration of the accuracy of photolithography.

更に図２１に示すように、この金層５上に電気めっきによりめっき層６を形成しバンプを形成する。   Further, as shown in FIG. 21, a plating layer 6 is formed on the gold layer 5 by electroplating to form bumps.

この方法では上述したように、パッシベーション膜を構成するポリイミド樹脂膜とバンプを構成する金層６との間に隙間が生じることになり、酸化され易いＴｉＷ表面が露呈することになり、腐蝕が生じ易く、パッシベーション効果を良好に発揮し得ず、信頼性が低下するという問題がある。   In this method, as described above, a gap is formed between the polyimide resin film constituting the passivation film and the gold layer 6 constituting the bump, and the TiW surface that is easily oxidized is exposed, and corrosion occurs. There is a problem that it is easy, the passivation effect cannot be exhibited well, and the reliability is lowered.

このように、従来のパッド構造では、パッシベーション膜とバンプとの間の隙間から、水分などが侵入し、アルミニウムなどの電極パッドに腐蝕が生じ易く、信頼性を維持するのが困難であるという問題があった。   As described above, in the conventional pad structure, moisture or the like enters from the gap between the passivation film and the bump, and the electrode pad such as aluminum is easily corroded, and it is difficult to maintain the reliability. was there.

この発明は、前記実情に鑑みてなされたもので、水分に対する耐性が高く信頼性の高いパッシベーション構造をもつパッドを有する半導体装置を提供することを目的とする。   The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device having a pad having a highly reliable passivation structure that is highly resistant to moisture.

本発明の第１では、半導体装置は、所望の素子領域の形成された半導体基板と、前記半導体基板表面、あるいは前記半導体基板表面に形成された配線層にコンタクトするように形成された電極パッドと、前記電極パッド表面に酸化性材料を含む中間層を介して形成されたバンプと、前記バンプの側面に露呈する、前記バンプと前記中間層との界面の酸化を防止すべく、少なくとも前記バンプの周辺部を覆う樹脂絶縁膜と、を含む。かかる構成によれば、樹脂絶縁膜がバンプの側面に露呈する、前記バンプと前記中間層との界面を覆うように、形成されているため、下地の電極パッドや中間層が露呈することなく、樹脂絶縁膜で被覆されており信頼性の向上を図ることが可能となる。なおここで中間層とはＴｉＷのようなバリアメタル層あるいは密着性層あるいは、めっきの下地を構成する下地層等を含むものとする。そして、これらは腐食性あるいは酸化され易い材料であるため、界面を樹脂被覆することにより、確実にパッシベーション効果を発揮させることができる。   According to a first aspect of the present invention, a semiconductor device includes a semiconductor substrate on which a desired element region is formed, and an electrode pad formed so as to contact the semiconductor substrate surface or a wiring layer formed on the semiconductor substrate surface. In order to prevent oxidation of the bumps formed on the electrode pad surface through an intermediate layer containing an oxidizing material and the interface between the bumps and the intermediate layer exposed on the side surfaces of the bumps, at least the bumps And a resin insulating film covering the periphery. According to such a configuration, the resin insulating film is exposed on the side surface of the bump, so as to cover the interface between the bump and the intermediate layer, so that the underlying electrode pad and intermediate layer are not exposed, Since it is covered with a resin insulating film, the reliability can be improved. Here, the intermediate layer includes a barrier metal layer such as TiW or an adhesive layer, or a base layer constituting a base of plating. Since these are materials that are corrosive or easily oxidized, the passivation effect can be surely exhibited by coating the interface with a resin.

望ましくは、この半導体装置は、前記中間層上に形成されたシード層をさらに含む。   Preferably, the semiconductor device further includes a seed layer formed on the intermediate layer.

望ましくは、前記樹脂絶縁膜はポリイミド樹脂膜である。かかる構成によれば、ポリイミド樹脂膜を用いることにより、バンプ周縁の表面の絶縁とパッシベーション効果を備えた信頼性の高いパッド構造を得ることが可能となる。また形成が容易である。   Preferably, the resin insulating film is a polyimide resin film. According to this configuration, by using the polyimide resin film, it is possible to obtain a highly reliable pad structure having insulation on the surface of the bump periphery and a passivation effect. Moreover, formation is easy.

望ましくは、前記中間層はチタンタングステン（ＴｉＷ）層を含む。かかる構成によれば、チタンタングステン（ＴｉＷ）層は特に酸化され易く界面が露呈していると劣化を招き易いという欠点があるが、本発明によれば、容易に信頼性の高いバンプ構造を得ることが可能となる。   Preferably, the intermediate layer includes a titanium tungsten (TiW) layer. According to such a configuration, the titanium tungsten (TiW) layer has a drawback that it is easily oxidized and easily deteriorates when the interface is exposed. According to the present invention, a highly reliable bump structure is easily obtained. It becomes possible.

望ましくは、前記バンプは金からなる。かかる構成によれば、ボンディング性が良好で信頼性の高い半導体装置を得ることが可能となる。   Preferably, the bump is made of gold. According to such a configuration, it is possible to obtain a highly reliable semiconductor device with good bonding properties.

望ましくは、前記電極パッドは、アルミニウムを含む金属膜からなる。アルミニウム層は特に酸化され易く界面が露呈していると劣化を招き易いという欠点があるが、かかる構成によれば、容易に信頼性の高いバンプ構造を得ることが可能となる。   Preferably, the electrode pad is made of a metal film containing aluminum. The aluminum layer has a drawback that it is particularly easily oxidized and easily deteriorates when the interface is exposed. According to such a configuration, it is possible to easily obtain a highly reliable bump structure.

望ましくは、前記電極パッドは、銅薄膜である。銅層は特に酸化され易く界面が露呈していると劣化を招き易いという欠点があるが、かかる構成によれば、容易に信頼性の高いバンプ構造を得ることが可能となる。   Preferably, the electrode pad is a copper thin film. The copper layer is particularly susceptible to oxidation and has the disadvantage of easily degrading when the interface is exposed. According to such a configuration, it is possible to easily obtain a highly reliable bump structure.

望ましくは、前記バンプは半田ボールからなり、中間層はクロム層、シード層はニッケル層からなり、さらに、前記半田ボールと前記ニッケル層との界面が融着されている。かかる構成によれば、バンプが通常の柱状突起である場合のみならず、半田ボールで構成されている場合にも有効な信頼性を得ることが可能となる。中間層はクロム層、シード層はニッケル層からなる場合、ニッケルやクロムは酸化されやすいが、この構造によれば、界面からの酸化も防止される。   Preferably, the bump is made of a solder ball, the intermediate layer is made of a chromium layer, the seed layer is made of a nickel layer, and the interface between the solder ball and the nickel layer is fused. According to such a configuration, it is possible to obtain effective reliability not only when the bump is a normal columnar protrusion but also when the bump is formed of a solder ball. When the intermediate layer is made of a chromium layer and the seed layer is made of a nickel layer, nickel and chromium are easily oxidized, but this structure also prevents oxidation from the interface.

さらにまた望ましくは、前記半導体装置は複数のバンプを具備しており、これら複数のバンプのうち第１のバンプを介して、他の半導体チップがフェースダウンで接続されており、第２のバンプを介して、ボンディングワイヤの一端が接続されこのボンディングワイヤの他端を介して電気的接続が実現される。かかる構成によれば図２０に示すように、複数の半導体チップを積層して実装することができる。   More preferably, the semiconductor device includes a plurality of bumps, and another semiconductor chip is connected face down via the first bump among the plurality of bumps. Thus, one end of the bonding wire is connected, and electrical connection is realized through the other end of the bonding wire. According to such a configuration, a plurality of semiconductor chips can be stacked and mounted as shown in FIG.

本発明の方法は、所望の素子領域の形成された半導体基板表面、あるいは前記半導体基板表面に形成された配線層にコンタクトするように電極パッドを形成する工程と、前記電極パッド表面に酸化性材料を含む中間層を形成する工程と、フォトリソグラフィにより、バンプ形成領域に窓を有するレジストパターンを形成する工程と、前記レジストパターンの窓から露呈する前記中間層の上側にバンプを形成する工程と、前記バンプをマスクとして、前記中間層をパターニングする工程と、前記バンプの側面で、前記バンプと前記中間層との界面を覆うように、少なくとも前記バンプの周辺部に樹脂絶縁膜を形成する工程と、を含む。かかる構成によれば、バンプを形成したのち、樹脂絶縁膜を形成しているため、バンプ周縁を良好に覆うことが可能となる。   The method of the present invention includes a step of forming an electrode pad so as to contact a surface of a semiconductor substrate on which a desired element region is formed or a wiring layer formed on the surface of the semiconductor substrate, and an oxidizing material on the surface of the electrode pad. A step of forming an intermediate layer including a step of forming a resist pattern having a window in a bump formation region by photolithography, a step of forming a bump on the upper side of the intermediate layer exposed from the window of the resist pattern, Patterning the intermediate layer using the bump as a mask, and forming a resin insulating film at least on the periphery of the bump so as to cover the interface between the bump and the intermediate layer on the side surface of the bump; ,including. According to such a configuration, since the resin insulating film is formed after the bump is formed, it is possible to satisfactorily cover the bump periphery.

望ましくは、この方法は、前記中間層表面にシード層を形成する工程をさらに含み、前記バンプを形成する工程では、前記レジストパターンの窓から露呈するシード層表面にめっき法によりバンプを形成し、前記中間層をパターニングする工程では、前記バンプをマスクとしてシード層もパターニングする。   Preferably, the method further includes a step of forming a seed layer on the surface of the intermediate layer, and in the step of forming the bump, a bump is formed on the surface of the seed layer exposed from the window of the resist pattern by a plating method, In the step of patterning the intermediate layer, the seed layer is also patterned using the bump as a mask.

望ましくは、前記樹脂絶縁膜を形成する工程は、前記界面よりも高いレベルまで形成する工程である。かかる構成によれば、樹脂絶縁膜を良好に形成することが可能となる。   Preferably, the step of forming the resin insulating film is a step of forming to a level higher than the interface. With this configuration, it is possible to satisfactorily form the resin insulating film.

望ましくは、前記樹脂絶縁膜を形成する工程は、ポリイミド樹脂膜を塗布する工程を含む。かかる構成によれば、樹脂絶縁膜がポリイミド樹脂膜であるため、形成が容易でかつパッシベーション効果も高い表面構造を得ることが可能となる。   Preferably, the step of forming the resin insulating film includes a step of applying a polyimide resin film. According to this configuration, since the resin insulating film is a polyimide resin film, it is possible to obtain a surface structure that is easy to form and has a high passivation effect.

望ましくは、前記中間層の形成工程は、スパッタリング法によりチタンタングステン（ＴｉＷ）層を形成する工程を含む。チタンタングステン（ＴｉＷ）層は特に酸化され易く界面が露呈していると劣化を招き易いという欠点があるが、かかる構成によれば、容易に信頼性の高いバンプ構造を得ることが可能となる。   Preferably, the step of forming the intermediate layer includes a step of forming a titanium tungsten (TiW) layer by a sputtering method. The titanium tungsten (TiW) layer has a disadvantage that it is particularly easily oxidized and easily deteriorates when the interface is exposed. With such a configuration, it is possible to easily obtain a highly reliable bump structure.

望ましくは、前記シード層を形成する工程は金層をスパッタリングにより形成する工程を含み、前記バンプの形成工程は、前記シード層上に電気めっきにより金層からなるバンプを形成する工程を含む。かかる構成によれば、より効率よく金バンプを形成することが可能となる。   Preferably, the step of forming the seed layer includes a step of forming a gold layer by sputtering, and the step of forming the bump includes a step of forming a bump made of a gold layer by electroplating on the seed layer. According to such a configuration, gold bumps can be formed more efficiently.

また、望ましくは、前記樹脂絶縁膜を形成する工程が、樹脂絶縁膜を塗布後、アッシングし、前記バンプ表面を露呈させる工程を含む。   Preferably, the step of forming the resin insulating film includes a step of ashing after the resin insulating film is applied and exposing the bump surface.

望ましくは、前記中間層の形成工程はクロム薄膜の形成工程を含み、前記シード層の形成工程はニッケル層をスパッタリングする工程を含み、前記バンプの形成工程は、前記ニッケル層上に半田ボールを載置し、前記ニッケル層と前記半田ボールとの界面を融着する工程と、前記レジストパターンを除去し、前記半田ボールをマスクとして前記中間層およびシード層をパターニングする工程と、前記半田ボールと前記中間層との界面を覆うようにポリイミド樹脂膜を形成する工程とを含む。かかる構成によれば、半田ボールの形成に際し、中間層との界面を露呈することなく、良好に覆うようにポリイミド樹脂膜を形成することができるため、信頼性の高い半田ボールの形成が可能となる。なおここでバンプとは、柱状突起、半田ボールなどの突起をさすものとする。   Preferably, the intermediate layer forming step includes a chromium thin film forming step, the seed layer forming step includes a step of sputtering a nickel layer, and the bump forming step includes mounting a solder ball on the nickel layer. Placing the interface between the nickel layer and the solder ball, removing the resist pattern, patterning the intermediate layer and the seed layer using the solder ball as a mask, the solder ball and the Forming a polyimide resin film so as to cover the interface with the intermediate layer. According to this configuration, when forming the solder ball, the polyimide resin film can be formed so as to cover well without exposing the interface with the intermediate layer, so that it is possible to form a highly reliable solder ball. Become. Here, the bump refers to a protrusion such as a columnar protrusion or a solder ball.

望ましくは、前記ポリイミド樹脂膜を形成する工程は、感光性ポリイミド樹脂を塗布し、露光後、前記半田ボール上のポリイミド樹脂を除去する工程を含む。   Preferably, the step of forming the polyimide resin film includes a step of applying a photosensitive polyimide resin and removing the polyimide resin on the solder ball after exposure.

本発明によれば、樹脂絶縁膜がバンプの側面に露呈する、前記バンプと前記中間層との界面を覆うように、形成されているため、下地の電極パッドや中間層が露呈することなく、樹脂絶縁膜で被覆されており、半導体装置の長寿命化および信頼性の向上を図ることが可能となる。   According to the present invention, the resin insulating film is exposed on the side surface of the bump, so as to cover the interface between the bump and the intermediate layer, so that the underlying electrode pad and intermediate layer are not exposed, Since it is covered with the resin insulating film, it is possible to extend the life and improve the reliability of the semiconductor device.

また、本発明の方法によれば、バンプを形成した後、樹脂絶縁膜を形成するようにしているため、バンプと前記中間層との界面を良好に被覆するように、樹脂絶縁膜を形成することができ、下地の電極パッドや中間層が露呈することなく、樹脂絶縁膜で被覆されており、長寿命化および信頼性の向上を図ることが可能となる。   According to the method of the present invention, since the resin insulating film is formed after the bump is formed, the resin insulating film is formed so as to satisfactorily cover the interface between the bump and the intermediate layer. In addition, the underlying electrode pad and the intermediate layer are covered with the resin insulating film without being exposed, and it is possible to extend the life and improve the reliability.

図１は、本発明の第１の実施形態のパッド構造をもつ半導体装置を示す説明図であり、図２乃至図１１は、本発明の第１の実施形態による半導体装置の製造工程を示す説明図である。この構造では、所望の素子領域の形成されたシリコン基板１表面の電極パッド２と、前記電極パッド表面に中間層４としてのチタンタングステン層を介して形成されたバンプ６とを含み、前記バンプ６の側面に露呈する、前記バンプ６と前記中間層４との界面を覆うように、バンプ６の周辺部にポリイミド樹脂膜７からなる樹脂絶縁膜を形成してなることを特徴とする。   FIG. 1 is an explanatory view showing a semiconductor device having a pad structure according to the first embodiment of the present invention, and FIGS. 2 to 11 are views showing manufacturing steps of the semiconductor device according to the first embodiment of the present invention. FIG. This structure includes an electrode pad 2 on the surface of the silicon substrate 1 on which a desired element region is formed, and a bump 6 formed on the surface of the electrode pad via a titanium tungsten layer as an intermediate layer 4. A resin insulating film made of a polyimide resin film 7 is formed on the periphery of the bump 6 so as to cover the interface between the bump 6 and the intermediate layer 4 exposed on the side surface.

ここで金層５はめっきの下地となる膜であり、ポリイミド樹脂膜７は中間層４と金層５との界面よりも高いレベルまで形成されている。   Here, the gold layer 5 is a film serving as a base for plating, and the polyimide resin film 7 is formed to a level higher than the interface between the intermediate layer 4 and the gold layer 5.

次に本発明の第１の実施形態の半導体装置の製造工程について説明する。まず、図１に示すように、半導体基板１上にフィールド酸化膜（図示せず）を形成したものを用意し、フィールド酸化膜や半導体基板の上に、ポリシリコンゲートを備えたＭＯＳＦＥＴなどの素子領域を形成する。   Next, the manufacturing process of the semiconductor device according to the first embodiment of the present invention will be described. First, as shown in FIG. 1, a device in which a field oxide film (not shown) is formed on a semiconductor substrate 1 is prepared, and an element such as a MOSFET having a polysilicon gate on the field oxide film or the semiconductor substrate is prepared. Form a region.

つぎに、この表面を覆うように、層間絶縁膜（図示せず）を形成する。層間絶縁膜は、たとえばＰＳＧ（リンをドーピングしたシリコン酸化膜）やＢＰＳＧ（ボロンおよびリンをドーピングしたシリコン酸化膜）により構成される。つぎに、層間絶縁膜の上に膜厚５００〜１０００ｎｍのアルミ配線を形成する。このようにして半導体基板１上にアルミ配線まで形成した後、これをパターニングし電極パッド２を形成する。そしてスパッタリング法により窒化シリコン膜３を形成し、前記電極パッド２に開口するように窓を形成する。   Next, an interlayer insulating film (not shown) is formed so as to cover the surface. The interlayer insulating film is made of, for example, PSG (silicon oxide film doped with phosphorus) or BPSG (silicon oxide film doped with boron and phosphorus). Next, an aluminum wiring having a thickness of 500 to 1000 nm is formed on the interlayer insulating film. Thus, after forming even aluminum wiring on the semiconductor substrate 1, this is patterned and the electrode pad 2 is formed. Then, a silicon nitride film 3 is formed by sputtering, and a window is formed so as to open in the electrode pad 2.

つぎに、図２に示すように、この上にスパッタリング法により膜厚２００ｎｍのＴｉＷ層４を形成した後、膜厚２００ｎｍの金層を形成する。   Next, as shown in FIG. 2, after a 200 nm-thick TiW layer 4 is formed thereon by sputtering, a 200 nm-thick gold layer is formed.

そして、図３に示すように、レジストを塗布しフォトリソグラフィによりレジストパターンＲ１を形成する。   Then, as shown in FIG. 3, a resist is applied and a resist pattern R1 is formed by photolithography.

そして、図４に示すように、レジストパターンＲ１をマスクとして電気めっき法によりレジストパターンＲ１から露呈する金層５上に、バンプを形成する。   Then, as shown in FIG. 4, bumps are formed on the gold layer 5 exposed from the resist pattern R1 by electroplating using the resist pattern R1 as a mask.

そして、図５に示すように、レジストパターンＲ１を剥離し、バンプ６を露呈せしめる。   Then, as shown in FIG. 5, the resist pattern R1 is peeled off to expose the bumps 6.

そしてさらに、図６に示すように、窒化シリコン層３上の金層５を除去し得る程度に薄く金のエッチングを行い、さらにこの金製のバンプ６をマスクとして、ＴｉＷ層４をエッチングする。   Further, as shown in FIG. 6, the gold etching is performed thin enough to remove the gold layer 5 on the silicon nitride layer 3, and the TiW layer 4 is etched using the gold bumps 6 as a mask.

この後、図７に示すように、感光性のポリイミド樹脂７を塗布する。このとき、バンプ６上にも薄くポリイミド樹脂７が形成される。   Thereafter, as shown in FIG. 7, a photosensitive polyimide resin 7 is applied. At this time, the polyimide resin 7 is also thinly formed on the bumps 6.

この後、図８に示すように、スクライブライン（図示せず）形成と同時にバンプ上のポリイミド樹脂７も除去するように形成したパターンを用いて露光を行う。ここではポリイミド樹脂７はバンプ上では膜厚が小さいため、必ずしも除去しなくてもよい。   Thereafter, as shown in FIG. 8, exposure is performed using a pattern formed so as to remove the polyimide resin 7 on the bumps simultaneously with the formation of a scribe line (not shown). Here, the polyimide resin 7 is not necessarily removed because the film thickness is small on the bump.

この後、図９に示すように、アッシングを行い、バンプ６上の感光性のポリイミド樹脂７を完全に除去する。   Thereafter, as shown in FIG. 9, ashing is performed to completely remove the photosensitive polyimide resin 7 on the bumps 6.

さらに、図１０に示すように、３００℃３０分の熱処理によりポリイミド樹脂をポストベークし、膜質の向上をはかる。   Furthermore, as shown in FIG. 10, the polyimide resin is post-baked by a heat treatment at 300 ° C. for 30 minutes to improve the film quality.

そして最後に、図１１に示すように、エッチバック工程後に、エッチバック工程において生じたポリマーやパーティクル（ごみ）を除去するために、Ｏ2プラズマ処理工程が実施される。   Finally, as shown in FIG. 11, an O2 plasma treatment process is performed after the etchback process in order to remove polymers and particles (dust) generated in the etchback process.

このようにして、図１に示したようなパッド構造を持つ半導体装置が形成される。   In this way, a semiconductor device having a pad structure as shown in FIG. 1 is formed.

かかる構成によれば、ポリイミド樹脂膜７がバンプの側面に露呈する、前記バンプ６と前記中間層４であるＴｉＷ層との界面を覆うように、形成されているため、下地の電極パッド２や中間層４が露呈することなく、良好にポリイミド樹脂膜で被覆保護されており長寿命で信頼性の高いパッド構造を得ることが可能となる。また、バンプを形成した後、ポリイミド樹脂膜７を形成しているため、効率よく良好に界面を被覆することが可能である。   According to this configuration, the polyimide resin film 7 is formed so as to cover the interface between the bump 6 and the TiW layer as the intermediate layer 4 exposed on the side surface of the bump. Without exposing the intermediate layer 4, it is possible to obtain a pad structure that is well coated and protected with a polyimide resin film and has a long life and high reliability. Moreover, since the polyimide resin film 7 is formed after the bumps are formed, the interface can be efficiently and satisfactorily covered.

なお、前記第１の実施形態においては、金のバンプを形成する場合について説明したが、中間層としてはＴｉ／ＴｉＮなど他の層を用いてもよく、またさらにチタン層やパラジウム層などの密着層を介在させたりすることも可能である。   In the first embodiment, the case where the gold bump is formed has been described. However, as the intermediate layer, other layers such as Ti / TiN may be used, and further, the titanium layer, the palladium layer, or the like is adhered. It is also possible to intervene layers.

さらにまたパッド電極についてもアルミニウムに限定されることなく、アルミニウム−シリコン（Ａｌ−Ｓｉ）、アルミニウム−シリコン−銅（Ａｌ−Ｓｉ−Ｃｕ）、銅（Ｃｕ）等の場合にも適用可能である。   Furthermore, the pad electrode is not limited to aluminum, but can be applied to aluminum-silicon (Al-Si), aluminum-silicon-copper (Al-Si-Cu), copper (Cu), and the like.

次に本発明の第２の実施形態について説明する。図１２は本発明の第２の実施形態の半導体装置を示す図である。前記実施形態では、金バンプについて説明したが、この例では半田バンプについて説明する。   Next, a second embodiment of the present invention will be described. FIG. 12 is a diagram showing a semiconductor device according to the second embodiment of the present invention. In the above embodiment, the gold bump has been described. In this example, the solder bump will be described.

この例では電極パッド２は前記第１の実施形態と同様にアルミニウムで構成したが、この上層に形成される中間層はチタン層からなるバリア層８ａと密着層としてのニッケル層８ｂであり、さらにこの上層にシード層としてのクロム層９を介して半田めっき層からなる半田バンプ１０が形成されるようになっている。   In this example, the electrode pad 2 is made of aluminum as in the first embodiment, but the intermediate layer formed thereon is a barrier layer 8a made of a titanium layer and a nickel layer 8b as an adhesion layer, A solder bump 10 made of a solder plating layer is formed on the upper layer via a chromium layer 9 as a seed layer.

製造工程としては半田の融点が低いため、処理温度を低く設定する必要がある他は前記第１の実施形態と同様である。この場合にもクロム層は酸化され易く界面で腐蝕が進むという問題があったが、本実施形態によれば、容易に信頼性の高いパッド構造を得ることが可能となる。   Since the melting point of the solder is low in the manufacturing process, it is the same as in the first embodiment except that the processing temperature needs to be set low. In this case as well, the chromium layer is easily oxidized and corrodes at the interface. However, according to the present embodiment, a highly reliable pad structure can be easily obtained.

次に本発明の第３の実施形態について説明する。図１３は本発明の第３の実施形態の半導体装置を示す図である。前記第１および第２の実施形態では、バンプについて説明したが、この例では半田ボールを用いた例について説明する。   Next, a third embodiment of the present invention will be described. FIG. 13 is a diagram showing a semiconductor device according to the third embodiment of the present invention. In the first and second embodiments, bumps have been described. In this example, an example using solder balls will be described.

この例では柱状突起をなすバンプをボール状の半田（以下半田ボール１３）としたことを特徴とするもので、Ｔｉ層１１、ニッケル層１２を形成した後、半田ボール１３を載置し、前記ニッケル層と前記半田ボールとの界面を融着した後、ポリイミド樹脂膜７を形成したことを特徴とする。他については前記第１および第２の実施形態と同様である。   In this example, the bumps forming the columnar protrusions are made of ball-shaped solder (hereinafter referred to as solder balls 13). After the Ti layer 11 and the nickel layer 12 are formed, the solder balls 13 are placed, The polyimide resin film 7 is formed after fusing the interface between the nickel layer and the solder ball. Others are the same as those in the first and second embodiments.

次にこのパッド構造を持つ半導体装置の製造工程について説明する。電極パッド２およびこの上層に窒化シリコン膜３を形成したのち、図２に示したのと同様に、この上にスパッタリング法により膜厚３００ｎｍのＴｉ層１１を形成した後、膜厚２００ｎｍのニッケル層１２を形成する。   Next, a manufacturing process of the semiconductor device having this pad structure will be described. After the formation of the electrode pad 2 and the silicon nitride film 3 on the upper layer, a Ti layer 11 having a thickness of 300 nm is formed thereon by a sputtering method in the same manner as shown in FIG. 2, and then a nickel layer having a thickness of 200 nm is formed. 12 is formed.

そして、図３に示したのと同様に、レジストを塗布しフォトリソグラフィによりレジストパターンＲ１を形成する。   Then, as shown in FIG. 3, a resist is applied and a resist pattern R1 is formed by photolithography.

そして、レジストパターンＲ１から露呈するニッケル層１２上に、半田ボール１３を載置し、１５０℃の熱処理を行い、ニッケル層１２と半田ボール１３との界面を融着する。   Then, the solder ball 13 is placed on the nickel layer 12 exposed from the resist pattern R1, and heat treatment at 150 ° C. is performed, and the interface between the nickel layer 12 and the solder ball 13 is fused.

そして、図５に示したのと同様に、レジストパターンＲ１を剥離し、半田ボール６を露呈せしめる。   Then, in the same manner as shown in FIG. 5, the resist pattern R1 is removed, and the solder balls 6 are exposed.

そしてさらに、図６に示したのと同様に、窒化シリコン層３上のＴｉ層およびニッケル層を除去し得る程度に薄くエッチングを行う。   Further, as shown in FIG. 6, etching is performed thin enough to remove the Ti layer and the nickel layer on the silicon nitride layer 3.

この後、図７に示したのと同様に、感光性のポリイミド樹脂７を塗布する。あとは前記第１の実施形態と同様にして、半田ボール１３上のポリイミド樹脂７を除去し、図１３に示したパッド構造が形成される。   Thereafter, a photosensitive polyimide resin 7 is applied in the same manner as shown in FIG. Thereafter, the polyimide resin 7 on the solder balls 13 is removed in the same manner as in the first embodiment, and the pad structure shown in FIG. 13 is formed.

このようにして、長寿命で信頼性の高いパッド構造を得ることが可能となる。   In this way, a long-life and highly reliable pad structure can be obtained.

次に本発明の第４の実施形態について説明する。図１４は本発明の第４の実施形態の半導体装置を示す図である。この例では半導体チップ１上に半導体チップ２０を直接接続する一方で、前記半導体チップ１表面に形成したバンプ６にボンディングワイヤＷを接続し、このボンディングワイヤＷの他端をリードフレームなどの実装基板（図示せず）に接続するようにしている。他部については前記第１乃至第３の実施形態と同様である。   Next, a fourth embodiment of the present invention will be described. FIG. 14 is a diagram showing a semiconductor device according to a fourth embodiment of the present invention. In this example, the semiconductor chip 20 is directly connected to the semiconductor chip 1, while the bonding wires W are connected to the bumps 6 formed on the surface of the semiconductor chip 1, and the other end of the bonding wires W is mounted on a mounting substrate such as a lead frame. (Not shown). Other parts are the same as those in the first to third embodiments.

かかる構成によれば、ボンディングパッドもバンプも同一のバンプ形成工程でポリイミド樹脂７で側面を覆われるように形成されているため、水分に対する耐性が高く信頼性の高い膜の形成が可能となる。   According to this configuration, since the bonding pad and the bump are formed so that the side surfaces are covered with the polyimide resin 7 in the same bump formation process, it is possible to form a highly reliable film with high moisture resistance.

なお、上述の実施形態においては、下地層として、フィールド酸化膜およびこの上に形成されたアルミ配線とにより構成される下地配線層を例に説明したが、下地層はこれに限定されるものではない。この発明における下地層とは、凹凸状表面を有する層全般を意味するものである。   In the above-described embodiment, the base wiring layer composed of the field oxide film and the aluminum wiring formed thereon is described as an example of the base layer. However, the base layer is not limited to this. Absent. The underlayer in this invention means the whole layer which has an uneven surface.

本発明の第１の実施形態による半導体装置を示す図である。1 is a diagram illustrating a semiconductor device according to a first embodiment of the present invention. 本発明の第１の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. 本発明の第１の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. 本発明の第１の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. 本発明の第１の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. 本発明の第１の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. 本発明の第１の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. 本発明の第１の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. 本発明の第１の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. 本発明の第１の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. 本発明の第１の実施形態による半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. 本発明の第２の実施形態による半導体装置を示す図である。It is a figure which shows the semiconductor device by the 2nd Embodiment of this invention. 本発明の第３の実施形態による半導体装置を示す図である。It is a figure which shows the semiconductor device by the 3rd Embodiment of this invention. 本発明の第４の実施形態による半導体装置を示す図である。It is a figure which shows the semiconductor device by the 4th Embodiment of this invention. 従来例の半導体装置を示す図である。It is a figure which shows the semiconductor device of a prior art example. 従来例の半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device of a prior art example. 従来例の半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device of a prior art example. 従来例の半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device of a prior art example. 従来例の半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device of a prior art example. 従来例の半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device of a prior art example. 従来例の半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device of a prior art example.

符号の説明Explanation of symbols

１ シリコン基板
２ 電極パッド
３ 窒化シリコン膜
４ 中間層
５ シード層
６ バンプ
７ ポリイミド樹脂膜
DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Electrode pad 3 Silicon nitride film 4 Intermediate layer 5 Seed layer 6 Bump 7 Polyimide resin film

Claims (18)

所望の素子領域の形成された半導体基板と、
前記半導体基板表面、あるいは前記半導体基板表面に形成された配線層にコンタクトするように形成された電極パッドと、
前記電極パッド表面に酸化性材料を含む中間層を介して形成されたバンプと、
前記バンプの側面に露呈する、前記バンプと前記中間層との界面の酸化を防止すべく、少なくとも前記バンプの周辺部を覆う樹脂絶縁膜と、
を含むことを特徴とする半導体装置。 A semiconductor substrate on which a desired element region is formed;
An electrode pad formed so as to contact the semiconductor substrate surface or a wiring layer formed on the semiconductor substrate surface;
A bump formed on the surface of the electrode pad through an intermediate layer containing an oxidizing material;
A resin insulating film that covers at least the periphery of the bump to prevent oxidation of the interface between the bump and the intermediate layer exposed on the side surface of the bump;
A semiconductor device comprising: 前記中間層上に形成されたシード層をさらに含むことを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, further comprising a seed layer formed on the intermediate layer. 前記樹脂絶縁膜はポリイミド樹脂膜であることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the resin insulating film is a polyimide resin film. 前記中間層はチタンタングステン（ＴｉＷ）層を含むことを特徴とする請求項１乃至３のいずれかに記載の半導体装置。   4. The semiconductor device according to claim 1, wherein the intermediate layer includes a titanium tungsten (TiW) layer. 前記バンプは金からなることを特徴とする請求項１乃至４のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the bump is made of gold. 前記電極パッドは、アルミニウムを含む金属膜からなることを特徴とする請求項１乃至５のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the electrode pad is made of a metal film containing aluminum. 前記電極パッドは、銅薄膜であることを特徴とする請求項１乃至５のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the electrode pad is a copper thin film. 前記バンプは半田ボールからなり、前記中間層はクロム層、前記シード層はニッケル層からなり、前記半田ボールと前記ニッケル層との界面が融着されていることを特徴とする請求項２乃至４および６乃至７いずれかに記載の半導体装置。   5. The bump is made of a solder ball, the intermediate layer is made of a chromium layer, the seed layer is made of a nickel layer, and the interface between the solder ball and the nickel layer is fused. And a semiconductor device according to any one of 6 to 7. 前記半導体装置は複数のバンプを具備しており、これら複数のバンプのうち第１のバンプを介して、他の半導体チップがフェースダウンで接続されており、
第２のバンプを介して、ボンディングワイヤの一端が接続されこのボンディングワイヤの他端を介して電気的接続が実現される請求項１乃至８のいずれかに記載の半導体装置。 The semiconductor device includes a plurality of bumps, and other semiconductor chips are connected face down through the first bump among the plurality of bumps.
9. The semiconductor device according to claim 1, wherein one end of a bonding wire is connected via the second bump, and electrical connection is realized via the other end of the bonding wire. 所望の素子領域の形成された半導体基板表面、あるいは前記半導体基板表面に形成された配線層にコンタクトするように電極パッドを形成する工程と、
前記電極パッド表面に酸化性材料を含む中間層を形成する工程と、
フォトリソグラフィにより、バンプ形成領域に窓を有するレジストパターンを形成する工程と、
前記レジストパターンの窓から露呈する前記中間層の上側にバンプを形成する工程と、
前記バンプをマスクとして、前記中間層をパターニングする工程と、
前記バンプの側面で、前記バンプと前記中間層との界面を覆うように、少なくとも前記バンプの周辺部に樹脂絶縁膜を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 Forming an electrode pad so as to contact a semiconductor substrate surface on which a desired element region is formed or a wiring layer formed on the semiconductor substrate surface;
Forming an intermediate layer containing an oxidizing material on the electrode pad surface;
Forming a resist pattern having a window in a bump formation region by photolithography;
Forming bumps on the upper side of the intermediate layer exposed from the window of the resist pattern;
Patterning the intermediate layer using the bump as a mask;
Forming a resin insulating film on at least the periphery of the bump so as to cover the interface between the bump and the intermediate layer on the side surface of the bump;
A method for manufacturing a semiconductor device, comprising: 前記中間層表面にシード層を形成する工程をさらに含み、
前記バンプを形成する工程では、前記レジストパターンの窓から露呈するシード層表面にめっき法によりバンプを形成し、
前記中間層をパターニングする工程では、前記バンプをマスクとしてシード層もパターニングすることを特徴とする請求項１０に記載の半導体装置の製造方法。 Forming a seed layer on the intermediate layer surface;
In the step of forming the bump, the bump is formed by plating on the seed layer surface exposed from the window of the resist pattern,
11. The method of manufacturing a semiconductor device according to claim 10, wherein in the step of patterning the intermediate layer, the seed layer is also patterned using the bump as a mask. 前記樹脂絶縁膜を形成する工程は、前記界面よりも高いレベルまで形成する工程であることを特徴とする請求項１０又は１１に記載の半導体装置の製造方法。   12. The method of manufacturing a semiconductor device according to claim 10, wherein the step of forming the resin insulating film is a step of forming the resin insulating film to a level higher than the interface. 前記樹脂絶縁膜を形成する工程は、ポリイミド樹脂膜を塗布する工程を含むことを特徴とする請求項１０乃至１２のいずれかに記載の半導体装置の製造方法。   13. The method of manufacturing a semiconductor device according to claim 10, wherein the step of forming the resin insulating film includes a step of applying a polyimide resin film. 前記中間層の形成工程は、スパッタリング法によりチタンタングステン（ＴｉＷ）層を形成する工程を含むことを特徴とする請求項１０乃至１３のいずれかに記載の半導体装置の製造方法。   14. The method of manufacturing a semiconductor device according to claim 10, wherein the intermediate layer forming step includes a step of forming a titanium tungsten (TiW) layer by a sputtering method. 前記シード層を形成する工程は金層をスパッタリングにより形成する工程を含み、
前記バンプの形成工程は、前記シード層上に電気めっきにより金層からなるバンプを形成する工程を含むことを特徴とする請求項１１乃至１４のいずれかに記載の半導体装置の製造方法。 Forming the seed layer includes forming a gold layer by sputtering;
15. The method of manufacturing a semiconductor device according to claim 11, wherein the bump forming step includes a step of forming a gold layer bump on the seed layer by electroplating. 前記樹脂絶縁膜を形成する工程は、樹脂絶縁膜を塗布後、アッシングし、前記バンプ表面を露呈させる工程を含むことを特徴とする請求項１０乃至１５のいずれかに記載の半導体装置の製造方法。   16. The method of manufacturing a semiconductor device according to claim 10, wherein the step of forming the resin insulating film includes a step of ashing after the resin insulating film is applied and exposing the bump surface. . 前記中間層の形成工程はクロム薄膜の形成工程を含み、
前記シード層の形成工程はニッケル層をスパッタリングする工程を含み、
前記バンプの形成工程は、前記ニッケル層上に半田ボールを載置し、前記ニッケル層と前記半田ボールとの界面を融着する工程と、
前記レジストパターンを除去し、前記半田ボールをマスクとして前記中間層およびシード層をパターニングする工程と、
前記半田ボールと前記中間層との界面を覆うようにポリイミド樹脂膜を形成する工程と、
を含むことを特徴とする請求項１３に記載の半導体装置の製造方法。 The intermediate layer forming step includes a chromium thin film forming step,
The step of forming the seed layer includes a step of sputtering a nickel layer,
The bump forming step includes placing a solder ball on the nickel layer and fusing the interface between the nickel layer and the solder ball;
Removing the resist pattern and patterning the intermediate layer and the seed layer using the solder balls as a mask;
Forming a polyimide resin film so as to cover an interface between the solder ball and the intermediate layer;
The method of manufacturing a semiconductor device according to claim 13, comprising: 前記ポリイミド樹脂膜を形成する工程は、感光性ポリイミド樹脂を塗布し、露光後、前記半田ボール上のポリイミド樹脂を除去する工程を含む請求項１７に記載の半導体装置の製造方法。
The method of manufacturing a semiconductor device according to claim 17, wherein the step of forming the polyimide resin film includes a step of applying a photosensitive polyimide resin and removing the polyimide resin on the solder balls after exposure.
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