JPH03112135A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH03112135A JPH03112135A JP1251675A JP25167589A JPH03112135A JP H03112135 A JPH03112135 A JP H03112135A JP 1251675 A JP1251675 A JP 1251675A JP 25167589 A JP25167589 A JP 25167589A JP H03112135 A JPH03112135 A JP H03112135A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal
- bump electrode
- pad
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 63
- 239000002184 metal Substances 0.000 claims abstract description 63
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 239000011521 glass Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 239000005368 silicate glass Substances 0.000 claims description 4
- 239000010931 gold Substances 0.000 abstract description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052737 gold Inorganic materials 0.000 abstract description 10
- 230000004888 barrier function Effects 0.000 abstract description 7
- 229910052681 coesite Inorganic materials 0.000 abstract description 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 229910052682 stishovite Inorganic materials 0.000 abstract description 4
- 229910052905 tridymite Inorganic materials 0.000 abstract description 4
- 238000010276 construction Methods 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 29
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 29
- 238000010438 heat treatment Methods 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Abstract
Description
【発明の詳細な説明】
〔概要〕
配線接続構造とその製造方法に関し、
半導体装置の信頼性を低下させることなく、製作期間を
短縮して、低価格化するごとを目的とし、その構造は、
基板上に複数層の金属膜からなるパッド部を設けて、該
金属膜上に少なくとも金属バンプ電極またはボンディン
グワイヤーのいずれか一方を接続してなることを特徴と
する。[Detailed Description of the Invention] [Summary] Regarding a wiring connection structure and its manufacturing method, the purpose is to shorten the manufacturing period and reduce the cost without reducing the reliability of a semiconductor device.
A pad section made of a plurality of layers of metal films is provided on a substrate, and at least one of a metal bump electrode or a bonding wire is connected to the metal film.
その製造方法は、基板上に被着形成したパッド部を構成
する第１金属膜上に酸化シリコン膜を被覆し、該酸化シ
リコン膜上にガラス膜を被覆して熱処理する工程、次い
で、前記酸化シリコン膜とガラス膜とをエツチングして
第１金属ｎりに達する第１の開口を形成する工程、
次いで、前記第１の開口内に露出した第１金属膜上に第
２金属膜を形成し、該第２金属膜上に窒化シリコン膜を
被覆し、該窒化シリコン膜上に燐シリケートガラス膜を
被覆して熱処理する工程、次いで、前記ガラス膜と窒化
シリコン膜とをエツチングして前記第１の開口上の第２
金属膜に達する第２の開口を形成する工程が含まれてな
ることを特徴とする。The manufacturing method includes a step of coating a first metal film constituting a pad portion formed on a substrate with a silicon oxide film, covering the silicon oxide film with a glass film and heat-treating the silicon oxide film, and then heat-treating the silicon oxide film. forming a first opening reaching the first metal layer by etching the silicon film and the glass film; then, forming a second metal film on the first metal film exposed in the first opening; , covering the second metal film with a silicon nitride film, covering the silicon nitride film with a phosphorus silicate glass film and heat-treating the same; then etching the glass film and the silicon nitride film to form the first etching film; the second on the opening of
The method is characterized in that it includes a step of forming a second opening that reaches the metal film.
本発明は半導体装置とその製造方法にかかり、そのうち
特に配線接続構造上その製造方法に関する。The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly relates to a wiring connection structure and a method of manufacturing the same.
半導体チップの配線接続法には種々の接続方式があるが
、ワイヤーボンディングと金属バンブ電極は特に良く用
いられている方式で、その信頼性の高い互換性ある構成
が望まれている。There are various methods for connecting semiconductor chips with wires, but wire bonding and metal bump electrodes are particularly commonly used, and highly reliable and compatible configurations are desired.
［従来の技術〕
バンプ（ｂｕｍｐ ）電極を設けた半導体装置は、ワイ
ヤーをボンディングする必要がなく、ＴＡＢ（Ｔａｐｅ
Ａｕｔｏｍａｔｅｄ Ｂｏｎｄｉｎｇ）技術によって
実装できるために、半導体容器の厚みを薄くできて半導
体容器を偏平な形状にできる利点がある。しかし、一方
、ワイヤーボンディングによる配線接続方式は極めて汎
用されており、同品種の半導体チップをバンブ電極とワ
イヤーボンディングとの両方に使用する場合も多くみら
れる。[Prior Art] Semiconductor devices provided with bump electrodes do not require bonding of wires, and are bonded using TAB (Tape).
Since it can be mounted using Automated Bonding (Automated Bonding) technology, there is an advantage that the thickness of the semiconductor container can be reduced and the semiconductor container can be made into a flat shape. However, on the other hand, the wiring connection method using wire bonding is extremely widely used, and semiconductor chips of the same type are often used for both bump electrodes and wire bonding.
さて、第５図はそのうちの従来の金属バンプ電極部分の
断面図を示しており、図中の記号１は半導体基板、２は
酸化シリコン（ｓｔｏｚ）膜からなる絶縁膜、３はパッ
ド部のアルミニウム膜、４は燐シリケートガラス（ＰＳ
Ｇ）ＪＩＩなどからなるカバー絶縁１１先５はＴｉ （
チタン）とＩ’ｄ （パラジウム）の複合膜からなるバ
リヤメタル膜、６はマツシュルーム型の金（Ａｕ）から
なるバンブ電極（金バンブ電極）である。ここに、バリ
ヤメタル膜はアルミニウム膜３と金バンプ電極６との反
応を抑制するために介在させる膜である。Now, FIG. 5 shows a cross-sectional view of the conventional metal bump electrode part. In the figure, symbol 1 is the semiconductor substrate, 2 is the insulating film made of silicon oxide (STOZ) film, and 3 is the aluminum pad part. Membrane 4 is phosphorus silicate glass (PS
G) Cover insulation 11 tip 5 made of JII etc. is Ti (
A barrier metal film is made of a composite film of (titanium) and I'd (palladium), and 6 is a bump electrode (gold bump electrode) made of bamboo-shaped gold (Au). Here, the barrier metal film is a film interposed to suppress the reaction between the aluminum film 3 and the gold bump electrode 6.
ところで、上記のように、通常、金属バンブ電極を有す
る半導体装置は１層のパッド部のアルミニウム膜３上に
バリヤメタル膜を介してバンブ電極６を形成しており、
これは出来るだけ凹凸のない平坦なアルミニウム膜３上
にバンブ電極６を設けて、金属バンブ電極による配線接
続を高倍転化したいためである。By the way, as mentioned above, normally in a semiconductor device having a metal bump electrode, the bump electrode 6 is formed on the aluminum film 3 of one layer of the pad portion with a barrier metal film interposed therebetween.
This is because it is desired to provide the bump electrode 6 on the flat aluminum film 3 with as few irregularities as possible, and to increase the wiring connection efficiency by the metal bump electrode.
一方、ワイヤーボンディング接続構造の半導体装置の場
合には、２層、３層などの多層からなるパッド部のアル
ミニウム膜上にワイヤーをボンディングして接続してお
り、これはボンディング時の押圧によって基板ダメージ
や膜剥離などが起こらないように、厚いパッド部を設け
て、その上にボンディングしたいためである。On the other hand, in the case of a semiconductor device with a wire bonding connection structure, the wire is bonded onto the aluminum film of the pad part consisting of multiple layers such as two or three layers, and the pressure during bonding may damage the substrate. This is because it is desired to provide a thick pad section and perform bonding on it to prevent film peeling and the like from occurring.
しかし、そのように、金属バンプ電極接続とワイヤーボ
ンディング接続との接続構造がカバー絶縁膜下のパッド
部の構造まで相違してくることは、受注後の製作期間が
長くかかり、また、予定見込み生産の場合には製品を多
く貯蔵してコストアップに繋がるという欠点がある。However, the difference in the connection structure between the metal bump electrode connection and the wire bonding connection, even down to the structure of the pad under the cover insulating film, means that the production period after receiving the order is long, and the expected production In this case, a disadvantage is that a large amount of product is stored, leading to an increase in costs.
本発明はこのような問題点を低減させて、半導体装置の
信頼性を低下させることな（、製作期間を短縮して、低
価格化（コストダウン）することを目的とした接続の互
換性ある半導体装置とその製造方法を提案するものであ
る。The present invention reduces these problems and provides compatible connections for the purpose of reducing the reliability of semiconductor devices (shortening the manufacturing period and reducing costs). This paper proposes a semiconductor device and its manufacturing method.
［課題を解決するための手段］
その課題は、基板上に複数層の金属■りからなるパッド
部を設けて、該金属膜上に少なくとも金属バンブ電極ま
たはボンディングワイヤーのいずれか一方を接続してな
る構造を具備している半導体装置によって解決される。[Means for solving the problem] The problem is to provide a pad portion made of multiple layers of metal on a substrate, and connect at least one of a metal bump electrode or a bonding wire to the metal film. The problem is solved by a semiconductor device having a structure as follows.
且つ、その製造方法は、基板上に被着形成したパッド部
を構成する第１金属膜上に酸化シリコン膜を被覆し、該
酸化シリコン膜上にガラス膜を被覆して熱処理する工程
、
次いで、前記酸化シリコン膜とガラス膜とをエツチング
して第１金属膜に達する第１の開口を形成する工程、
次いで、前記第１の開口内に露出した第１金属膜上に第
２金属膜を形成し、該第２金属膜上に窒化シリコン膜を
被覆し、該窒化シリコン膜上に燐シリケートガラス膜を
被覆して熱処理する工程、次いで、前記ガラス膜と窒化
シリコン膜とをエツチングして前記第１の開口上の第２
金属膜に達する第２の開口を形成する工程が含まれてい
ることを特徴とする。The manufacturing method includes the steps of: coating a first metal film constituting a pad portion formed on a substrate with a silicon oxide film; covering the silicon oxide film with a glass film; and heat-treating the silicon oxide film. forming a first opening reaching the first metal film by etching the silicon oxide film and the glass film; then, forming a second metal film on the first metal film exposed in the first opening; a step of covering the second metal film with a silicon nitride film, covering the silicon nitride film with a phosphorus silicate glass film and heat-treating the same, and then etching the glass film and the silicon nitride film to form the first 2nd above opening of 1
The method is characterized in that it includes a step of forming a second opening that reaches the metal film.
［作用］
即ち、本発明は、パッド部を複数層の金属膜で構成し、
そのパッド部上に金属バンプ電極またはボンディングワ
イヤーを接続した構造にする。[Function] That is, the present invention configures the pad portion with a plurality of layers of metal films,
A metal bump electrode or bonding wire is connected to the pad portion.
且つ、そのパッド部の平坦化のために、複数層のパッド
部形成工程において積層毎に絶縁膜を被覆し、且つ、熱
処理を加える。In addition, in order to flatten the pad portion, each layer is covered with an insulating film and subjected to heat treatment in the step of forming the pad portion in multiple layers.
そうすれば、パッド部を構成する複数層からなる金属膜
は平坦化されて、その上に金属バンプ電極を形成しても
問題なく、また、ボンディングワイヤーを形成してもダ
メージや剥離がな゛（て、その信頬性が維持され、しか
も、製作期間の短縮、低価格化することができる。In this way, the multi-layered metal film that makes up the pad section will be flattened, and there will be no problem in forming metal bump electrodes on it, and there will be no damage or peeling even when bonding wires are formed. (In this way, the credibility can be maintained, and the production period can be shortened and the price can be lowered.)
［実施例］ 以下、図面を参照して実施例によって詳細に説明する。[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.
第１図は本発明にかかる金属バンプ電極部分の断面図を
示しており、ｌは半導体基板、２はＳｉＯ２膜、５はＴ
ｉ膜とＰｄ膜からなるバリヤメタル膜。FIG. 1 shows a cross-sectional view of a metal bump electrode portion according to the present invention, where l is a semiconductor substrate, 2 is a SiO2 film, and 5 is a T
Barrier metal film consisting of i film and Pd film.
６は金バンプ電極、 １１はパッド部の第１アルミニウ
ム膜（金属膜）、１２はパッド部の第２アルミニウム膜
（金属膜）、２１はＳｉＯ□膜、２２はＰＳＧ膜。6 is a gold bump electrode, 11 is a first aluminum film (metal film) of a pad portion, 12 is a second aluminum film (metal film) of a pad portion, 21 is a SiO□ film, and 22 is a PSG film.
２３は窒化シリコン（Ｓｉｓ Ｎａ ）膜、２４はＰＳ
Ｇ膜である。図のように、パッド部のアルミニウム膜は
２層に積層されているが、パッド部上面が平坦になって
いるため金属バンプ電極を形成しても接続の信顛性は低
下せず、また、多層のパッド部であるからダメージ、剥
離がなくワイヤーをボンディングすることができる。そ
の２層のアルミニウム膜の平坦化は１層毎に絶縁膜を被
■ｌ・し、且つ、熱処理しながら積層すれば得られ、そ
の形成方法は後述する。23 is a silicon nitride (SisNa) film, 24 is a PS
It is a G film. As shown in the figure, the aluminum film on the pad part is laminated in two layers, but since the top surface of the pad part is flat, the reliability of the connection does not deteriorate even if a metal bump electrode is formed. Since it is a multi-layered pad part, wires can be bonded without damage or peeling. Planarization of the two-layer aluminum film can be achieved by covering each layer with an insulating film and laminating the films while heat-treating them, and the method for forming the same will be described later.
第２図は第１図に示す金属バンプ電極の代わりにワイヤ
ーボンディングした、本発明にかかるワイヤーボンディ
ング部分の断面図を示しており、第１図に示す断面図部
分においてバリヤメタル膜５、金バンプ電極６を形成す
ることなく、アルミニウムまたは金からなるボンディン
グワイヤー７を接着した断面図である。ただＳｉｚ Ｎ
ａ膜２３．ＰＳＧ膜２４の開口部の広さは相違する場合
があり、ワイヤーをボンディングする場合に面積を広く
することもあるが、これは最終形成工程であるから製作
期間に影響することは少ない。FIG. 2 shows a cross-sectional view of a wire-bonded part according to the present invention in which wire bonding is performed instead of the metal bump electrode shown in FIG. 1. In the cross-sectional view part shown in FIG. 6 is a cross-sectional view in which a bonding wire 7 made of aluminum or gold is bonded without forming a bonding wire 6. FIG. Just Size N
a membrane 23. The width of the opening in the PSG film 24 may vary, and the area may be increased when bonding wires, but since this is the final forming step, it does not affect the manufacturing period.
上記のように、本発明によれば金バンブ電極とワイヤー
ボンディングとの互換性が得られ、金属バンプ電極また
はボンディングワイヤーのいずれか一方または両方を接
続した半導体装置が形成できて、しかも、いずれの接続
方式も高信頼性が維持される。As described above, according to the present invention, compatibility between gold bump electrodes and wire bonding can be obtained, and a semiconductor device can be formed in which either one or both of metal bump electrodes and bonding wires are connected. The connection method also maintains high reliability.
次に、本発明にかかる製造方法の工程順断面図を第３図
（ａ）〜（ｅ）に示しており、その概要を順を追って説
明する。Next, step-by-step sectional views of the manufacturing method according to the present invention are shown in FIGS. 3(a) to 3(e), and an outline thereof will be explained step by step.
第３図（ａ）参照；まず、半導体基板１のＳｉＯ□膜２
上にアルミニウム膜をスパック法で被着した後、フォト
プロセスを適用してパターンニングして第１アルミニウ
ム膜１１のパターン（パッド部）を形成し、その上に化
学気相成長（ＣＶＤ）法によってＳｉＯ２膜２１膜上１
ＰＳＧ膜２２を被着した後、５００℃以下で熱処理する
。そうすれば、アルミニウムは溶融しないが、内部スト
レスが緩和されて、同時に接触抵抗が低下する。且つ、
固いＳｉＯ□膜２１で被覆されているためにアルミニウ
ム膜のヒロックなどの発生が抑えられる。ヒロックとは
熱処理または電流によるアルミニウム原子の移動で発生
する突起物のことである。Refer to FIG. 3(a); First, the SiO□ film 2 of the semiconductor substrate 1
After depositing an aluminum film thereon by the spackle method, patterning is performed by applying a photo process to form a pattern (pad portion) of the first aluminum film 11, and then a pattern (pad portion) of the first aluminum film 11 is formed by chemical vapor deposition (CVD). SiO2 film 21 film top 1
After depositing the PSG film 22, heat treatment is performed at 500° C. or lower. In this way, the aluminum will not melt, but the internal stress will be relieved and the contact resistance will be reduced at the same time. and,
Since it is covered with the hard SiO□ film 21, the occurrence of hillocks in the aluminum film can be suppressed. Hillocks are protrusions that occur due to the movement of aluminum atoms due to heat treatment or electric current.
第３図（ｂ）参照；次いで、フォトプロセスを適用して
Ｓｉｎ、膜２１とＰＳＧ膜２２を同時にパターンニング
して開口部１５を形成する。開口は、反応ガスとしてＣ
Ｆ Ｊ系のものを用いたドライエツチングをおこなう。Refer to FIG. 3(b); Next, by applying a photo process, the Sin film 21 and the PSG film 22 are simultaneously patterned to form the opening 15. The opening allows C as the reactant gas.
Perform dry etching using FJ type material.
なお、ＰＳＧ膜２２は絶縁膜を厚くして、配線容量を減
少させるために被着するものである。Note that the PSG film 22 is deposited to thicken the insulating film and reduce wiring capacitance.
第３図（Ｃ）参照；次いで、再びアルミニウム膜をスパ
ッタ法で被着し、フォトプロセスを適用してパターンニ
ングして第２アルミニウム膜１２のパターン（パッド部
）を形成し、その上にＣＶＤ法によってＳｉ３Ｎｍ膜２
３およびＰＳＧ膜２４を被着した後、５００°Ｃ以下で
熱処理する。そうすれば、上記と同じく、アルミニウム
は熔融せず、内部ストレスが緩和されて、同時に接触抵
抗が低下する。且つ、アルミニウム膜のヒロックなどの
発生が抑えられる。See FIG. 3(C); Next, an aluminum film is deposited again by sputtering, patterned using a photo process to form a pattern (pad part) of the second aluminum film 12, and then CVD Si3Nm film 2 by method
3 and the PSG film 24, heat treatment is performed at 500°C or less. In this case, as described above, the aluminum will not melt, the internal stress will be alleviated, and the contact resistance will be reduced at the same time. In addition, the occurrence of hillocks in the aluminum film can be suppressed.
第３図（ｄ）参照；しかる後、フォトプロセスを適用し
てＰＳＧＪｉ２４を開口した後、全面にバリヤメタル膜
５を被着し、次にレジスト膜マスクを形成して、金バン
プ電極６をメツキ形成し、余分のバリヤメタル膜を除去
する。かくして、金属バンブ電極（直径１００〜２００
ａｍφ、高さ２０〜３０μｍ程度）を形成する。See FIG. 3(d); After that, a photo process is applied to open the PSGJi 24, a barrier metal film 5 is deposited on the entire surface, a resist film mask is formed, and gold bump electrodes 6 are plated. and remove the excess barrier metal film. Thus, metal bump electrodes (diameter 100-200
amφ, height of about 20 to 30 μm).
第３図（ｅ）参照；また、ワイヤーをボンディングする
場合には、フォトプロセスを適用してＰＳＧ膜２４を開
口した後、ボンディングワイヤー７を接着する。Refer to FIG. 3(e); when bonding wires, a photo process is applied to open the PSG film 24, and then the bonding wire 7 is bonded.
このようにすれば、金バンプ電極、ワイヤーボンディン
グのいずれの接続方式も高い信頼性が得られる。In this way, high reliability can be obtained with either the gold bump electrode or wire bonding connection method.
次に、第４図は本発明にかかる他の金属バンプ電極部分
の断面図を示している。即ち、本例はパッド部のアルミ
ニウム膜を３層に積層した構造で、１１、１２．１３が
第１アルミニウム膜、第２アルミニウム膜、第３アルミ
ニウム膜であり、その他の部材は第１図と同一部位に同
一記号が付けである。Next, FIG. 4 shows a sectional view of another metal bump electrode portion according to the present invention. That is, this example has a structure in which the aluminum film of the pad part is laminated in three layers, 11, 12, and 13 are the first aluminum film, the second aluminum film, and the third aluminum film, and the other members are as shown in FIG. The same parts have the same symbols.
即ち、各層のアルミニウム膜は積層する毎に熱処理して
平坦化しており、このように構成すればパッド部が更に
平坦になって、本例は多層配線構造に好適な構成である
。That is, the aluminum film of each layer is heat-treated and planarized each time it is laminated, and with this configuration, the pad portion becomes even more flat, and this example is suitable for a multilayer wiring structure.
なお、上記実施例はパッド部の金属膜をアルミニウム膜
としているが、その他のパッド材料、例えば、Ｔｉ膜に
よってパッド部を構成する構造に適用することもできる
。In the above embodiment, the metal film of the pad portion is an aluminum film, but the present invention can also be applied to a structure in which the pad portion is made of other pad materials, for example, a Ti film.
［発明の効果コ
以上の説明から明らかなように、本発明によれば金属バ
ンプ電極、ボンディングワイヤーのいずれの方式に切り
換えて接続しても高信頬化した接続構造が得られ、半導
体装置の製作期間が短縮できて、且つ、低価格化するこ
とができる。[Effects of the Invention] As is clear from the above explanation, according to the present invention, a connection structure with high reliability can be obtained regardless of whether the connection is made using a metal bump electrode or a bonding wire, and the connection structure of the semiconductor device can be improved. The manufacturing period can be shortened and the price can be reduced.
第１図は本発明にかかる金属バンプ電極部分の断面図、
第２図は本発明にかかるワイヤーボンディング部分の断
面図、
第３図（ａ）〜（ｅ）は本発明にかかる製造方法の工程
順断面図、
第４図は本発明にかかる他の金属バンプ電極部分の断面
図、
第５図は従来の金属バンプ電極部分の断面図である。
図において、
１は半導体基板、
２はＳｉｎ、膜（絶縁膜）、
３はアルミニウム膜（パッド部）、
４はＰＳＧ膜（絶縁膜）、
５はバリヤメタル膜、
６は金バンプ電極（金属バンブ電極）
７はボンディングワイヤー
１１は第１アルミニウム膜（パッド部）１２は第２アル
ミニウム膜（パッド部）１３は第３アルミニウム膜（パ
ッド部）１５は開口部、
２１はＳｉ０ｇ膜（絶縁膜）、
２３はＳｉ３ Ｎ４膜（絶縁膜）、
２２、２４はＰＳＧ膜（絶縁膜）
を示している。Fig. 1 is a cross-sectional view of a metal bump electrode portion according to the present invention, Fig. 2 is a cross-sectional view of a wire bonding portion according to the present invention, and Fig. 3 (a) to (e) are steps of a manufacturing method according to the present invention. 4 is a sectional view of another metal bump electrode portion according to the present invention, and FIG. 5 is a sectional view of a conventional metal bump electrode portion. In the figure, 1 is a semiconductor substrate, 2 is a Sin film (insulating film), 3 is an aluminum film (pad part), 4 is a PSG film (insulating film), 5 is a barrier metal film, and 6 is a gold bump electrode (metal bump electrode). ) 7 is the bonding wire 11 is the first aluminum film (pad part) 12 is the second aluminum film (pad part) 13 is the third aluminum film (pad part) 15 is the opening, 21 is the Si0g film (insulating film), 23 22 and 24 indicate a Si3N4 film (insulating film), and PSG films (insulating film).
Claims (2)
て、該金属膜上に少なくとも金属バンプ電極またはボン
ディングワイヤーのいずれか一方を接続してなる構造を
具備していることを特徴とする半導体装置。(1) A pad section made of multiple layers of metal films is provided on a substrate, and at least one of a metal bump electrode or a bonding wire is connected to the metal film. semiconductor devices.
属膜上に酸化シリコン膜を被覆し、該酸化シリコン膜上
にガラス膜を被覆して熱処理する工程、次いで、前記酸
化シリコン膜とガラス膜とをエッチングして第１金属膜
に達する第１の開口を形成する工程、 次いで、前記第１の開口内に露出した第１金属膜上に第
２金属膜を形成し、該第２金属膜上に窒化シリコン膜を
被覆し、該窒化シリコン膜上に燐シリケートガラス膜を
被覆して熱処理する工程、次いで、前記ガラス膜と窒化
シリコン膜とをエッチングして前記第１の開口上の第２
金属膜に達する第２の開口を形成する工程が含まれてな
ることを特徴とするバンプ電極形半導体装置の製造方法
。(2) a step of coating a silicon oxide film on the first metal film constituting the pad portion deposited on the substrate, covering the silicon oxide film with a glass film and heat-treating the silicon oxide film; and a glass film to form a first opening that reaches the first metal film; then, forming a second metal film on the first metal film exposed in the first opening; 2. A step of coating a silicon nitride film on the metal film, and heat-treating the silicon nitride film with a phosphorus silicate glass film, and then etching the glass film and the silicon nitride film to form a silicon nitride film on the first opening. the second of
A method for manufacturing a bump electrode type semiconductor device, comprising the step of forming a second opening reaching a metal film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1251675A JPH03112135A (en) | 1989-09-26 | 1989-09-26 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1251675A JPH03112135A (en) | 1989-09-26 | 1989-09-26 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03112135A true JPH03112135A (en) | 1991-05-13 |
Family
ID=17226346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1251675A Pending JPH03112135A (en) | 1989-09-26 | 1989-09-26 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03112135A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05109731A (en) * | 1991-10-21 | 1993-04-30 | Mitsubishi Electric Corp | Bonding pad |
| JP2009194152A (en) * | 2008-02-14 | 2009-08-27 | Casio Comput Co Ltd | Semiconductor integrated circuit apparatus |
| WO2018168316A1 (en) * | 2017-03-13 | 2018-09-20 | 三菱電機株式会社 | Semiconductor device and method for producing semiconductor device |
-
1989
- 1989-09-26 JP JP1251675A patent/JPH03112135A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05109731A (en) * | 1991-10-21 | 1993-04-30 | Mitsubishi Electric Corp | Bonding pad |
| JP2009194152A (en) * | 2008-02-14 | 2009-08-27 | Casio Comput Co Ltd | Semiconductor integrated circuit apparatus |
| WO2018168316A1 (en) * | 2017-03-13 | 2018-09-20 | 三菱電機株式会社 | Semiconductor device and method for producing semiconductor device |
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