JPS61225836A - Manufacture of wiring of semiconductor device - Google Patents

Manufacture of wiring of semiconductor device

Info

Publication number
JPS61225836A
JPS61225836A JP60068283A JP6828385A JPS61225836A JP S61225836 A JPS61225836 A JP S61225836A JP 60068283 A JP60068283 A JP 60068283A JP 6828385 A JP6828385 A JP 6828385A JP S61225836 A JPS61225836 A JP S61225836A
Authority
JP
Japan
Prior art keywords
wiring
wiring layer
bonding
layer
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60068283A
Other languages
Japanese (ja)
Inventor
Kiyoshi Watabe
渡部　潔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60068283A priority Critical patent/JPS61225836A/en
Publication of JPS61225836A publication Critical patent/JPS61225836A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05559—Shape in side view non conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce a height including an insulation around a bonding pad and avoid disconnection of a bonding wire by a method wherein the second wiring layer is connected to the edge part of the first wiring layer and the other region of the first layer is used as the bonding pad. CONSTITUTION:The first wiring layer 6, which is to be a bonding pad, is covered with a PSG film 7 and a contact hole 21 is drilled in the PSG film 7. The second wiring layer 22 is formed on the PSG film 7 and connection parts 23 and 24 are formed with contact holes 8 and 21. The wiring layer 6 is exposed to form an aperture 25 by etching and a bonding wire 26 is bonded to that exposed part. With this constitution, the height of the edge part 27 around the bonding pad 28 becomes low and the edge part 27 does not touch the wire 26. Therefore, disconnection of the wire 26 is avoided.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の配線製造方法に係わり、特にボン
デングワイヤの断線を防止するためのボンデングパッド
部の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing wiring for a semiconductor device, and particularly to a structure of a bonding pad portion for preventing disconnection of a bonding wire.

近時、半導体装置の集積化にともなって微少化と緻密化
が進み、半導体素子内における複数の配線が立体的に絶
縁膜を介して交叉するクロスオーバ配線が採用されてい
るが、従来このような複数の配線を接続して、その部分
からボンデングワイヤを接続する際には、ボンデングパ
ッド部を複数層の配線層で積層してボンデングパッドを
形成し、更にボンデングバンド部の周囲を絶縁膜で被覆
するために、ボンデングパッド部とそのエツジ部の段差
が大きく、ボンデングワイヤが、このエツジ部に接触し
てボンデングワイヤが断線になることがあり、その改善
が要望されている。In recent years, with the integration of semiconductor devices, miniaturization and densification have progressed, and crossover wiring, in which multiple wirings within a semiconductor element intersect three-dimensionally through an insulating film, has been adopted. When connecting multiple wiring lines and connecting a bonding wire from that part, the bonding pad part is laminated with multiple wiring layers to form the bonding pad, and then the surrounding area of the bonding band part is stacked with multiple wiring layers. In order to cover the bonding pad with an insulating film, there is a large step difference between the bonding pad part and its edge part, and the bonding wire may come into contact with this edge part and break the bonding wire, so there is a need to improve this problem. ing.

〔従来の技術〕[Conventional technology]

第２図（ａ）〜第２図（＠）は、従来のボンデングバッ
ト部を形成をするための要部断面図である。FIG. 2(a) to FIG. 2(@) are sectional views of essential parts for forming a conventional bonding butt part.

この図では、所定の電極の配線を他の電極とクロスオー
バして引き出してボンデングパッドに配線する状態の製
造方法を説明する。In this figure, a manufacturing method will be described in which the wiring of a predetermined electrode is crossed over with other electrodes, drawn out, and wired to a bonding pad.

第２図（ａ）で、基板１があり、その表面に絶縁膜２と
して例えば二酸化シリコン膜があって、電極と接合する
部分３が開口しである。In FIG. 2(a), there is a substrate 1, on the surface of which there is an insulating film 2, such as a silicon dioxide film, and a portion 3 to be bonded to an electrode is open.

第２図（ｂｌは、その表面に第１の配線層として厚みが
１μ−のアルミニウムがスパッタにより被着され、ドラ
イエツチングによって所定のバターニングがなされて、
配線４．５．６がなされたとする。In Figure 2 (bl), aluminum with a thickness of 1 μm is deposited on the surface as a first wiring layer by sputtering, and a predetermined patterning is performed by dry etching.
Assume that wiring 4.5.6 is done.

第２図（Ｃ）は、配線が行われた表面に眉間絶縁物７と
して、燐珪酸ガラス（Ｐ　Ｓ　Ｇ’）をＣＶＤ法により
被着したものであり、第２の配線層と接続すべき所定の
位置にコンタクトホール８．９をドライエツチングによ
って形成するが、特にボンデングバットになるべき配線
６上のコンタクトホールは約１００μｍ角の大きさにす
ると共に、配線５をクロスオーバにするために眉間絶縁
物７によって絶縁する。Fig. 2 (C) shows a case in which phosphosilicate glass (PSG') is deposited as a glabellar insulator 7 on the surface where wiring is performed by CVD method, and it is used as a material to be connected to the second wiring layer. A contact hole 8.9 is formed at a predetermined position by dry etching, and in particular, the contact hole on the wiring 6 which is to become a bonding bat is made to have a size of about 100 μm square, and in order to make the wiring 5 a crossover. Insulation is provided by the glabellar insulator 7.

第２図（ｄ）は、その表面に第２の配線層１０としてア
ルミニウムを厚みが１μ油で被膜したものであり、これ
によって上記のコンタクトホール部８．９で、第１の配
線層と第２の配線層が積層されて接続部１１．１２が形
成され、又配線５はクロスオーバの配線構造となる。In FIG. 2(d), aluminum is coated with oil to a thickness of 1 μm as a second wiring layer 10 on the surface thereof, so that the first wiring layer and the The two wiring layers are stacked to form the connection portions 11 and 12, and the wiring 5 has a crossover wiring structure.

第２図（Ｑ）は、更に表面に保護膜１３を厚みが１μｍ
で被膜したもので、コンタクトホール領域１４では第１
の配線層と第２の配線層が積層されているが、通常この
部分にボンデングワイヤ１５がボンデングによって接続
されている。In Fig. 2 (Q), a protective film 13 is further applied to the surface with a thickness of 1 μm.
In the contact hole region 14, the first
The wiring layer and the second wiring layer are laminated, and a bonding wire 15 is usually connected to this portion by bonding.

このような半導体装置のボンデングバット部では、配線
構造が二層になっているために、保護膜のエツジ部１６
の高さが高くなり、その部分がボンデングワイヤと接触
してボンデングワイヤが断線するという欠点がある。In the bonding butt portion of such a semiconductor device, since the wiring structure is two-layered, the edge portion 16 of the protective film
There is a disadvantage that the height of the bonding wire becomes high and that portion comes into contact with the bonding wire, causing the bonding wire to break.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記の半導体素子で配線がクロスオーバ構造を有する場
合の配線の方法では、ボンデングパッドが二層になるた
めに、絶縁膜の高さが高くなり、そのためにボンデング
ワイヤが絶縁膜に接触してて断線するということが問題
である。In the above-mentioned wiring method when the wiring has a cross-over structure in the semiconductor device, the height of the insulating film is increased because the bonding pad is made of two layers, which causes the bonding wire to come into contact with the insulating film. The problem is that the wire breaks when the wire is turned on.

〔問題を解決するための手段〕[Means to solve the problem]

本発明は、上記問題点を解消した半導体装置の配線方法
を提供するもので、その手段は、クロスオーバ配線がな
される下層の第１の配線と、上層の第２の配線とが積層
接続される半導体装置の配線構造において、下層の第１
の配線層を形成した後、該第１の配線層の所定の領域の
端部に該上層の第２の配線を積層して両者を接続してか
ら、その部分の上部に絶縁被膜をなし、前記所定の領域
のうち、第２の配線層が積層して接続されていない該第
１の配線層の部分をボンデングパッド部としてボンデン
グワイヤを接続する半導体装置の配線製造方法によって
達成できる。The present invention provides a wiring method for a semiconductor device that solves the above-mentioned problems, and the means thereof is such that a first wiring in a lower layer, in which a crossover wiring is made, and a second wiring in an upper layer are stacked and connected. In the wiring structure of a semiconductor device, the first
After forming a wiring layer, a second wiring layer of the upper layer is laminated on an end of a predetermined region of the first wiring layer to connect the two, and then an insulating film is formed on the top of that part, This can be achieved by a wiring manufacturing method for a semiconductor device in which a portion of the first wiring layer which is not connected to the stacked second wiring layer in the predetermined area is used as a bonding pad portion to connect a bonding wire.

〔作用〕[Effect]

本発明は、半導体素子で配線がクロスオーバ構造を有す
る場合のボンデングワイヤ部が第１の配線と第２の配線
の二層構造のため、ボンデングバット部の周囲のエツジ
部が高くなって、そこがボンデングワイヤと接触して断
線するのであるから、第１の配線層の一部分である端部
に、第２の配線を接続して、第１の配線層の他の領域を
ボンデングバット部にすることにより、第１の配線層に
直接ボンデングワイヤを接続することによなり、従って
ボンデングパット部の周囲の絶縁物を含む高さが低くな
って、ボンデングワイヤとの接触を防止するようにした
ものであって、これによりボンデングワイヤの断線を大
幅に低下させることができる。In the present invention, when the wiring has a cross-over structure in a semiconductor device, the bonding wire part has a two-layer structure of the first wiring and the second wiring, so that the edge part around the bonding butt part becomes high. , which will come in contact with the bonding wire and break, so connect the second wiring to the end, which is a part of the first wiring layer, and bond other areas of the first wiring layer. By forming a butt part, the bonding wire can be directly connected to the first wiring layer, and therefore the height including the insulation around the bonding pad part is lowered, making it easier to contact the bonding wire. This prevents the bonding wire from breaking, thereby significantly reducing the chance of bonding wire breaking.

〔実施例〕〔Example〕

第１図（ａ）〜第１図（ｅ）は、本発明の実施例である
半導体素子の配線構造の製造方法を示す断面図である。FIGS. 1(a) to 1(e) are cross-sectional views showing a method of manufacturing a wiring structure of a semiconductor element according to an embodiment of the present invention.

第１図（ａ）と第１図中）は、前記の第２図（ａ）と第
２図（ｂ）と、全く同様であるので説明を省略する。FIG. 1(a) and FIG. 1 middle) are completely the same as FIG. 2(a) and FIG. 2(b) described above, so a description thereof will be omitted.

第１図（Ｃ）で、ボンデングバットになるべき第１の配
線層６上で、その表面に被着されているＰＳＧ膜７に、
約５μｍ角のコンタクトホール２１を設ける。In FIG. 1(C), on the first wiring layer 6 which is to become a bonding butt, on the PSG film 7 deposited on the surface thereof,
A contact hole 21 of approximately 5 μm square is provided.

第１図（ｄ）は、その表面に第２の配線層２２を被膜し
たものであり、それによってコンタクトホール部８．２
１で接続部２３．２４が形成される。In FIG. 1(d), a second wiring layer 22 is coated on its surface, thereby forming a contact hole portion 8.2.
1, a connection 23.24 is formed.

第１図（ｅ）で、ボンデングバットになるべき第１の配
線層まで、エツチングを行って開口部２５を形成して、
その部分にボンデングワイヤ２６をボンデングするが、
この構造ではボンデングバット部２８の周囲のエツジ部
２７が低くなるために、ボンデングワイヤと接触するこ
とがなく、極めて高信頼のワイヤボンデングができるこ
とになる。In FIG. 1(e), etching is performed to form an opening 25 up to the first wiring layer which is to become a bonding bat.
Bonding wire 26 is bonded to that part,
In this structure, since the edge portion 27 around the bonding butt portion 28 is lowered, it does not come into contact with the bonding wire, making it possible to perform extremely reliable wire bonding.

〔発明の効果〕〔Effect of the invention〕

以上、詳細に説明したように、本発明の半導体装置の配
線方法は、ボンデングワイヤの断線のない高信頼性の製
品を供し得るという効果大なるものがある。As described above in detail, the semiconductor device wiring method of the present invention has the great effect of providing a highly reliable product without disconnection of bonding wires.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）〜第１図（ｅ）は、本発明の一実施例であ
る半導体装置の製造方法を示す要部断面図、第２図（ａ
）〜第２図（ｅ）は、従来の半導体装置の製造方法を示
す要部断面図、 図において、 １は基板、　　　　　　２は絶縁膜、 ３は電極と接合部分、　４．５．６は配線、７はＰＳＧ
膜、　　　　２１はコンタクトホール２２は第２の配線
層、　　２３．２４は接続部、２５は開口部、　　　　
　２６はボンデングワイヤ２７はボンデングバット部の
周囲のエツジ部、２８はボンデングバット部、 をそれぞれ示している。 −り Ｏ−−1(a) to 1(e) are sectional views of main parts showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2(a)
) to FIG. 2(e) are cross-sectional views of main parts showing a conventional method for manufacturing a semiconductor device. In the figures, 1 is a substrate, 2 is an insulating film, 3 is an electrode and a bonding part, and 4.5.6 is a wiring. , 7 is PSG
21 is a contact hole 22 is a second wiring layer, 23 and 24 are connection parts, 25 is an opening part,
Reference numeral 26 indicates the edge portion of the bonding wire 27 around the bonding butt portion, and numeral 28 indicates the bonding butt portion. -riO--

Claims (1)

【特許請求の範囲】[Claims] クロスオーバ配線がなされる下層の第１の配線と、上層
の第２の配線とが積層接続される半導体装置の配線構造
において、下層の第１の配線層を形成した後、該第１の
配線層の所定の領域の端部に該上層の第２の配線を積層
して両者を接続してから、その部分の上部に絶縁被膜を
なし、前記所定の領域のうち、第２の配線層が積層して
接続されていない該第１の配線層の部分をボンデングパ
ッド部としてボンデングワイヤを接続することを特徴と
する半導体装置の配線製造方法。In a wiring structure of a semiconductor device in which a first wiring layer in a lower layer and a second wiring layer in an upper layer are stacked and connected to each other for cross-over wiring, after forming the first wiring layer in the lower layer, the first wiring layer is connected to the first wiring layer in the lower layer. A second wiring layer of the upper layer is laminated at the end of a predetermined region of the layer to connect the two, and then an insulating film is formed on the top of the layer, and the second wiring layer of the predetermined region is laminated. A method of manufacturing wiring for a semiconductor device, characterized in that a portion of the first wiring layer that is not stacked and connected is used as a bonding pad portion to connect a bonding wire.
JP60068283A 1985-03-29 1985-03-29 Manufacture of wiring of semiconductor device Pending JPS61225836A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60068283A JPS61225836A (en) 1985-03-29 1985-03-29 Manufacture of wiring of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60068283A JPS61225836A (en) 1985-03-29 1985-03-29 Manufacture of wiring of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61225836A true JPS61225836A (en) 1986-10-07

Family

ID=13369279

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60068283A Pending JPS61225836A (en) 1985-03-29 1985-03-29 Manufacture of wiring of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61225836A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02273930A (en) * 1989-04-17 1990-11-08 Nippon Telegr & Teleph Corp <Ntt> Electrode pad for integrated circuit and manufacture thereof
KR100268858B1 (en) * 1992-09-19 2000-11-01 김영환 Method of forming chip protection film in semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57115838A (en) * 1981-01-09 1982-07-19 Toshiba Corp Semiconductor device
JPS57202749A (en) * 1981-06-08 1982-12-11 Toshiba Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57115838A (en) * 1981-01-09 1982-07-19 Toshiba Corp Semiconductor device
JPS57202749A (en) * 1981-06-08 1982-12-11 Toshiba Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02273930A (en) * 1989-04-17 1990-11-08 Nippon Telegr & Teleph Corp <Ntt> Electrode pad for integrated circuit and manufacture thereof
KR100268858B1 (en) * 1992-09-19 2000-11-01 김영환 Method of forming chip protection film in semiconductor device

Similar Documents

Publication Publication Date Title
US5736791A (en) Semiconductor device and bonding pad structure therefor
JP2002198374A (en) Semiconductor device and its fabrication method
JPS61225836A (en) Manufacture of wiring of semiconductor device
JPS61187262A (en) Semiconductor element
JPH0578180B2 (en)
JPH0230137A (en) Method forming wiring of semiconductor device
JPS6149452A (en) Semiconductor element
JPH0456237A (en) Semiconductor device
JPH02161755A (en) Semiconductor device
JP2000357708A (en) Construction of bonding pad and manufacture of the bonding pad
JPH02123753A (en) Semiconductor device and manufacture thereof
JPH02183536A (en) Semiconductor device
JPS63308924A (en) Semiconductor device
JPH03112135A (en) Semiconductor device and manufacture thereof
JPH03209823A (en) Resin-sealed semiconductor device
JPH02184035A (en) Semiconductor device
JP2800525B2 (en) Semiconductor device
JPH03265140A (en) Semiconductor device and manufacture thereof
JP2770390B2 (en) Semiconductor device
JPH04109654A (en) Semiconductor device and manufacture thereof
KR0167291B1 (en) Electrode wire of semiconductor device
JPH0456239A (en) Semiconductor device
JPS63143826A (en) Semiconductor device
JPS62104138A (en) Semiconductor device
JPS63107141A (en) Manufacture of semiconductor device