JPS57115838A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57115838A
JPS57115838A JP56001980A JP198081A JPS57115838A JP S57115838 A JPS57115838 A JP S57115838A JP 56001980 A JP56001980 A JP 56001980A JP 198081 A JP198081 A JP 198081A JP S57115838 A JPS57115838 A JP S57115838A
Authority
JP
Japan
Prior art keywords
wiring
insulating film
bonding
outermost
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56001980A
Other languages
Japanese (ja)
Inventor
Tsutomu Koyanagi
Tadashi Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56001980A priority Critical patent/JPS57115838A/en
Publication of JPS57115838A publication Critical patent/JPS57115838A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the outermost wiring from corroding earlier than an inner wiring by a method wherein the outermost wiring is constituted of a highly corrosion resistant conductive material and the inner wiring connected to the outermost wiring serves as a bonding pad. CONSTITUTION:A wiring 14 is formed in a semiconductor substrate 11 through an interlayer insulating film 12. The wiring 14 includes a bonding pad 14'. Formed over the wiring 14 across an interlayer insulating film 15 are wirings 171 and 172 made of material with higher anti-corrosion feature than the wiring 14. Provided in the insulating film 15 are contact hole 161 and a bonding window 162. The wiring 172 is connected to the wiring 14 through the hole 161. It is usual with this setup that the wiring 14 is covered with an insulating film 15 protecting the wiring 14 enjoying adequately long service life and reliability thanks to the protection. No faulty bonding of the wiring 172 occurs because the pad 14' serves as a bonding pad for the wiring 172.
JP56001980A 1981-01-09 1981-01-09 Semiconductor device Pending JPS57115838A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56001980A JPS57115838A (en) 1981-01-09 1981-01-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56001980A JPS57115838A (en) 1981-01-09 1981-01-09 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS57115838A true JPS57115838A (en) 1982-07-19

Family

ID=11516665

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56001980A Pending JPS57115838A (en) 1981-01-09 1981-01-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57115838A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61225836A (en) * 1985-03-29 1986-10-07 Fujitsu Ltd Manufacture of wiring of semiconductor device
JPS62232940A (en) * 1986-04-02 1987-10-13 Nec Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61225836A (en) * 1985-03-29 1986-10-07 Fujitsu Ltd Manufacture of wiring of semiconductor device
JPS62232940A (en) * 1986-04-02 1987-10-13 Nec Corp Semiconductor device

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