JPS6482656A - Sealing structure for hybrid integrated circuit - Google Patents

Sealing structure for hybrid integrated circuit

Info

Publication number
JPS6482656A
JPS6482656A JP62242179A JP24217987A JPS6482656A JP S6482656 A JPS6482656 A JP S6482656A JP 62242179 A JP62242179 A JP 62242179A JP 24217987 A JP24217987 A JP 24217987A JP S6482656 A JPS6482656 A JP S6482656A
Authority
JP
Japan
Prior art keywords
pads
chip
wirings
integrated circuit
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62242179A
Other languages
Japanese (ja)
Inventor
Masaru Kurisaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62242179A priority Critical patent/JPS6482656A/en
Publication of JPS6482656A publication Critical patent/JPS6482656A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To prevent pads from corroding due to the absorption of moisture of a sheath resin by providing insulating films on the surfaces of an IC chip, wirings and a mounting substrate. CONSTITUTION:A die pad 8 for placing an IC chip 2 formed with a hybrid integrated circuit and a plurality of wire bonding pads 9 are provided on a mounting substrate 1. A passivation film 3 and a plurality of aluminum pads 4 are provided on the surface of the chip 2. After the pads 4 are connected to the pads 9 by wirings 5, SiO2 oxide films 6 are formed on the surfaces of the chip 2 including the pads 4, the wirings 5 and the substrate 1. Thereafter, the substrate 1 is covered with the wirings 5 and the chip 2, and a sheath resin 7 is formed. Even if moisture is invaded from externally to the resin 7, the films 6 can prevent the pads 4 of the chip 2 from corroding.
JP62242179A 1987-09-25 1987-09-25 Sealing structure for hybrid integrated circuit Pending JPS6482656A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62242179A JPS6482656A (en) 1987-09-25 1987-09-25 Sealing structure for hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62242179A JPS6482656A (en) 1987-09-25 1987-09-25 Sealing structure for hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS6482656A true JPS6482656A (en) 1989-03-28

Family

ID=17085484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62242179A Pending JPS6482656A (en) 1987-09-25 1987-09-25 Sealing structure for hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS6482656A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04337638A (en) * 1991-05-14 1992-11-25 Murata Mfg Co Ltd Protecting method of electronic parts
JPH09106998A (en) * 1995-06-05 1997-04-22 He Holdings Inc Dba Hughes Electron Manufacture of sealed chip-on-board electronic module
US5869905A (en) * 1996-01-15 1999-02-09 Kabushiki Kaisha Toshiba Molded packaging for semiconductor device and method of manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04337638A (en) * 1991-05-14 1992-11-25 Murata Mfg Co Ltd Protecting method of electronic parts
JPH09106998A (en) * 1995-06-05 1997-04-22 He Holdings Inc Dba Hughes Electron Manufacture of sealed chip-on-board electronic module
US5869905A (en) * 1996-01-15 1999-02-09 Kabushiki Kaisha Toshiba Molded packaging for semiconductor device and method of manufacturing the same
US6258632B1 (en) 1996-01-15 2001-07-10 Kabushiki Kaisha Toshiba Molded packaging for semiconductor device and method of manufacturing the same

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