JPH04337638A - Protecting method of electronic parts - Google Patents
Protecting method of electronic partsInfo
- Publication number
- JPH04337638A JPH04337638A JP3139606A JP13960691A JPH04337638A JP H04337638 A JPH04337638 A JP H04337638A JP 3139606 A JP3139606 A JP 3139606A JP 13960691 A JP13960691 A JP 13960691A JP H04337638 A JPH04337638 A JP H04337638A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- defects
- type electronic
- protective film
- electronic component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 25
- 230000001681 protective effect Effects 0.000 claims abstract description 18
- 238000007789 sealing Methods 0.000 claims abstract description 6
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims abstract description 5
- 230000007547 defect Effects 0.000 abstract description 11
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 18
- 238000010586 diagram Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000011179 visual inspection Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【0001】0001
【産業上の利用分野】この発明は、電子部品の保護方法
、更に詳しくは、アセンブリ工程で発生し、かつ有効な
検査が行なえないマイクロクラックなどによる故障を減
少させることができる保護方法に関するものである。[Field of Industrial Application] This invention relates to a method for protecting electronic components, and more particularly, to a method for protecting electronic components that can reduce failures caused by microcracks that occur during assembly processes and which cannot be effectively inspected. be.
【0002】0002
【従来の技術】多くの電子部品の場合、その製造工程に
はアセンブリ工程(組立工程)が含まれ、アセンブリ工
程による機械的ストレスなどにより電子部品の信頼性を
低下させる場合がある。2. Description of the Related Art In the case of many electronic parts, the manufacturing process includes an assembly process, and the reliability of the electronic parts may be lowered due to mechanical stress caused by the assembly process.
【0003】図4乃至図6はチップ型半導体電子部品の
アセンブリ工程のいくつかの例を示しており、図4は半
導体ウエハ1を多数のチップ型電子部品2に分割する作
業であり、スクライバ,ブレーカによってチップ型電子
部品2に機械的ストレスが加わることになる。FIGS. 4 to 6 show some examples of assembly processes for chip-type semiconductor electronic components, and FIG. 4 shows the process of dividing a semiconductor wafer 1 into a large number of chip-type electronic components 2, in which a scriber, Mechanical stress is applied to the chip type electronic component 2 by the breaker.
【0004】図5はチップ電子部品2をパッケージにダ
イボンドで接着する作業であり、ダイボンダによってチ
ップ電子部品2に機械的ストレスが加わる。FIG. 5 shows the process of bonding a chip electronic component 2 to a package by die bonding, and mechanical stress is applied to the chip electronic component 2 by the die bonder.
【0005】また、図6はチップ型電子部品2の電極と
パッケージ3の外部電極4を金属ワイヤ5等により電気
的接続をとるワイヤボンド作業であり、ワイヤボンダに
よって機械的ストレスが加わる。Further, FIG. 6 shows a wire bonding operation in which the electrodes of the chip type electronic component 2 and the external electrodes 4 of the package 3 are electrically connected by a metal wire 5 or the like, and mechanical stress is applied by the wire bonder.
【0006】上記のように、チップ型電子部品2に機械
的なストレスが加わると割れや欠け等の不良が生じるが
目視などの方法で発見できる不良は、通常目視検査等の
工程内検査によって除外できる。As mentioned above, when mechanical stress is applied to the chip-type electronic component 2, defects such as cracks and chips occur, but defects that can be detected by visual inspection are usually eliminated by in-process inspection such as visual inspection. can.
【0007】[0007]
【発明が解決しようとする課題】しかしながら、マイク
ロクラック等の目視による発見が難しい不良は、そのま
ま見逃されて製品となり、市場での故障原因となるとい
う問題がある。[Problems to be Solved by the Invention] However, there is a problem in that defects such as microcracks that are difficult to detect visually are overlooked and become a cause of product failure in the market.
【0008】そこで、この発明は、アセンブリ工程で発
生し、かつ有効な検査が行なえないマイクロクラック等
の不良に帰因する故障を減少させ、信頼性を向上させる
ことができる電子部品の保護方法を提供することを目的
とする。Therefore, the present invention provides a method for protecting electronic components that can reduce failures caused by defects such as microcracks that occur during the assembly process and cannot be effectively inspected, and improve reliability. The purpose is to provide.
【0009】[0009]
【課題を解決するための手段】上記のような課題を解決
するため、この発明は、パッケージのベース表面に実装
した電子部品の封止工程前に、電子部品の外表面に保護
膜を形成する方法を採用したものである。[Means for Solving the Problems] In order to solve the above problems, the present invention forms a protective film on the outer surface of the electronic component before the sealing process of the electronic component mounted on the base surface of the package. This method was adopted.
【0010】0010
【作用】パッケージのベース表面に電子部品を実装した
後、この電子部品の外表面に、プラズマCVD法によっ
て保護膜を塗布形成し、この後電子部品の封止工程を行
なえば、電子部品は保護膜によって保護され、マイクロ
クラックが存在してもそれによる不良の発生を抑え、故
障を減少させることができる。[Operation] After electronic components are mounted on the base surface of the package, a protective film is applied and formed on the outer surface of the electronic components using the plasma CVD method, and then a sealing process is performed to protect the electronic components. Protected by the film, even if microcracks exist, the occurrence of defects due to them can be suppressed and failures can be reduced.
【0011】[0011]
【実施例】以下、この発明の実施例を添付図面の図1乃
至図3に基づいて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to FIGS. 1 to 3 of the accompanying drawings.
【0012】図面はチップ型電子部品のアセンブリ工程
としてワイヤボンディングの例を示し、図1のようにパ
ッケージのベース11の表面に実装したチップ型電子部
品12はその電極がパッケージのベース11の電極と金
属ワイヤ13によって接続される。The drawings show an example of wire bonding as an assembly process for chip-type electronic components, and as shown in FIG. Connected by metal wire 13.
【0013】上記チップ型電子部品12の外表面及びパ
ッケージのベース11の表面に、図で矢印で示すように
プラズマCVD法を用いて、例えばシリコン窒化膜の如
き保護膜15を付着形成する。A protective film 15, such as a silicon nitride film, is deposited on the outer surface of the chip-type electronic component 12 and the surface of the package base 11 using the plasma CVD method as shown by the arrows in the figure.
【0014】保護膜15の形成に用いる材料としては、
SiN、SiO、SiON等を例示することができ、ま
た保護膜15を形成するプラズマCVD法は、SiN等
の耐環境性のよい薄膜が容易に形成でき、しかもステッ
プカバレッジがよく、微細構造の隅々にまで成膜可能で
あり、更に成膜温度が比較的低いため、耐熱性の低いア
センブリ材料にも通用可能であるという利点がある。Materials used for forming the protective film 15 include:
For example, SiN, SiO, SiON, etc. can be used, and the plasma CVD method for forming the protective film 15 can easily form a thin film with good environmental resistance such as SiN, and has good step coverage and can be used to Furthermore, since the film formation temperature is relatively low, it has the advantage that it can be applied to assembly materials with low heat resistance.
【0015】上記のように保護膜15を形成した後、図
2の如くチップ型電子部品12を覆うようにパッケージ
11上へキャップ16を取付け、チップ型電子部品12
の封止工程を行ない、この後図3のように、ウェットあ
るいはドライエッチングにより外部端子14上に付着し
ている保護膜を除去する。After forming the protective film 15 as described above, the cap 16 is attached onto the package 11 so as to cover the chip type electronic component 12 as shown in FIG.
After that, as shown in FIG. 3, the protective film adhering to the external terminal 14 is removed by wet or dry etching.
【0016】パッケージ11上に封止されたチップ型電
子部品12はその外表面がシリコン窒化膜の如き保護膜
15で覆われて保護されているため、アセンブリ工程で
マイクロクラック等の目視による発見ができないような
部分があっても、マイクロクラック等の進行を保護膜1
5によって抑えることができ、これによってマイクロク
ラック等の不良に帰因する故障の発生を減少させること
ができる。Since the outer surface of the chip-type electronic component 12 sealed on the package 11 is protected by being covered with a protective film 15 such as a silicon nitride film, it is difficult to visually detect microcracks or the like during the assembly process. Protective film 1 prevents the progression of microcracks, etc. even if there are areas that cannot be prevented.
5, thereby reducing the occurrence of failures due to defects such as microcracks.
【0017】なお、図示実施例は、ベース11とキャッ
プ16による封止を示したが、例えばリードフレームを
使用したモールドパッケージの場合も同様に扱える。Although the illustrated embodiment shows sealing using the base 11 and cap 16, a molded package using a lead frame, for example, can be similarly handled.
【0018】[0018]
【発明の効果】以上のように、この発明によると、パッ
ケージのベース上に封止前の電子部品の外表面に保護膜
を形成するようにしたので、電子部品にマイクロクラッ
ク等の目視検査による除外が困難な不良が存在していて
も、保護膜によってマイクロクラック等の進行を抑える
ことができ、従ってマイクロクラック等の不良が原因と
なる故障の発生を減少させ、電子部品の信頼性を向上さ
せることができる。As described above, according to the present invention, a protective film is formed on the outer surface of the electronic component before being sealed on the base of the package. Even if there are defects that are difficult to eliminate, the protective film can suppress the progression of microcracks, etc., thereby reducing the occurrence of failures caused by defects such as microcracks, and improving the reliability of electronic components. can be done.
【図1】この発明の保護方法の保護膜形成工程を示す説
明図。FIG. 1 is an explanatory diagram showing a protective film forming step of the protection method of the present invention.
【図2】この発明の保護方法の封止工程を示す説明図。FIG. 2 is an explanatory diagram showing the sealing process of the protection method of the present invention.
【図3】この発明の保護方法における外部電極上の保護
膜除去工程を示す説明図。FIG. 3 is an explanatory diagram showing a step of removing a protective film on an external electrode in the protection method of the present invention.
【図4】半導体ウエハのスクライブを示す説明図。FIG. 4 is an explanatory diagram showing scribing of a semiconductor wafer.
【図5】チップ型電子部品のダイボンドを示す説明図。FIG. 5 is an explanatory diagram showing die bonding of a chip-type electronic component.
【図6】チップ型電子部品のワイヤボンドを示す説明図
。FIG. 6 is an explanatory diagram showing a wire bond of a chip-type electronic component.
11 パッケージのベース 12 チップ型電子部品 14 外部電極 15 保護膜 16 パッケージのキャップ 11 Package base 12 Chip type electronic components 14 External electrode 15 Protective film 16 Package cap
Claims (2)
子部品の封止工程前に、電子部品の外表面に保護膜を形
成することを特徴とする電子部品の保護方法。1. A method for protecting an electronic component, comprising forming a protective film on the outer surface of the electronic component before a sealing process for the electronic component mounted on the base surface of a package.
って行なわれる請求項1に記載の電子部品の保護方法。2. The method for protecting electronic components according to claim 1, wherein the protective film is formed by a plasma CVD method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3139606A JPH04337638A (en) | 1991-05-14 | 1991-05-14 | Protecting method of electronic parts |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3139606A JPH04337638A (en) | 1991-05-14 | 1991-05-14 | Protecting method of electronic parts |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04337638A true JPH04337638A (en) | 1992-11-25 |
Family
ID=15249202
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3139606A Pending JPH04337638A (en) | 1991-05-14 | 1991-05-14 | Protecting method of electronic parts |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04337638A (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5656659A (en) * | 1979-10-16 | 1981-05-18 | Toshiba Corp | Semiconductor device |
JPS58206129A (en) * | 1982-05-27 | 1983-12-01 | Seiko Epson Corp | Semiconductor device |
JPS6482656A (en) * | 1987-09-25 | 1989-03-28 | Nec Corp | Sealing structure for hybrid integrated circuit |
-
1991
- 1991-05-14 JP JP3139606A patent/JPH04337638A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5656659A (en) * | 1979-10-16 | 1981-05-18 | Toshiba Corp | Semiconductor device |
JPS58206129A (en) * | 1982-05-27 | 1983-12-01 | Seiko Epson Corp | Semiconductor device |
JPS6482656A (en) * | 1987-09-25 | 1989-03-28 | Nec Corp | Sealing structure for hybrid integrated circuit |
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