JPS58206129A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58206129A
JPS58206129A JP57090287A JP9028782A JPS58206129A JP S58206129 A JPS58206129 A JP S58206129A JP 57090287 A JP57090287 A JP 57090287A JP 9028782 A JP9028782 A JP 9028782A JP S58206129 A JPS58206129 A JP S58206129A
Authority
JP
Japan
Prior art keywords
gas
substrate
silicon oxide
nitride film
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57090287A
Other languages
Japanese (ja)
Inventor
Seiichi Iwamatsu
誠一 岩松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP57090287A priority Critical patent/JPS58206129A/en
Publication of JPS58206129A publication Critical patent/JPS58206129A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To maintain a protective effect against external pollutions, and to prevent degradation for a prolonged term of the characteristics of a semiconductor element by connecting a semiconductor chip to a substrate to a lead-frame, etc. and forming a silicon oxide-nitride film to the surface of the substrate to be assembled. CONSTITUTION:The semiconductor element 1 is bonded with the lead-frame while being connected by gold lead wires 3. The surface of the substrate assembled is coated with the silicon oxide-nitride film 4 in approximately 0.5mum thickness, and the surface of the film 4 is resin-molded with an epoxy-resin 5, etc. The silicon oxide-nitride film is coated through a photochemical evaporation method while a mixed gas of monosilane gas and oxygen gas or oxygen nitride gas and ammonia gas is irradiated by ultraviolet rays in a reaction chamber with a quartz window under pressure as heating the substrate.

Description

【発明の詳細な説明】 本発明は半導体装置゛の保禮被膜材料構成に関する。[Detailed description of the invention] The present invention relates to the structure of protective coating materials for semiconductor devices.

従来、半導体チップ°をリード・フレーム等への基板に
結線し、組立てした、組立基板にはシリコン懐化膜か上
横されるのが通例であった。Conventionally, semiconductor chips were connected to a substrate such as a lead frame and assembled, and the assembled substrate was usually covered with a silicone film.

しかし、上ｄ己使来技術では、／リコン窒化腓が外部ｆ
’ｊ染（Ｎαや水）に対する保諌幼果は大なるにも拘わ
らず、逆に、イの保誇効果が、半導体′１ｇｆ表面のｔ
ｉｚｏ、膜に吸紙さＪｒ　ｆｃ）ｉ　（水素）原子を外
部に放出し難くなシ、吸絨水索が止孔捕獲中心の原因と
なり、半導体素子特性を長期的には劣化させるという問
題があった。However, in the conventional technology, the /recon nitride layer is external f
Although the protective effect on 'j dye (Nα and water) is large, on the contrary, the protective effect of A on the surface of semiconductor '1gf
izo, it is difficult to release the (hydrogen) atoms to the outside due to paper absorption in the membrane, and the problem is that the water-absorbing cables become the cause of trapping holes, which deteriorates the characteristics of semiconductor devices in the long term. there were.

本発明は拘る従来技術の欠点をなくシ、外部汚ｉＫ対す
る保−効果を保ちつつ、月４つ、半導体素子表面のＢ１
０ｘＮｋＫ吸蔵された水素原子を放出し易い保睦被膜を
提供することを目的とする。The present invention eliminates the drawbacks of the related prior art, maintains the protection effect against external contamination, and improves the B1 on the surface of the semiconductor element.
The object of the present invention is to provide a protective coating that easily releases hydrogen atoms occluded with 0xNkK.

上記目的を達成するための本発明の基本的な構成は、半
導体装置に於て、半導体チップをリード・フレーム等へ
の基板に結線し、組立てした組立基板表面にはシリコン
酸化・窒化（Ｂ１０ｚＮｙ・オキシナイトライド）膜が
抜機されて成る事を特徴とする。The basic structure of the present invention for achieving the above object is that, in a semiconductor device, a semiconductor chip is connected to a substrate to a lead frame, etc., and silicon oxidation/nitridation (B10zNy/ oxynitride) membrane is removed.

以下、実施例により本発明の詳細な説明する。Hereinafter, the present invention will be explained in detail with reference to Examples.

第１図は本発明による半導体装置の一実施例の断（３）
構造を示す。１は半導体素子であり、２のリード・フレ
ームに半導体素子ｌが接着されると共に、金リード線３
により結線されている。この組立基板表面にシリコン酸
化・窒化膜４が０．５μｍ厚程度に抜機され、その表面
はエポキシ・レジン等でし・ジン・モールドさｔして成
る。FIG. 1 is a cross section (3) of an embodiment of a semiconductor device according to the present invention.
Show the structure. 1 is a semiconductor element, a semiconductor element l is bonded to a lead frame 2, and a gold lead wire 3 is attached to the lead frame 2.
are connected by. A silicon oxide/nitride film 4 is cut out to a thickness of about 0.5 .mu.m on the surface of this assembled substrate, and the surface is then molded with epoxy resin or the like.

この場合、／リコン酸化・窒化膜は、光化学蒸漸法によ
す、ＳｔＨ，（モノ７ラン）ガスと酸素ガス（０！　）
あるいは１化酸素（ＮｔＯ）ガスおよびアンモニア（Ｎ
Ｈｓ　）ガスの混合ガスを１００　Ｔｏｒｒ　。In this case, the /recon oxidation/nitride film is prepared by photochemical vaporization using StH, (mono7 run) gas and oxygen gas (0!).
Alternatively, oxygen monoxide (NtO) gas and ammonia (N
Hs) gas mixture at 100 Torr.

程度の圧力で石英窓をもった反応室内で紫外ＩＩＭを照
射すると共シこ、基板力ロ熱を竹ないながら被着される
。シリコン酸化・窒化膜の酸素およびＳ１木５南電は混
合ガス中のモノンランガスに対する酸素ガス等とアンモ
ニアガスとの混合比によって自由に決駕することができ
る。一般にＦｉむ０χＮｙはｚ＝１、ｙ−１のむＯＮ程
度を用いるが、ν素成分が多い力が外部汚染に対しては
保膿効来は大である。When irradiated with ultraviolet IIM in a reaction chamber with a quartz window at a moderate pressure, the substrate is deposited without causing any heat or heat. Oxygen in the silicon oxide/nitride film and S1 wood 5 can be determined freely by changing the mixing ratio of oxygen gas, etc. and ammonia gas to monolan gas in the mixed gas. In general, a value of z = 1, y - 1 is used for Fi = 0xNy, but a force with a large ν component has a large purulent retention effect against external contamination.

上記の如く、半導体装置の保跪被膜をシリコン酸化・窒
化膜となすことにより、外部汚染に灯してＱま保膿効果
に株ちつつ、半導体素子次回のｋＪｉ（＋。As mentioned above, by using a silicon oxide/nitride film as the protective coating for a semiconductor device, it can protect against external contamination and maintain Q and pus protection effects, while also increasing the semiconductor device's next kJi (+).

膜に吸蔵された水素原子は故出し、半導体菓子特性の長
期父化のない保諌被膜となすことができる効果がある。The hydrogen atoms occluded in the film are ejected, resulting in a protective film that does not deteriorate over time, which is characteristic of semiconductor confectionery.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明にこよる半２４体製１βの一実施例の的
１面構造を示すっ Ｉ　・　・　・半導体巣子　　２　・　・　・　リード
・フレーム３・・・五′ｉ巌電極 ４・・壽７リコン酢化・９化膜 ５・１七−ルドレジン 以　　　上 出願人　株式会社め訪精工合 代理人　升埋土最　上　　柚FIG. 1 shows the target one-sided structure of an embodiment of the semi-24-piece 1β according to the present invention. ...Junior 7 recon acetylation/9 compound film 5/17-ru resin and above Applicant: Mewa Seiko Co., Ltd. Joint Agent Masu Uedo Mogami Yuzu

Claims (1)

【特許請求の範囲】[Claims] 半導体チップをリード・フレーム等への基板に結縁し、
組立てした、組立基板表面にはシリコ７酸化・窒化（ｄ
ｉｏｘＮｙ・オキシナイトライド）膜が破穐されて成る
事を％値とする半導体装置。Bonding semiconductor chips to substrates such as lead frames,
The surface of the assembled substrate is coated with silicon 7 oxidation and nitridation (d
A semiconductor device whose percentage value is that the ioxNy/oxynitride) film is ruptured.
JP57090287A 1982-05-27 1982-05-27 Semiconductor device Pending JPS58206129A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57090287A JPS58206129A (en) 1982-05-27 1982-05-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57090287A JPS58206129A (en) 1982-05-27 1982-05-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS58206129A true JPS58206129A (en) 1983-12-01

Family

ID=13994306

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57090287A Pending JPS58206129A (en) 1982-05-27 1982-05-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58206129A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62160732A (en) * 1986-01-09 1987-07-16 Agency Of Ind Science & Technol Forming method for silicon oxynitride films
JPS63184340A (en) * 1986-09-08 1988-07-29 Nec Corp Semiconductor device
JPH0383365A (en) * 1989-08-28 1991-04-09 Semiconductor Energy Lab Co Ltd Electronic device
JPH04337638A (en) * 1991-05-14 1992-11-25 Murata Mfg Co Ltd Protecting method of electronic parts

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5771137A (en) * 1980-10-22 1982-05-01 Oki Electric Ind Co Ltd Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5771137A (en) * 1980-10-22 1982-05-01 Oki Electric Ind Co Ltd Manufacture of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62160732A (en) * 1986-01-09 1987-07-16 Agency Of Ind Science & Technol Forming method for silicon oxynitride films
JPS63184340A (en) * 1986-09-08 1988-07-29 Nec Corp Semiconductor device
JPH0383365A (en) * 1989-08-28 1991-04-09 Semiconductor Energy Lab Co Ltd Electronic device
JPH04337638A (en) * 1991-05-14 1992-11-25 Murata Mfg Co Ltd Protecting method of electronic parts

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