JPS63216352A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS63216352A
JPS63216352A JP62050615A JP5061587A JPS63216352A JP S63216352 A JPS63216352 A JP S63216352A JP 62050615 A JP62050615 A JP 62050615A JP 5061587 A JP5061587 A JP 5061587A JP S63216352 A JPS63216352 A JP S63216352A
Authority
JP
Japan
Prior art keywords
aluminum
semiconductor chip
wire
pad
aluminum pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62050615A
Other languages
Japanese (ja)
Inventor
Kichiji Ogawa
吉司 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62050615A priority Critical patent/JPS63216352A/en
Publication of JPS63216352A publication Critical patent/JPS63216352A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To enhance the dampproofness of a wire bonding part by a method wherein an aluminum oxide layer is formed on the exposed surface of a wire- bonded aluminum pad by using a dry oxidation method so that a thick oxide film can be formed without a bad influence in a PSG film. CONSTITUTION:A semiconductor chip is mounted on a lead frame; an aluminum pad 2 of the semiconductor chip is wire-bonded; after that, an aluminum oxide layer 5 is formed on the exposed surface of the aluminum pad 2 by using a dry oxidation method. For example, a gold wire 3 is wire-bonded to the aluminum pad 2 on a PSG film 1 covering the surface of the semiconductor chip; after that, the exposed part of the aluminum pad 2 is oxidized by ozone gas 4; aluminum oxide 5 is formed. During this process, the ozone gas 4 is generated after oxygen gas 6 has been introduced to the surface of the semiconductor chip and has been irradiated with ultraviolet rays 7; the ozone oxidation is executed at atmospheric pressure and at a temperature of 350 deg.C. After that, the semiconductor chip is sealed by using a resin and a semiconductor device is completed.

Description

【発明の詳細な説明】 〔腫栗上の利用分野〕 本発明に半導体装置の装造方法に関し、特にワイヤボン
ティング部分の耐湿性を同上し得る製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a manufacturing method that can improve the moisture resistance of a wire bonding portion.

〔従来の技術〕[Conventional technology]

ＩＣあるいはＬＳＩ等の半導体装置を製造する場合、ト
ランジスタやダイオードなどが形成された半導体チップ
を、パッケージングするために。When manufacturing semiconductor devices such as ICs or LSIs, it is used to package semiconductor chips on which transistors, diodes, etc. are formed.

従来次のような組立工程が行なわｎる。即ち、まず第３
図（ａ）の斜視図に示すように、リードフレームのアイ
ランド１１上に半導体チップ１２をマウントし、更に半
導体チップに形成されているアルミニウムパッド１３と
アイランド１１の周囲に配設されたリード１４との間を
金等のボンディングワイヤ１５を介して接続（ワイヤボ
ンディング）する。続いて、熱硬化性樹脂などのトラン
スファーモルトを行ない、第３凶（ｂ）の断面図に示す
ように、所要部分をモールド樹脂層１６で樹脂封止する
。また、ワイヤボンディング後に、パッドの表面にアル
ミニウムの自然酸化膜（自然酸化アルミニウム）よりも
厚いば化アルミニウムを形成するために水蒸気処理など
のウェット敗北を行なう場合もある。Conventionally, the following assembly process is performed. That is, first, the third
As shown in the perspective view of Figure (a), a semiconductor chip 12 is mounted on an island 11 of a lead frame, and aluminum pads 13 formed on the semiconductor chip and leads 14 disposed around the island 11 are mounted on an island 11 of a lead frame. A connection (wire bonding) is made between them via a bonding wire 15 made of gold or the like. Subsequently, transfer molding of a thermosetting resin or the like is performed, and as shown in the cross-sectional view of the third section (b), required portions are resin-sealed with a mold resin layer 16. Further, after wire bonding, wet defeating such as water vapor treatment may be performed in order to form aluminum oxide, which is thicker than the natural oxide film of aluminum (natural aluminum oxide), on the surface of the pad.

〔発明が屏犬しようとする問題点〕[Problems that the invention attempts to address]

上述の従来法でに、パッドのアルミニウム表面１−）、
２０Ａ程度の薄い自然酸化アルミニウムで被われている
のみであって％組立工程で混入するゴミやモールド樹脂
中に含まれる塩素イオン、あるいは耐湿性試験で外部か
ら侵入する塩素イオン等のハロゲンイオンがパッドに作
用し、パッドの腐食を生じ、配線の断線を引きおこすと
いう欠点があった。このような欠点を解決する方法とし
て。In the conventional method described above, the aluminum surface of the pad 1-),
The pad is only covered with a thin layer of natural aluminum oxide of about 20A, and halogen ions such as dust mixed in during the assembly process, chlorine ions contained in the mold resin, or chlorine ions that enter from the outside during the moisture resistance test can be removed from the pad. This has the disadvantage of causing corrosion of the pads and disconnection of the wiring. As a way to solve such shortcomings.

パッド上の酸化アルミニウムを厚くすることが考えらｎ
１水蒸気処理などによるウェット酸化方法が試みられた
。しかし、半導体チップの表面保諌膜としてリンケイ酸
ガラス膜（ＰＳＧ膜）が使用された半導体チップにおい
てに、これ等の酸化過程でＰＳＧ膜からのリンの溶出が
起り、ＰＳＧ＃の模員を劣化させるのみならず、浴出し
たリンが水と反応してリン酸となり、アルミニウム配線
の腐食を引＠起し、配線が断−してしまうという欠点が
あった。I have considered making the aluminum oxide on the pad thicker.
1 Wet oxidation methods such as steam treatment have been attempted. However, in semiconductor chips in which a phosphosilicate glass film (PSG film) is used as a surface protection film, phosphorus elutes from the PSG film during these oxidation processes, degrading the PSG#. Not only that, but the phosphorus released from the bath reacts with water to form phosphoric acid, which causes corrosion of the aluminum wiring and causes the wiring to break.

〔問題点に１％犬するための手段〕 上記問題点に対し不発明では、ワイヤボンディングを行
ったアルミニウムパッドの露出表面に対し、従来性なわ
れた水蒸気による酸化の代わりに。[Means for solving the problem by 1%] In order to solve the above problem, the exposed surface of the aluminum pad that has been wire bonded is oxidized by water vapor instead of the conventional method.

ドライ酸化ｆ２を用いて厚い欧化アルミニウムの保護層
を形成し、水＃気による従来の方法の欠点をなくしてい
る。Dry oxidation f2 is used to form a thick protective layer of European aluminum, eliminating the drawbacks of the traditional method due to water and air.

〔実施例〕〔Example〕

次ＶＣ％不発明を実施例に基づいて説明する。 Next, VC% non-invention will be explained based on an example.

第１図（ａ）　、　（ｂ）に不発明の紺１の実施例とし
てオゾン酸化法を用いた場合の製造方法について説明す
る工程断面図である。まず第１図（ａ）において。FIGS. 1(a) and 1(b) are process sectional views illustrating a manufacturing method using an ozone oxidation method as an example of the inventive navy blue 1. First, in Figure 1(a).

１は半導体チップ表面を仮うＰＳＧ膜、２にアルミニウ
ムのパッド、３はパッド３にワイヤボンディングされた
金線である。このようなワイヤボンディングされたチッ
プに対し、つぎに同図（ｂ）に示すように、アルミニウ
ムパッド２の露出部分をオゾンガス４にエフ酸化し、酸
化アルミニウム５を形成する。ここでオゾンガス４は、
酸素ガス６を半導体チップ表面に導入し、紫外−１７を
照射することにエリ発生させ友。また、オゾン酸化に。1 is a PSG film that covers the surface of the semiconductor chip, 2 is an aluminum pad, and 3 is a gold wire wire-bonded to the pad 3. With respect to such wire-bonded chips, the exposed portions of the aluminum pads 2 are then oxidized with ozone gas 4 to form aluminum oxide 5, as shown in FIG. 2(b). Here, ozone gas 4 is
Oxygen gas 6 is introduced onto the surface of the semiconductor chip, and irradiation with ultraviolet -17 rays is caused. Also for ozone oxidation.

常圧下で３５０℃の温度で行なった。このような条件で
はＰＳＧ映１の膜質を変えることなく、アルミニウムパ
ッド２の露出部分にのみ膜厚８０Ａ程度の酸化アルミニ
ウム５を形成できる。次に、従来の製造方法と同様に、
樹脂で半導体チップを封止して半導体装ｒ１１を完成さ
せた。The test was carried out at a temperature of 350° C. under normal pressure. Under such conditions, aluminum oxide 5 with a thickness of about 80 Å can be formed only on the exposed portion of aluminum pad 2 without changing the film quality of PSG film 1. Next, similar to traditional manufacturing methods,
The semiconductor chip was sealed with resin to complete the semiconductor device r11.

上記実施例により製造された半導体装置でに。In the semiconductor device manufactured according to the above embodiment.

アルミニウムパッド２が、自然酸化アルミニウムエフも
厚い酸化アルミニウム　５、あるいに金製のボンディン
グワイヤ３で仮積されているために内部のアルミニウム
成分は塩素イオン等のノ１０ゲンイオンによる腐食作用
から保護される。従って耐湿性試験においても腐食によ
る惜続不良の発生全防止することができた。Since the aluminum pad 2 is temporarily laminated with thick aluminum oxide 5 or gold bonding wire 3, the internal aluminum component is protected from the corrosive effects of chlorine ions and other ions. Ru. Therefore, even in the moisture resistance test, it was possible to completely prevent poor continuity due to corrosion.

ａ２図に本発明の第２実施例について説明するための断
面図である。第２凶において、ＰＳＧ膜１で被われた半
導体チップ上のアルミニウムのパッド２に対し、ボンデ
ィングワイヤ３を接続した債、アルミニウムパッド２の
露出表面を、放′酸に工り発生させた酸素プラズマ８に
（２）して酸化を行う。この場合、温度３５０”Ｃで、
ＲＦパワー５００ワットで行った。この鹸化条件で、第
１実施例と同様にＰＳＧ膜１の膜質に影響を与えず、７
０Ａ根度の酸化アルミニウムの層５が形成できた。その
後、従来例と同様に樹脂封止全行って半導体装置を完成
させる。Fig. a2 is a sectional view for explaining a second embodiment of the present invention. In the second case, bonding wires 3 were connected to aluminum pads 2 on the semiconductor chip covered with PSG film 1, and the exposed surface of the aluminum pads 2 was treated with free acid to generate oxygen plasma. Oxidation is performed in step 8 (2). In this case, at a temperature of 350"C,
The RF power was 500 watts. Under these saponification conditions, the film quality of the PSG film 1 is not affected and the
A layer 5 of aluminum oxide having a strength of 0A was formed. Thereafter, resin sealing is performed in the same manner as in the conventional example to complete the semiconductor device.

上記方法で製造された半導体装置は、アルミニウムパッ
ドの露出表面が自然酸化膜より厚い酸化アルミニウムの
層で被わ扛ているため、耐湿性試験においても腐食によ
る接続不良の発生全防止することができた。In semiconductor devices manufactured by the above method, the exposed surface of the aluminum pad is covered with a layer of aluminum oxide that is thicker than the natural oxide film, so connection failures due to corrosion can be completely prevented even in moisture resistance tests. Ta.

〔発明の効果〕〔Effect of the invention〕

以上説明した工うに１本発明方法にエフ半導体チップ表
面のＰＳＧ膜に対する患影響なしに、アルミニウムパッ
ドの露出表面を保護する厚いアルミニウムの酸化膜を形
成することができ、よって。According to the method of the present invention as described above, it is possible to form a thick aluminum oxide film that protects the exposed surface of the aluminum pad without affecting the PSG film on the surface of the F semiconductor chip.

アルミニウムパッドとこれに接続したボンディングワイ
ヤの耐湿性の同上がなされ％信頼性の篩い半導体装！１
を提供することができる。The moisture resistance of the aluminum pad and the bonding wire connected to it is the same as above, making it a highly reliable semiconductor device! 1
can be provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）　、　（ｂ）に不発明の第１の実施例の製
造工程全説明するための部分断面図、４２図μ本発明の
第２の実施例を説明するための部分断面図、第３図（ａ
）　、　（ｂｌに従来の半導体装置の製造方法のｇ！造
工程を説明するための図であって２図（ａ）に＠視図、
図（ｂ）に断面図である。 １・・・・・・ＰＳＧｉ、２．１３・・・・・・アルミ
ニウムパッド、３．１５・・・・・・ボンディングワイ
ヤ、４・・・・・・オゾンガス、５・・・・・・酸化ア
ルミニウム、６・・・・・・酸禦ガス、７・・・・・・
紫外凱　８−−−−−−敵累プラズマ％１１・・・・・
・リードフレームのアイランド、１２・・・・・・半導
体チップ、１４・・・・・・リードフレームのリード、
１６・・・・・・モールド樹脂。 ｌ　　　　　　　　　　ｊｊ〜７業列−５そ敦↓　　　
ル　　　↓　　　壷 禎　ｌ　図 筋２図Figures 1(a) and 1(b) are partial sectional views for explaining the entire manufacturing process of the first embodiment of the invention, and Figure 42 is a partial sectional view for explaining the second embodiment of the invention. , Figure 3 (a
), (bl is a diagram for explaining the manufacturing process of the conventional semiconductor device manufacturing method, and FIG. 2(a) is a @ view,
Figure (b) is a cross-sectional view. 1...PSGi, 2.13... Aluminum pad, 3.15... Bonding wire, 4... Ozone gas, 5... Oxidation Aluminum, 6... Acid gas, 7...
Ultraviolet Gai 8--------Enemy plasma% 11...
・Lead frame island, 12... Semiconductor chip, 14... Lead frame lead,
16...Mold resin. l jj ~ 7 business row - 5 sotsu ↓
Le ↓ Tsubosada l Diagram 2

Claims (1)

【特許請求の範囲】[Claims] リードフレームに半導体チップをマウントし、この半導
体チップのアルミニウムパッドにワイヤボンディングを
行った後、前記アルミニウムパッドの露出表面に酸化ア
ルミニウムの層を形成することを含む半導体装置の製造
方法において、前記酸化アルミニウムの層をドライ酸化
法により形成することを特徴とする半導体装置の製造方
法。A method for manufacturing a semiconductor device comprising mounting a semiconductor chip on a lead frame, performing wire bonding to an aluminum pad of the semiconductor chip, and then forming an aluminum oxide layer on an exposed surface of the aluminum pad. 1. A method for manufacturing a semiconductor device, characterized in that the layer is formed by a dry oxidation method.
JP62050615A 1987-03-04 1987-03-04 Manufacture of semiconductor device Pending JPS63216352A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62050615A JPS63216352A (en) 1987-03-04 1987-03-04 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62050615A JPS63216352A (en) 1987-03-04 1987-03-04 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS63216352A true JPS63216352A (en) 1988-09-08

Family

ID=12863878

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62050615A Pending JPS63216352A (en) 1987-03-04 1987-03-04 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS63216352A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0529379A (en) * 1991-07-25 1993-02-05 Mitsubishi Electric Corp Semiconductor device and fabrication thereof
US5565378A (en) * 1992-02-17 1996-10-15 Mitsubishi Denki Kabushiki Kaisha Process of passivating a semiconductor device bonding pad by immersion in O2 or O3 solution
JPH08316267A (en) * 1995-05-17 1996-11-29 Samsung Electron Co Ltd Bonding pad protective film formation of semiconductor chip
JP2010114880A (en) * 2008-11-04 2010-05-20 Samsung Electronics Co Ltd Surface acoustic wave element, surface acoustic wave device and methods for manufacturing the same
CN105826183A (en) * 2015-01-06 2016-08-03 中芯国际集成电路制造(上海)有限公司 Method for reducing crystal defect of bonding pad structure
JP2019106480A (en) * 2017-12-13 2019-06-27 株式会社デンソー Metal member and semiconductor element using metal member, resin-metal composite, semiconductor device, different kind metal composite, and manufacturing method for metal member

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0529379A (en) * 1991-07-25 1993-02-05 Mitsubishi Electric Corp Semiconductor device and fabrication thereof
US5565378A (en) * 1992-02-17 1996-10-15 Mitsubishi Denki Kabushiki Kaisha Process of passivating a semiconductor device bonding pad by immersion in O2 or O3 solution
JPH08316267A (en) * 1995-05-17 1996-11-29 Samsung Electron Co Ltd Bonding pad protective film formation of semiconductor chip
JP2010114880A (en) * 2008-11-04 2010-05-20 Samsung Electronics Co Ltd Surface acoustic wave element, surface acoustic wave device and methods for manufacturing the same
CN105826183A (en) * 2015-01-06 2016-08-03 中芯国际集成电路制造(上海)有限公司 Method for reducing crystal defect of bonding pad structure
JP2019106480A (en) * 2017-12-13 2019-06-27 株式会社デンソー Metal member and semiconductor element using metal member, resin-metal composite, semiconductor device, different kind metal composite, and manufacturing method for metal member

Similar Documents

Publication Publication Date Title
US5595934A (en) Method for forming oxide protective film on bonding pads of semiconductor chips by UV/O3 treatment
JPS63216352A (en) Manufacture of semiconductor device
JPS5917252A (en) Manufacture of semiconductor device
JP2844633B2 (en) Semiconductor die for plastic encapsulation with adhesion promoter
JPH07221259A (en) Semiconductor device and its manufacture
JPH0263148A (en) Semiconductor device
JPS5951139B2 (en) Manufacturing method for resin-encapsulated semiconductor devices
JPH03276736A (en) Manufacture of semiconductor device
JPH06349814A (en) Semiconductor integrated circuit device
US4517734A (en) Method of passivating aluminum interconnects of non-hermetically sealed integrated circuit semiconductor devices
JPS63205930A (en) Manufacture of semiconductor integrated circuit device
JPH0745755A (en) Resin-sealed semiconductor device and manufacture thereof
JPH0529379A (en) Semiconductor device and fabrication thereof
JPH04318944A (en) Semiconductor device sealed with resin
JPH0521653A (en) Resin sealed type semiconductor device
JPH08288447A (en) Lead frame
JPS6010652A (en) Semiconductor device
JPS5817627A (en) Semiconductor integrated circuit device and manufacture thereof
JPH11265939A (en) Semiconductor device and its manufacture
JPS5882534A (en) Semiconductor device
JPH0837182A (en) Semiconductor device and manufacture thereof
JPS59220957A (en) Semiconductor device
JPH0541469A (en) Resin sealed semiconductor device
KR19980025552A (en) Low Stress Semiconductor Chip Package
JPS5852331B2 (en) Semiconductor device and its manufacturing method