JPH0541469A - Resin sealed semiconductor device - Google Patents

Abstract

PURPOSE:To relieve a stress applied to a semiconductor element from a sealing resin so as to enable an assembling facility to automatically recognize patterns and to improve the heat resistance of the element by providing a stress relieving resin layer with recessed sections on the circuit forming surface of the semiconductor element in corresponding to recognition patterns. CONSTITUTION:A stress relieving resin layer 3a is formed on the circuit forming surface 2 of a semiconductor element 1 provided with recognition patterns on the surface 2 and recessed sections 4a1 and 4a2 are provided on the surface of the layer 3a in corresponding to the recognition patterns. A total of two recognition patterns are provided at inner diagonal sections of the outer peripheral section 3 of the rectangular element 1 where bonding pads 10 are arranged. The sizes of the sections 4a1 and 4a2 are made a little smaller than the areas of the patterns. The thickness of the layer 3a at the recessed sections is 5mum at most. Most of the surface 2 can be covered with a resin layer having a thickness of at least 5mum and, at the same time, the pattern recognition in an assembling process can be performed in the recessed section having a thickness of 5mum at most. Therefore, the heat resistance of the element 1 can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device, and more particularly to a resin-encapsulated semiconductor device having a stress relaxation resin layer such as polyimide.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 4, a resin-sealed semiconductor device of this type is used for mounting a semiconductor element on a semiconductor element 1 made of silicon with a silver paste 6 made by mixing silver powder with epoxy resin. Is adhered to the metal die attach portion 7 of the above, the metal lead 8 and the bonding hud of the semiconductor element 1 are electrically connected by the gold wire 5, and the epoxy sealing resin 9 is integrated. There is.

At this time, on the upper surface of the circuit forming surface 2 of the semiconductor element 1, in order to relieve the stress from the sealing resin 9, a thickness of 5 is applied.
A stress relaxation resin layer 3 having a thickness of up to 20 μm is provided except in the vicinity of the bonding pad of the semiconductor element 1. Usually, the stress relaxation resin layer 3 is formed on the upper surface of a semiconductor element in a wafer state by applying a mixture of a polyimide liquid and a filler by a method such as spin coating using a predetermined mask, and then curing, etching and the like. To be done.

[0004]

The conventional resin-encapsulated semiconductor device described above has the following drawbacks.
That is, as the semiconductor element 1 becomes larger (a square of about 7 mm × 7 mm or a rectangle of which the longer side is about 10 mm), the stress also increases. Therefore, the stress relaxation resin layer 3 has to be thicker, and the stress relaxation resin layer 3 is usually 10 μm. The above thickness is required. However, the stress relaxation resin layer contains a large amount of filler in order to bring the thermal expansion coefficient close to that of the encapsulating resin, and the transparency is poor, and the pattern on the semiconductor element cannot be recognized even when exposed to light. In other words, automatic pattern recognition cannot be performed on the semiconductor element used for aligning equipment such as mounting and bonding in the assembly process. In the stress relaxation resin layer currently in practical use, the upper limit of the thickness for such automatic pattern recognition is 5 μm.
It is a degree.

Such recognition patterns for alignment are usually provided at two corners of a square or rectangular semiconductor element, but the stress relaxation resin film is not provided at two corners. Cracks are likely to occur in that part,
There is a problem that the heat resistance is not good.

[0006]

A resin-encapsulated semiconductor device according to the present invention comprises a semiconductor element having a recognition pattern on a circuit formation surface, and a stress relaxation resin layer covering the circuit formation surface of the semiconductor element. In a resin-encapsulated semiconductor device having
A recess corresponding to the recognition pattern is provided on the surface of the stress relaxation resin layer.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing a first embodiment of the present invention, and FIG. 2 is a plan view showing the relationship between a semiconductor element and a stress relaxation resin layer in the first embodiment. Note that FIG.
FIG. 3 is a cross-sectional view taken along the line AA line of FIG. 2.

In this embodiment, a stress relaxation resin layer 3a is provided on the circuit formation surface of the semiconductor element 1 having a recognition pattern formed on the circuit formation surface, and the aforementioned recognition pattern is formed on the surface of the stress relaxation resin layer 3a. Corresponding recesses 4a1 and 4a2 are provided.

The recognition pattern is provided at two diagonal positions inside the outer peripheral portion 3 where the bonding pads 10 of the rectangular semiconductor element 1 are arranged, 100 μm × 100 μm to 200 μm × 2.
It is provided with a width of 00 μm. Recesses 4a1 and 4a2
The size of is slightly larger than this area. The thickness of the stress relaxation resin layer 3a in the recess is as high as 5 μm, for example 4
The thickness is about μm, and the remaining portion is about 12 μm when the size of the semiconductor element is 8 mm × 8 mm.

Next, a method for forming the stress relaxation resin layer will be described.

A coating solution prepared by mixing a polyimide solution and a filler such as fused silica in a weight ratio of 8: 1 is applied to a wafer (which has been completed up to the formation of a bonding pad and a cover film) by a spin-on method, and cured to a thickness. A first resin film having a thickness of 4 μm is formed, and is patterned into a rectangle by etching and left on the semiconductor element. Next, the above-mentioned coating solution is used again to form a first resin film having a thickness of 8 μm, and a square hole (4a2) of 300 μm × 300 μm and a rectangular shape of 300 μm × 400 μm are formed at the diagonal portions of the rectangle by etching. The second resin film is patterned into a shape having the holes (4a1). In this way, the stress relaxation resin layer 3a shown in FIGS. 1 and 2 can be formed. The size of the semiconductor element 1 is 8 mm × 8 mm.

After that, a resin-sealed semiconductor device can be obtained by performing pelletizing, die bonding, wire bonding and resin sealing simultaneously with the conventional method.

With this structure, even if the size of the semiconductor element 1 is increased, most of the circuit forming surface 2 is at least 5 μm.
It can be covered with a resin layer having a thickness of m, and the pattern recognition in the assembling process can be performed by the recess having a height of 5 μm. Therefore, the heat resistance can be improved as compared with the conventional example.

FIG. 3 is a sectional view of the second embodiment of the present invention. In this case, a large number of concave portions 4b are provided by selecting a portion (for example, an uneven portion) that is likely to be strong in the circuit forming pattern against the stress from the sealing resin 9. According to this embodiment, there is an advantage that the mechanical adhesion between the sealing resin and the stress relaxation resin layer is increased, the water resistance from the outside is increased, and the moisture resistance is further improved.

[0016]

As described above, according to the present invention, the stress relaxation resin layer having the recess corresponding to the recognition pattern is provided on the circuit formation surface of the semiconductor element, so that the stress applied from the sealing resin to the semiconductor element is reduced. Since it is possible to effectively mitigate the problem, it is possible to automatically recognize the pattern of the assembly equipment and obtain a resin-sealed semiconductor device having excellent heat resistance.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention.

FIG. 2 is a plan view showing details of a part of FIG.

FIG. 3 is a sectional view showing a second embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a conventional resin-sealed semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Circuit formation surface 3, 3a, 3b Stress relaxation resin layer 4, 4a1, 4a2, 4b Recessed portion 5 Gold wire 6 Silver paste 7 Die attach portion 8 Lead 9 Sealing resin 10 Bonding pad

Claims (1)

[Claims] 1. A semiconductor device having a semiconductor element having a recognition pattern formed on a circuit formation surface and a stress relaxation resin layer covering the circuit formation surface of the semiconductor element, wherein the stress relaxation resin layer has a surface. A resin-encapsulated semiconductor device having a recess corresponding to the recognition pattern.