JP2000183108A - Semiconductor integrated circuit device and its manufacture - Google Patents
Semiconductor integrated circuit device and its manufactureInfo
- Publication number
- JP2000183108A JP2000183108A JP10360336A JP36033698A JP2000183108A JP 2000183108 A JP2000183108 A JP 2000183108A JP 10360336 A JP10360336 A JP 10360336A JP 36033698 A JP36033698 A JP 36033698A JP 2000183108 A JP2000183108 A JP 2000183108A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- circuit device
- interlayer insulating
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する分野】本発明は、半導体集積回路装置、
特にワイヤレスボンディング工程におけるフリップチッ
プ接続用電極パッドとその電極パッド近傍の表面保護膜
構造に関するものである。The present invention relates to a semiconductor integrated circuit device,
In particular, the present invention relates to a flip chip connection electrode pad in a wireless bonding process and a surface protective film structure near the electrode pad.
【０００２】[0002]
【従来の技術】近年、半導体集積回路装置に搭載される
素子数が増加するに伴い、係る半導体集積回路装置の入
出力用信号ピン数も増加している。また、電子機器の小
型化という点においては、実装面積を少なくした高密度
実装の電子機器が求められていることから、多数の信号
ピンを高密度で実装できるフリップチップ接続による実
装方法が注目されている。このフリップチップ接続方法
が提案されたのは古く、International BusinessMachin
e Corporationによって、その解説記事がSemiconductor
World増刊 サーフェイスマウントテクノロジー（1993
年冬号）等に紹介されている。2. Description of the Related Art In recent years, as the number of elements mounted on a semiconductor integrated circuit device has increased, the number of input / output signal pins of the semiconductor integrated circuit device has also increased. In addition, in terms of miniaturization of electronic devices, there is a demand for high-density electronic devices with a small mounting area, so mounting methods using flip-chip connection that can mount a large number of signal pins at high density are attracting attention. ing. This flip-chip connection method has been proposed for a long time, and
e Corporation explains the article by Semiconductor
World special issue surface mount technology (1993
Winter issue).
【０００３】フリップチップ接続に用いるハンダバンプ
電極の形成方法の一例を図面を参照して以下に説明す
る。図１０はＬＳＩチップＡの電極面の平面図であり、
シリコン基板１上にパッド電極２がアレイ状に配設され
ている。この図１０における１つのパッド電極２を取り
出したものが図１１であり、また図１１に記載されたＢ
−Ｂ’線における断面図が図１２である。この図１２に
示されるように、ＬＳＩチップＡはシリコン基板１上
に、第１の層間絶縁膜４が形成され、係る第１の層間絶
縁膜４上に第２の層間絶縁膜６が形成されている。第１
層配線５は前記第１の層間絶縁膜４と接した態様で第１
の層間絶縁膜４と第２の層間絶縁膜６とに挟まれて形成
されている。第２層配線７は前記第２の層間絶縁膜６上
に設けられており、その第２の層間絶縁膜６と第２層配
線７との表面を覆う態様で第３の層間絶縁膜８が形成さ
れているが、係る第３の層間絶縁膜８は第２層配線７の
表面の一部で分断されている。第３の層間絶縁膜８上に
は表面保護膜９が形成されており、前記第３の層間絶縁
膜８が分断されている箇所、すなわち、第２層配線７上
と前記表面保護膜９の側面とを覆う態様でバリアメタル
１０が円環状に形成されている。また、係るバリアメタ
ル１０上には、パッド電極２が前記バリアメタル１０に
対して所定の厚さを有して設けられている。An example of a method for forming a solder bump electrode used for flip chip connection will be described below with reference to the drawings. FIG. 10 is a plan view of the electrode surface of the LSI chip A,
Pad electrodes 2 are arranged in an array on a silicon substrate 1. FIG. 11 shows one pad electrode 2 in FIG. 10 taken out.
FIG. 12 is a sectional view taken along line -B '. As shown in FIG. 12, in the LSI chip A, a first interlayer insulating film 4 is formed on a silicon substrate 1, and a second interlayer insulating film 6 is formed on the first interlayer insulating film 4. ing. First
The layer wiring 5 is a first layer in a state where the layer wiring 5 is in contact with the first interlayer insulating film 4.
Is formed between the first interlayer insulating film 4 and the second interlayer insulating film 6. The second layer wiring 7 is provided on the second interlayer insulating film 6. The third interlayer insulating film 8 is formed so as to cover the surfaces of the second interlayer insulating film 6 and the second layer wiring 7. Although formed, the third interlayer insulating film 8 is divided at a part of the surface of the second-layer wiring 7. A surface protection film 9 is formed on the third interlayer insulating film 8, and a portion where the third interlayer insulating film 8 is divided, that is, a portion between the second layer wiring 7 and the surface protection film 9. The barrier metal 10 is formed in an annular shape so as to cover the side surfaces. Further, the pad electrode 2 is provided on the barrier metal 10 so as to have a predetermined thickness with respect to the barrier metal 10.
【０００４】以上に説明した各層間絶縁膜は、各配線を
導電体として独立させて機能させるために設けられてお
り、ＬＳＩチップＡの作成工程におけるリソグラフィー
技術を簡便に行うために各層間絶縁膜上に各配線が設置
される。また、前記表面保護膜９の膜厚を十分に設定し
なければＬＳＩチップＡ内部を外部の熱などによる影響
から保護しなければならないことから、前記パッド電極
２もそれに伴って十分な厚さを設定する必要を有する。The above-described interlayer insulating films are provided to make each wiring function independently as a conductor, and to facilitate the lithography technique in the process of manufacturing the LSI chip A, each interlayer insulating film is provided. Each wiring is installed on the top. If the thickness of the surface protection film 9 is not set sufficiently, the inside of the LSI chip A must be protected from the influence of external heat and the like, so that the pad electrode 2 also has a sufficient thickness. You have to set.
【０００５】次に、図１０に示されるパッド電極２の形
成方法を以下に説明する。図１３ａにおいて、シリコン
基板１上にトランジスタ素子（図示せず）を形成した
後、第１の層間絶縁膜４を形成する。次に、第１の層間
絶縁膜４上に第１層配線５をパターニングした後、第２
の層間絶縁膜６、第２層配線７を同様に形成する。この
とき、第２層配線７はＣｕを含有するＡｌ合金である。
また、その膜厚は約１μｍであり、第２層配線７により
形成されるパッドのサイズは約２００μｍである。Next, a method of forming the pad electrode 2 shown in FIG. 10 will be described below. In FIG. 13A, after forming a transistor element (not shown) on a silicon substrate 1, a first interlayer insulating film 4 is formed. Next, after patterning the first layer wiring 5 on the first interlayer insulating film 4,
Are formed in the same manner. At this time, the second layer wiring 7 is an Al alloy containing Cu.
The film thickness is about 1 μm, and the size of the pad formed by the second-layer wiring 7 is about 200 μm.
【０００６】次に、図１４ｂに示すように第２層配線７
を保護する第３の層間絶縁膜８及び表面保護膜９を形成
する。このとき、第３の層間絶縁膜８は酸化膜と窒化膜
の２層構造を成しており、その膜厚は各々約０．１μ
ｍ、約１μｍである。また、従来、前記表面保護膜９に
はポリイミド樹脂が使用されており、耐熱性に富むこの
樹脂は膜形成における欠陥が少なく、形成膜の膜厚を比
較的自由に設定することができ、平坦性に優れていると
いう特徴があるためである。[0006] Next, as shown in FIG.
A third interlayer insulating film 8 and a surface protection film 9 for protecting the semiconductor device are formed. At this time, the third interlayer insulating film 8 has a two-layer structure of an oxide film and a nitride film, each having a thickness of about 0.1 μm.
m, about 1 μm. Conventionally, a polyimide resin is used for the surface protective film 9, and this resin having high heat resistance has few defects in film formation, the film thickness of the formed film can be set relatively freely, and This is because it has a characteristic of being excellent in property.
【０００７】感光性ポリイミド樹脂からなる表面保護膜
９を、フォトリソグラフィー工程にて露光、現像したも
のを図１４ａに示す。この工程からさらに、表面保護膜
９自身をフォトマスクとして、第３の層間絶縁膜８をＲ
ＩＥ法により第２層配線７を露出させ、バリアメタル１
０を形成し、連続してその後に、Ｃｕを材料とするパッ
ド電極２を１０μｍの厚さで形成する。その図が図１４
ｂである。ここで、バリアメタル材料とは半田（ＰｂＳ
ｎ）からＬＳＩチップＡ側のＡｌ配線へＰｂ、Ｓｎが拡
散することで、Ａｌ配線の信頼性を低下させるのを防ぐ
高融点金属であり、主にＰｄ、Ｎｉ、ＣｒＣｕ、Ｔｉ
Ｗ、Ｔｉ等が用いられる。FIG. 14A shows a surface protective film 9 made of a photosensitive polyimide resin, which is exposed and developed in a photolithography process. From this step, the third interlayer insulating film 8 is further formed by using the surface protective film 9 itself as a photomask.
The second layer wiring 7 is exposed by the IE method, and the barrier metal 1 is exposed.
0 is formed, and subsequently, a pad electrode 2 made of Cu is formed with a thickness of 10 μm. Fig. 14
b. Here, the barrier metal material is solder (PbS
n) is a refractory metal that prevents Pb and Sn from diffusing into the Al wiring on the side of the LSI chip A, thereby lowering the reliability of the Al wiring, and is mainly composed of Pd, Ni, CrCu, Ti
W, Ti, etc. are used.
【０００８】次に、図１５に示すようにカバースルーホ
ール１１を覆うようにフォトレジスト１２を形成し、こ
のフォトレジスト１２をマスクとしてバリアメタル１
０、パッド電極２のエッチングを行い、図１２に示され
る構造が得られる。Next, a photoresist 12 is formed so as to cover the cover through hole 11 as shown in FIG.
0, the pad electrode 2 is etched to obtain the structure shown in FIG.
【０００９】ワイヤレスボンディング工程におけるフリ
ップチップ法は図１６に示されるように、ＬＳＩチップ
Ａを裏返しにし、半田ボール１８をカバースルーホール
１１に載置し、接続するべきリードフレーム（図示せ
ず）に対しリフローさせることによって接続されてその
工程を完了する。In the flip chip method in the wireless bonding step, as shown in FIG. 16, the LSI chip A is turned upside down, the solder balls 18 are placed in the cover through holes 11, and a lead frame (not shown) to be connected is provided. On the other hand, they are connected by reflow to complete the process.
【００１０】[0010]
【発明が解決しようとする課題】しかしながら、従来の
この半導体集積回路の実装工程においては次のような問
題があった。一般に、プリント基板等と接続するリード
フレーム（図示せず）とＬＳＩチップとは前記半田ボー
ル１８を介して繋がっている。半導体集積回路装置のお
かれる環境下に前記リフロー作業などの温度変化が生じ
ると、ＬＳＩチップとプリント基板等との熱膨張係数が
異なるために熱起因の応力が発生し、半田ボールに亀裂
が生じることがあった。However, there are the following problems in the conventional mounting process of this semiconductor integrated circuit. Generally, a lead frame (not shown) connected to a printed circuit board or the like is connected to the LSI chip via the solder ball 18. When a temperature change such as the reflow operation occurs in an environment where a semiconductor integrated circuit device is placed, heat-induced stress occurs due to a difference in thermal expansion coefficient between an LSI chip and a printed circuit board, and a solder ball is cracked. There was something.
【００１１】この熱起因による応力を緩和するために、
ＬＳＩチップとプリント基板等との間に樹脂を注入する
ことがよく知られている。しかし、係る樹脂注入により
半田ボールの亀裂は防止できるが、熱起因による応力自
身が消失する訳ではなく、熱起因による応力はＬＳＩチ
ップの内部に多大な悪影響を与える。具体的には、熱起
因による応力は半田ボールを介してＬＳＩチップへ働
き、表面保護膜に亀裂を生じさせるという問題が挙げら
れる。係る亀裂の発生により、表面保護膜自体が本来の
役目を果たさず、結果として半導体集積回路装置の信頼
性を低下させるという問題を生じていた。In order to alleviate the heat-induced stress,
It is well known that a resin is injected between an LSI chip and a printed circuit board or the like. However, cracks in the solder balls can be prevented by the resin injection, but the stress due to heat does not disappear, and the stress due to heat has a great adverse effect on the inside of the LSI chip. Specifically, there is a problem that a stress due to heat acts on an LSI chip via a solder ball and causes a crack in a surface protective film. Due to the occurrence of such cracks, the surface protective film itself does not perform its original function, and as a result, there has been a problem that the reliability of the semiconductor integrated circuit device is reduced.
【００１２】本発明に係る半導体集積回路装置は、以上
の従来技術における問題に鑑みてなされたものであり、
リフロー作業に起因する熱ストレスによって生じる亀裂
を防止する表面保護膜の構造を提供することが目的であ
る。A semiconductor integrated circuit device according to the present invention has been made in view of the above-mentioned problems in the prior art,
It is an object of the present invention to provide a structure of a surface protective film that prevents cracks caused by thermal stress caused by a reflow operation.
【００１３】[0013]
【課題を解決するための手段】前記課題を解決するため
に提供する本願第一の発明に係る半導体集積回路装置
は、カバースルーホールの外周囲近傍に熱放射部が設け
られていることを特徴とする。According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device provided with a heat radiation portion near an outer periphery of a cover through hole. And
【００１４】カバースルーホールの外周囲近傍が熱放射
機能を有する形状に形成されていることにより、ＬＳＩ
チップをプリント基板等と接続する際に起因する熱スト
レスの影響を表面保護膜において緩和させ、半導体素子
にまでその影響を至らしめることを防ぐことができる。Since the vicinity of the outer periphery of the cover through hole is formed in a shape having a heat radiation function, an LSI
The effect of thermal stress caused when the chip is connected to a printed circuit board or the like can be reduced in the surface protective film, and the effect can be prevented from reaching the semiconductor element.
【００１５】前記課題を解決するために提供する本願第
二の発明に係る半導体集積回路装置は、前記熱放射部は
孔が形成されてなることを特徴とする。A semiconductor integrated circuit device according to a second aspect of the present invention, which is provided to solve the above problem, is characterized in that the heat radiating portion is formed with a hole.
【００１６】前記熱放射部に孔が形成されてなることに
より、前記熱放射機能を孔が形成する表面積の大きさで
高めることができる。By forming the holes in the heat radiating portion, the heat radiating function can be enhanced by the size of the surface area formed by the holes.
【００１７】前記課題を解決するために提供する本願第
三の発明に係る半導体集積回路装置は、前記孔が表面保
護膜内に形成されていることを特徴とする。A semiconductor integrated circuit device according to a third aspect of the present invention provided to solve the above-mentioned problem is characterized in that the hole is formed in a surface protection film.
【００１８】前記孔が表面保護膜内に形成されているこ
とにより、半導体内部素子に熱による応力の影響を与え
ることなく、前記孔が形成する表面積を最大限に生かす
ことができる。Since the holes are formed in the surface protective film, the surface area formed by the holes can be maximized without exerting an influence of thermal stress on the internal semiconductor element.
【００１９】前記課題を解決するために提供する本願第
四の発明に係る半導体集積回路装置は、前記孔が円環状
に形成されていることを特徴とする。According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit device provided to solve the above-mentioned problem, wherein the hole is formed in an annular shape.
【００２０】前記孔が円環状に形成されていることによ
り、熱による応力を均一に分散させることが可能とな
り、表面保護膜内における前記孔の形成分布に起因する
熱放射の歪みなどが生じない。Since the holes are formed in an annular shape, it is possible to uniformly disperse the stress caused by heat, so that distortion of heat radiation caused by the formation distribution of the holes in the surface protective film does not occur. .
【００２１】前記課題を解決するために提供する本願第
五の発明に係る半導体集積回路装置は、前記孔が多重の
円環状に形成されていることを特徴とする。According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit device provided in order to solve the above-mentioned problem, wherein the holes are formed in multiple annular shapes.
【００２２】前記孔が多重の円環状に形成されているこ
とにより、さらに均一な熱放射機能を実現することが可
能となる。Since the holes are formed in multiple annular shapes, it is possible to realize a more uniform heat radiation function.
【００２３】前記課題を解決するために提供する本願第
六の発明に係る半導体集積回路装置は、前記熱放射部は
溝が形成されてなることを特徴とする。A semiconductor integrated circuit device according to a sixth aspect of the present invention provided to solve the above-mentioned problem is characterized in that the heat radiating portion is formed with a groove.
【００２４】前記カバースルーホールの外周囲に溝が形
成されていることにより、表面保護膜及び半導体内部素
子に係る熱による応力を効果的に緩和することが可能で
ある。Since the groove is formed around the outer periphery of the cover through hole, it is possible to effectively reduce the thermal stress on the surface protection film and the semiconductor internal element.
【００２５】前記課題を解決するために提供する本願第
七の発明に係る半導体集積回路装置は、前記溝が表面保
護膜内に形成されていることを特徴とする。A semiconductor integrated circuit device according to a seventh aspect of the present invention provided to solve the above-mentioned problem is characterized in that the groove is formed in a surface protection film.
【００２６】前記溝が表面保護膜内に形成されているこ
とにより、半導体内部素子に熱による応力の影響を与え
ることなく、前記溝が形成する表面積を最大限に生かす
ことができる。Since the groove is formed in the surface protective film, the surface area formed by the groove can be maximized without affecting the internal semiconductor element by the thermal stress.
【００２７】前記課題を解決するために提供する本願第
八の発明に係る半導体集積回路装置は、前記溝が円環状
に形成されていることを特徴とする。A semiconductor integrated circuit device according to an eighth aspect of the present invention provided to solve the above-mentioned problem is characterized in that the groove is formed in an annular shape.
【００２８】前記溝が円環状に形成されていることによ
り、熱による応力を均一に分散させることが可能とな
る。Since the grooves are formed in an annular shape, it is possible to uniformly disperse the thermal stress.
【００２９】前記課題を解決するために提供する本願第
九の発明に係る半導体集積回路装置は、前記溝が多重の
円環状に形成されていることを特徴とする。According to a ninth aspect of the present invention, there is provided a semiconductor integrated circuit device in which the grooves are formed in a multiple annular shape.
【００３０】前記溝が多重の円環状に形成されているこ
とにより、さらに均一な熱放射機能を実現することが可
能となる。Since the grooves are formed in multiple annular shapes, a more uniform heat radiation function can be realized.
【００３１】前記課題を解決するために提供する本願第
十の発明に係る半導体集積回路装置の製造方法は、パッ
ド電極上に表面保護膜を形成し、係る表面保護膜にカバ
ースルーホールを形成する半導体集積回路装置の製造方
法において、前記表面保護膜に、感光性樹脂の解像度以
下のサイズのパターンを用いて溝を形成することを特徴
とする。According to a tenth aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device in which a surface protective film is formed on a pad electrode and a cover through hole is formed in the surface protective film. In the method for manufacturing a semiconductor integrated circuit device, a groove is formed in the surface protective film using a pattern having a size equal to or smaller than the resolution of the photosensitive resin.
【００３２】前記表面保護膜に、感光性樹脂の解像度以
下のサイズのパターンを用いて溝を形成することによ
り、複雑な構造又は、余分な工程を経ることなく熱放射
機能を有する表面保護膜を形成することが可能となる。By forming a groove in the surface protective film using a pattern having a size smaller than the resolution of the photosensitive resin, a surface protective film having a complicated structure or a heat radiation function without passing through an extra step is formed. It can be formed.
【００３３】前記課題を解決するために提供する本願第
十一の発明に係る半導体集積回路装置の製造方法は、前
記表面保護膜に、感光性樹脂の解像度以下のサイズのパ
ターンを用いて孔を形成することを特徴とする。According to an eleventh aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device, comprising the steps of: forming a hole in the surface protective film by using a pattern having a size equal to or smaller than the resolution of a photosensitive resin; It is characterized by forming.
【００３４】前記表面保護膜に、感光性樹脂の解像度以
下のサイズのパターンを用いて孔を形成することによ
り、強度を保ちつつ、十分な熱放射機能を有する表面保
護膜を形成することが可能となる。By forming holes in the surface protective film using a pattern having a size smaller than the resolution of the photosensitive resin, it is possible to form a surface protective film having a sufficient heat radiation function while maintaining strength. Becomes
【００３５】[0035]
【発明の実施の形態】以下に、本発明に係る半導体集積
回路装置及びその製造方法の一実施の形態を図面を参照
しながら説明する。図１は、本発明に係る半導体集積回
路装置における、パッド電極２の周囲に溝１３を形成し
たときのＬＳＩチップＡの電極面の平面図である。ＬＳ
ＩチップＡはシリコン基板１上に各層にわたって半導体
素子（図示せず）が形成されてなり、図１に示すよう
に、係るＬＳＩチップＡ表面にはパッド電極２がアレイ
状に配設され、その周囲には溝１３が形成されている。
さらに、係るパッド電極２付近の拡大図である図２に示
されるように、溝１３は個々のパッド電極２の外周を取
り囲むように形成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a semiconductor integrated circuit device and a method of manufacturing the same according to the present invention will be described with reference to the drawings. FIG. 1 is a plan view of an electrode surface of an LSI chip A when a groove 13 is formed around a pad electrode 2 in a semiconductor integrated circuit device according to the present invention. LS
The I chip A has a semiconductor element (not shown) formed on each layer on a silicon substrate 1. As shown in FIG. 1, pad electrodes 2 are arranged in an array on the surface of the LSI chip A. A groove 13 is formed around the periphery.
Further, as shown in FIG. 2 which is an enlarged view near the pad electrode 2, the groove 13 is formed so as to surround the outer periphery of each pad electrode 2.
【００３６】ここで、図２Ａ−Ａ’線断面図、すなわち
本発明に係る半導体集積回路装置の断面図を図３に示
す。図３に示されるように、シリコン基板１上に、第１
の層間絶縁膜４が形成され、係る第１の層間絶縁膜４上
に第２の層間絶縁膜６が形成されている。第１層配線５
は前記第１の層間絶縁膜４と接した態様で第１の層間絶
縁膜４と第２の層間絶縁膜６とに挟まれて形成されてい
る。第２層配線７は前記第２の層間絶縁膜６上に設けら
れており、その第２の層間絶縁膜６と第２層配線７との
表面を覆う態様で第３の層間絶縁膜８が形成されている
が、係る第３の層間絶縁膜８は第２層配線７の表面の一
部で分断されている。第３の層間絶縁膜８上には表面保
護膜９が形成されており、前記第３の層間絶縁膜８が分
断されている箇所、すなわち、第２層配線７上と前記表
面保護膜９の側面とを覆う態様でバリアメタル１０が円
柱状に形成されている。また、係るバリアメタル１０上
には、パッド電極２が前記バリアメタル１０に対して所
定の厚さを有して設けられている。さらに、前記表面保
護膜９には、前記パッド電極２を囲むように溝１３が設
けられ、係る溝１３の深さは前記表面保護膜９の底部に
達しない深さで設定されている。FIG. 3 is a sectional view taken along the line AA 'of FIG. 2, that is, a sectional view of the semiconductor integrated circuit device according to the present invention. As shown in FIG. 3, the first
Is formed, and a second interlayer insulating film 6 is formed on the first interlayer insulating film 4. First layer wiring 5
Is formed so as to be in contact with the first interlayer insulating film 4 and sandwiched between the first interlayer insulating film 4 and the second interlayer insulating film 6. The second layer wiring 7 is provided on the second interlayer insulating film 6. The third interlayer insulating film 8 is formed so as to cover the surfaces of the second interlayer insulating film 6 and the second layer wiring 7. Although formed, the third interlayer insulating film 8 is divided at a part of the surface of the second-layer wiring 7. A surface protection film 9 is formed on the third interlayer insulating film 8, and a portion where the third interlayer insulating film 8 is divided, that is, a portion between the second layer wiring 7 and the surface protection film 9. The barrier metal 10 is formed in a columnar shape so as to cover the side surfaces. Further, the pad electrode 2 is provided on the barrier metal 10 so as to have a predetermined thickness with respect to the barrier metal 10. Further, a groove 13 is provided in the surface protection film 9 so as to surround the pad electrode 2, and the depth of the groove 13 is set to a depth that does not reach the bottom of the surface protection film 9.
【００３７】以上に記載の溝１３が表面保護膜９に設け
られたことによって、表面保護膜９に係る熱の応力は前
記溝１３によって解消され、表面保護膜９に過度の応力
が掛かるのを防ぐことが可能となり、表面保護膜９の亀
裂を防止できることから、半導体集積回路装置の信頼性
の低下を防ぐことが可能となる。また、カバースルーホ
ール１１の開口後に、新たにフォトレジストを塗布して
エッチングを行うという溝１３形成のための余分な工程
を必要としないという利点がある。Since the groove 13 described above is provided in the surface protection film 9, the thermal stress on the surface protection film 9 is eliminated by the groove 13, and excessive stress is applied to the surface protection film 9. Since the surface protection film 9 can be prevented from cracking, it is possible to prevent a decrease in the reliability of the semiconductor integrated circuit device. In addition, there is an advantage that an additional process for forming the groove 13 such that a new photoresist is applied and etched after the opening of the cover through hole 11 is not required.
【００３８】以上に記載されたＬＳＩチップ及び溝の形
成方法を図を参照にして以下に説明する。図４ａに示す
ように、シリコン基板１上にトランジスタ素子（図示せ
ず）を形成した後、第１の層間絶縁膜４を形成する。係
る第１の層間絶縁膜４の上に第１層配線５をパターニン
グし、第２の層間絶縁膜６及び第２層配線７を上記と同
様に形成する。ここで、第２層配線７はその上下をＴｉ
Ｎにより挟まれた構造を有するＣｕ含有のＡｌ合金であ
り、係る第２層配線７の膜厚は約１μｍである。また、
第２層配線７により形成されたアルミパッドのサイズは
約２００μｍである。The method of forming the above-described LSI chip and groove will be described below with reference to the drawings. As shown in FIG. 4A, after forming a transistor element (not shown) on the silicon substrate 1, a first interlayer insulating film 4 is formed. The first layer wiring 5 is patterned on the first interlayer insulating film 4 to form the second interlayer insulating film 6 and the second layer wiring 7 in the same manner as described above. Here, the upper and lower portions of the second layer wiring 7 are Ti
It is a Cu-containing Al alloy having a structure sandwiched by N, and the thickness of the second-layer wiring 7 is about 1 μm. Also,
The size of the aluminum pad formed by the second layer wiring 7 is about 200 μm.
【００３９】次に、図４ｂに示すように第２層配線７を
保護する第３の層間絶縁膜８及び表面保護膜９を形成す
る。本発明における半導体集積回路装置の実施例におい
ても、表面保護膜９は、感光基をもつ感光性ポリイミド
樹脂を用い、その塗布膜厚は約１０μｍとする。また、
第３の層間絶縁膜８は酸化膜と窒化膜との２層構造であ
り、その膜厚は各々約０．１μｍ、約１μｍである。Next, as shown in FIG. 4B, a third interlayer insulating film 8 and a surface protection film 9 for protecting the second layer wiring 7 are formed. Also in the embodiment of the semiconductor integrated circuit device according to the present invention, the surface protective film 9 is made of a photosensitive polyimide resin having a photosensitive group, and has a coating thickness of about 10 μm. Also,
The third interlayer insulating film 8 has a two-layer structure of an oxide film and a nitride film, and has a thickness of about 0.1 μm and about 1 μm, respectively.
【００４０】次に、図５に示すように、石英基板１４の
表面にカバースルーホール１１及び溝１３とを形成する
パターンＡ１６，パターンＢ１７とを形成したＣｒマス
ク１５を通して、感光性ポリイミド樹脂からなる表面保
護膜９の露光を行う。このときのパターンＡ１６のサイ
ズは約１６０μｍとし、パターンＢ１７のサイズは、感
光性ポリイミド樹脂内に含まれる感光基が有する解像度
よりも小さいサイズであり、感光基の光化学反応が表面
保護膜９内部において終了することで前記溝１３は表面
保護膜９の底部まで到達しない深度で形成される。ここ
で、前記感光性樹脂の解像度は、前述のように感光性ポ
リイミド樹脂の膜厚を約１０μｍとしたため、溝１３に
必要な深さを約７μｍに設定し、約２μｍのパターン径
にて前記溝１３が形成できるように感光性ポリイミド樹
脂内に含まれる感光基の環や分子鎖の長さを調整するこ
とで解像度を調整する。また、本発明の実施の形態にお
いては、ポジ型の感光基を有する感光性ポリイミド樹脂
を例として挙げたが、ネガ型の感光基を有する感光性ポ
リイミド樹脂を用いても良い。Next, as shown in FIG. 5, a photosensitive polyimide resin is passed through a Cr mask 15 on which a pattern A16 and a pattern B17 for forming the cover through hole 11 and the groove 13 are formed on the surface of the quartz substrate 14. The surface protection film 9 is exposed. At this time, the size of the pattern A16 is about 160 μm, and the size of the pattern B17 is smaller than the resolution of the photosensitive group contained in the photosensitive polyimide resin. When the process is completed, the groove 13 is formed at a depth that does not reach the bottom of the surface protection film 9. Here, as for the resolution of the photosensitive resin, since the thickness of the photosensitive polyimide resin was set to about 10 μm as described above, the depth required for the groove 13 was set to about 7 μm, and the pattern diameter was set to about 2 μm. The resolution is adjusted by adjusting the length of the ring or molecular chain of the photosensitive group contained in the photosensitive polyimide resin so that the groove 13 can be formed. In the embodiment of the present invention, a photosensitive polyimide resin having a positive photosensitive group has been described as an example, but a photosensitive polyimide resin having a negative photosensitive group may be used.
【００４１】次に、図６に示されるように、前述の露光
工程完了時点での表面保護膜９の形状をマスクとして第
３の層間絶縁膜８をＲＩＥ法により除去し、第２層配線
７の露出を行う。さらに、前工程で露出された第２層配
線７と表面保護膜９の側面とを覆う態様でバリアメタル
１０，パッド電極２とを連続して形成し、フォトリソグ
ラフィ技術によるパターニングを行うことで、前述の図
３に示す構造を得る。このバリアメタル１０の材料とし
ては、Ｐｄ、Ｎｉ、ＣｒＣｕ、ＴｉＷ、Ｔｉ等が提案さ
れているが、本発明の実施の形態においては従来の配線
技術にしばしば用いられているＴｉＷを使用し、その膜
厚を約０．２μｍとした。また、パッド電極２はＣｕと
し、その膜厚を約６μｍとした。その後、図７に示され
るように、フリップチップ法によって、半導体チップを
裏返しにし、半田ボール１８をカバースルーホール１１
に載置し、接続するべきリードフレーム（図示せず）に
対しリフローさせることによって接続されてその工程を
完了する。Next, as shown in FIG. 6, the third interlayer insulating film 8 is removed by RIE using the shape of the surface protective film 9 at the time of completion of the above-mentioned exposure step as a mask, and the second layer wiring 7 is removed. Exposure. Further, the barrier metal 10 and the pad electrode 2 are continuously formed so as to cover the second layer wiring 7 exposed in the previous step and the side surface of the surface protection film 9, and are patterned by photolithography. The structure shown in FIG. 3 is obtained. As a material of the barrier metal 10, Pd, Ni, CrCu, TiW, Ti, and the like have been proposed. In the embodiment of the present invention, TiW, which is often used in the conventional wiring technology, is used. The film thickness was about 0.2 μm. The pad electrode 2 was made of Cu, and its film thickness was about 6 μm. Thereafter, as shown in FIG. 7, the semiconductor chip is turned over by the flip chip method, and the solder balls 18 are covered with the cover through holes 11.
And connected by reflowing to a lead frame (not shown) to be connected to complete the process.
【００４２】また、パッド電極２周囲に配設された溝１
３の形成に用いるパターンＢ１７を感光性ポリイミド樹
脂の有する解像度以下のサイズとなるように、感光基の
調整を行うことにより、パターンＢ１７による感光性ポ
リイミド樹脂の光反応が感光性ポリイミド樹脂内で止ま
り、溝１３の深度は係る感光性ポリイミド樹脂の深度以
内で形成される。この方法により、感光性ポリイミド樹
脂の途中で、溝１３を止まらせるために、表面保護膜９
内にエッチングストッパー用の膜を挟んだサンドイッチ
構造を構成しなければならないといった工程上の煩雑さ
がなくなる。The groove 1 provided around the pad electrode 2
The photoreaction of the photosensitive polyimide resin by the pattern B17 stops in the photosensitive polyimide resin by adjusting the photosensitive group so that the size of the pattern B17 used for the formation of the pattern 3 is equal to or smaller than the resolution of the photosensitive polyimide resin. The depth of the groove 13 is formed within the depth of the photosensitive polyimide resin. According to this method, the surface protective film 9 is formed to stop the groove 13 in the middle of the photosensitive polyimide resin.
There is no need for a complicated process in which a sandwich structure in which a film for an etching stopper is sandwiched is formed.
【００４３】尚、図８に示すように、表面保護膜９に溝
１３を多重に形成することによって、熱による応力緩和
効果がさらに高まるといった効果を奏する。また、図９
ａに示すように、表面保護膜９に溝１３を孔３の群に置
換した構成とすることによって、表面保護膜９の強度を
保ちつつ、熱による応力緩和の効果を十分に奏する。As shown in FIG. 8, by forming the grooves 13 in the surface protective film 9 in a multiplex manner, the effect of relaxing the stress by heat is further enhanced. FIG.
As shown in FIG. 3A, by employing a configuration in which the grooves 13 are replaced with the group of the holes 3 in the surface protection film 9, the effect of relaxing stress by heat is sufficiently exhibited while maintaining the strength of the surface protection film 9.
【００４４】ここで、Ｃｒマスク１５を光が透過したと
ころで、係るＣｒマスク１５がネガであれば高分子の光
架橋反応、ポジであれば光分解反応が起こり、そのＣｒ
マスク１５により光が当たる箇所と当たらない箇所とを
分けることで前記溝１３を分断し、図９ａに示されるよ
うなパッド電極２外周を取り囲む態様で孔３を形成する
ことが可能である。また、表面保護膜内９に孔３を形成
し、その後、感光性樹脂の解像度を落とすことでマスク
パターン縁部で光の境界線が等しい軌跡、すなわちパタ
ーンの実効的な境界線であるエッジを不明瞭な形状にし
て前記孔３同士を連通させることによって溝１３を形成
させることも可能である。ここで、孔３を形成する方法
として、図５に示されたＣｒマスク１５がネガであれば
高分子の光架橋反応、ポジであれば光分解反応が起こる
ことを利用し、そのＣｒマスク１５により光が当たる箇
所と当たらない箇所とを任意に分けることで前記溝１３
を分断し、図９ａに示されるような孔３を表面保護膜９
に形成することが可能である。また、表面保護膜内９に
孔３を形成した後、感光性樹脂の解像度を落とすことで
マスクパターン縁部で光の境界線が等しい軌跡、すなわ
ちパターンの実効的な境界線であるエッジを不明瞭な形
状にして前記孔３同士を連通させることによって溝１３
を形成させることも可能である。さらに、図９ｂに示す
ように、前述の表面保護膜９に溝１３を多重に形成する
と同様、表面保護膜９に孔３を多重に形成することによ
り、表面保護膜９の強度を損なうことなく、リフロー作
業による熱を放射させる機能を十分に実現させることが
可能である。Here, when light is transmitted through the Cr mask 15, if the Cr mask 15 is negative, a photocrosslinking reaction of a polymer occurs. If the Cr mask 15 is positive, a photolysis reaction occurs.
The groove 13 is divided by dividing a portion where light is irradiated and a portion where light is not irradiated by the mask 15, and the hole 3 can be formed so as to surround the outer periphery of the pad electrode 2 as shown in FIG. 9A. In addition, holes 3 are formed in the surface protective film 9 and then the resolution of the photosensitive resin is reduced so that the trajectory where the light boundaries are equal at the edges of the mask pattern, that is, the edges that are the effective boundaries of the pattern are formed. It is also possible to form the groove 13 by making the holes 3 communicate with each other in an unclear shape. Here, as a method of forming the holes 3, a method in which a photocrosslinking reaction of a polymer occurs when the Cr mask 15 shown in FIG. The groove 13 can be arbitrarily divided into a portion where light is applied and a portion where light is not applied.
And the holes 3 as shown in FIG.
It is possible to form. Also, after the holes 3 are formed in the surface protective film 9, the resolution of the photosensitive resin is reduced to make the trajectory of the light boundary equal at the edge of the mask pattern, that is, the edge which is the effective boundary of the pattern. The grooves 13 are formed by communicating the holes 3 with each other in a clear shape.
Can also be formed. Further, as shown in FIG. 9B, similarly to the case where the grooves 13 are multiplexed in the surface protective film 9, the holes 3 are multiplexed in the surface protective film 9, without impairing the strength of the surface protective film 9. In addition, it is possible to sufficiently realize a function of radiating heat by the reflow operation.
【００４５】また、本発明に係る半導体集積回路装置
は、フリップチップ構造において説明したが、通常のモ
ールド封止パッケージやボールグリッドアレイ（ＢＧ
Ａ）に適用しても同様の効果が得られると考えられる。The semiconductor integrated circuit device according to the present invention has been described with reference to the flip chip structure.
It is considered that the same effect can be obtained by applying the method to A).
【００４６】[0046]
【発明の効果】以上に記載した様に、本発明に係る半導
体集積回路装置によれば、カバースルーホールを取り巻
くように表面保護膜内に孔又は溝を形成することで、半
田ボールを介して表面保護膜に掛かる熱による応力が前
記孔又は溝によって緩衝される。従って、表面保護膜の
亀裂を防止する高信頼性の半導体集積回路装置を提供す
ることが可能となる。また、前記溝の形成には、感光性
ポリイミド樹脂の解像度以下のパターンを用いることに
より、複雑な構造あるいは余分な工程を加えることな
く、半導体集積回路装置を提供することが可能となる。As described above, according to the semiconductor integrated circuit device of the present invention, by forming a hole or a groove in the surface protective film so as to surround the cover through hole, the semiconductor integrated circuit device can be connected via the solder ball. Stress due to heat applied to the surface protection film is buffered by the holes or grooves. Therefore, it is possible to provide a highly reliable semiconductor integrated circuit device that prevents cracks in the surface protective film. In addition, by using a pattern having a resolution equal to or less than the resolution of the photosensitive polyimide resin for forming the groove, a semiconductor integrated circuit device can be provided without adding a complicated structure or an extra step.
【００４７】[0047]
【図１】本発明に係る半導体集積回路装置の一実施例に
おけるＬＳＩチップの平面図FIG. 1 is a plan view of an LSI chip in one embodiment of a semiconductor integrated circuit device according to the present invention.
【図２】図１におけるパッド電極付近を拡大した平面図FIG. 2 is an enlarged plan view showing the vicinity of a pad electrode in FIG. 1;
【図３】図２に記載されたＡ−Ａ’線における断面図FIG. 3 is a sectional view taken along line A-A ′ shown in FIG. 2;
【図４】本発明に係る半導体集積回路装置の製造方法の
一例を工程順に示す断面図FIG. 4 is a sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device according to the present invention in the order of steps.
【図５】本発明に係る半導体集積回路装置の製造方法の
一例を工程順に示す断面図FIG. 5 is a sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device according to the present invention in the order of steps.
【図６】本発明に係る半導体集積回路装置の製造方法の
一例を工程順に示す断面図FIG. 6 is a sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device according to the present invention in the order of steps.
【図７】本発明に係る半導体集積回路装置の半田ボール
形成後の断面図FIG. 7 is a sectional view of the semiconductor integrated circuit device according to the present invention after the formation of solder balls;
【図８】本発明に係る半導体集積回路装置の他の実施の
形態における、パッド電極付近の平面図FIG. 8 is a plan view showing the vicinity of a pad electrode in another embodiment of the semiconductor integrated circuit device according to the present invention.
【図９】本発明に係る半導体集積回路装置の他の実施の
形態における、パッド電極付近の平面図FIG. 9 is a plan view showing the vicinity of a pad electrode in another embodiment of the semiconductor integrated circuit device according to the present invention.
【図１０】従来技術におけるＬＳＩチップの平面図FIG. 10 is a plan view of a conventional LSI chip.
【図１１】従来技術における、一つのパッド電極付近を
拡大した平面図FIG. 11 is an enlarged plan view showing the vicinity of one pad electrode in the related art.
【図１２】図１１に記載されたＢ−Ｂ’線における断面
図FIG. 12 is a sectional view taken along the line BB ′ shown in FIG. 11;
【図１３】従来技術における半導体集積回路装置の製造
工程図FIG. 13 is a manufacturing process diagram of a semiconductor integrated circuit device according to a conventional technique.
【図１４】従来技術における半導体集積回路装置の製造
工程図FIG. 14 is a manufacturing process diagram of a semiconductor integrated circuit device according to a conventional technique.
【図１５】従来技術における半導体集積回路装置の製造
工程図FIG. 15 is a manufacturing process diagram of a semiconductor integrated circuit device according to a conventional technique.
【図１６】従来技術における、半田ボール形成後の半導
体集積回路装置の断面図FIG. 16 is a cross-sectional view of a semiconductor integrated circuit device after a solder ball is formed in a conventional technique.
１．シリコン基板 ２．パッド電極 ３．孔 ４．第１の層間絶縁膜 ５．第１層配線 ６．第２の層間絶縁膜 ７．第２層配線 ８．第３の層間絶縁膜 ９．表面保護膜 １０．バリアメタル １１．カバースルーホール １２．フォトレジスト膜 １３．溝 １４．石英基板 １５．Ｃｒマスク １６．パターンＡ １７．パターンＢ １８．半田ボール Ａ．ＬＳＩチップ 1. 1. Silicon substrate 2. Pad electrode Hole 4. 4. First interlayer insulating film First layer wiring 6. 6. Second interlayer insulating film 7. Second layer wiring 8. Third interlayer insulating film Surface protective film 10. Barrier metal 11. Cover through hole 12. Photoresist film 13. Groove 14. Quartz substrate 15. Cr mask 16. Pattern A 17. Pattern B 18. Solder ball A. LSI chip
Claims (11)
保護膜と、パッド電極上の前記表面保護膜に形成された
カバースルーホールとを有する半導体集積回路装置にお
いて、カバースルーホールの外周囲に熱放射部が設けら
れていることを特徴とする半導体集積回路装置。In a semiconductor integrated circuit device having a pad electrode, a surface protection film covering the pad electrode, and a cover through hole formed in the surface protection film on the pad electrode, the semiconductor device is provided around a periphery of the cover through hole. A semiconductor integrated circuit device provided with a heat radiation part.
特徴とする請求項１に記載の半導体集積回路装置。2. The semiconductor integrated circuit device according to claim 1, wherein said heat radiating portion is formed with a hole.
とを特徴とする請求項２に記載の半導体集積回路装置。3. The semiconductor integrated circuit device according to claim 2, wherein said holes are formed in a surface protection film.
徴とする請求項２又は請求項３に記載の半導体集積回路
装置。4. The semiconductor integrated circuit device according to claim 2, wherein said hole is formed in an annular shape.
とを特徴とする請求項４に記載の半導体集積回路装置。5. The semiconductor integrated circuit device according to claim 4, wherein said holes are formed in multiple annular shapes.
特徴とする請求項１に記載の半導体集積回路装置。6. The semiconductor integrated circuit device according to claim 1, wherein said heat radiating portion is formed with a groove.
とを特徴とする請求項６に記載の半導体集積回路装置。7. The semiconductor integrated circuit device according to claim 6, wherein said groove is formed in a surface protection film.
徴とする請求項６又は請求項７に記載の半導体集積回路
装置。8. The semiconductor integrated circuit device according to claim 6, wherein said groove is formed in an annular shape.
とを特徴とする請求項８に記載の半導体集積回路装置。9. The semiconductor integrated circuit device according to claim 8, wherein said grooves are formed in multiple annular shapes.
る表面保護膜にカバースルーホールを形成する半導体集
積回路装置の製造方法において、前記表面保護膜に、感
光性樹脂の解像度以下のサイズのパターンを用いて溝を
形成することを特徴とする半導体集積回路装置の製造方
法。10. A method of manufacturing a semiconductor integrated circuit device, wherein a surface protective film is formed on a pad electrode and a cover through hole is formed in the surface protective film. Forming a groove by using the pattern of (1).
以下のサイズのパターンを用いて孔を形成することを特
徴とする請求項１０に記載の半導体集積回路装置の製造
方法。11. The method for manufacturing a semiconductor integrated circuit device according to claim 10, wherein holes are formed in said surface protective film using a pattern having a size smaller than the resolution of a photosensitive resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36033698A JP3173488B2 (en) | 1998-12-18 | 1998-12-18 | Semiconductor integrated circuit device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36033698A JP3173488B2 (en) | 1998-12-18 | 1998-12-18 | Semiconductor integrated circuit device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000183108A true JP2000183108A (en) | 2000-06-30 |
| JP3173488B2 JP3173488B2 (en) | 2001-06-04 |
Family
ID=18468965
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP36033698A Expired - Fee Related JP3173488B2 (en) | 1998-12-18 | 1998-12-18 | Semiconductor integrated circuit device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3173488B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003100744A (en) * | 2001-09-21 | 2003-04-04 | Ricoh Co Ltd | Semiconductor device and method of manufacturing the same |
| JP2010171253A (en) * | 2009-01-23 | 2010-08-05 | Toshiba Corp | Semiconductor device, and manufacturing method thereof |
| JP2013115054A (en) * | 2011-11-24 | 2013-06-10 | Rohm Co Ltd | Semiconductor chip and semiconductor package |
| JP2013128145A (en) * | 2013-03-11 | 2013-06-27 | Rohm Co Ltd | Semiconductor device |
| JP2015097244A (en) * | 2013-11-15 | 2015-05-21 | 日立オートモティブシステムズ株式会社 | Semiconductor integrated circuit |
| WO2018186131A1 (en) * | 2017-04-06 | 2018-10-11 | 株式会社デンソー | Semiconductor device |
-
1998
- 1998-12-18 JP JP36033698A patent/JP3173488B2/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003100744A (en) * | 2001-09-21 | 2003-04-04 | Ricoh Co Ltd | Semiconductor device and method of manufacturing the same |
| JP2010171253A (en) * | 2009-01-23 | 2010-08-05 | Toshiba Corp | Semiconductor device, and manufacturing method thereof |
| JP2013115054A (en) * | 2011-11-24 | 2013-06-10 | Rohm Co Ltd | Semiconductor chip and semiconductor package |
| JP2013128145A (en) * | 2013-03-11 | 2013-06-27 | Rohm Co Ltd | Semiconductor device |
| JP2015097244A (en) * | 2013-11-15 | 2015-05-21 | 日立オートモティブシステムズ株式会社 | Semiconductor integrated circuit |
| WO2018186131A1 (en) * | 2017-04-06 | 2018-10-11 | 株式会社デンソー | Semiconductor device |
| JP2018181962A (en) * | 2017-04-06 | 2018-11-15 | 株式会社デンソー | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3173488B2 (en) | 2001-06-04 |
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