JP2000164622A - Chip-sized package and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability of a chip-sized package. SOLUTION: When an Al electrode 1 is formed, this electrode material is formed and continuously a Ti nitride film 5 is formed. By performing patterning in one sitting via a photoresist layer PR1, the patterning is enabled accurately in virtue of function of the Ti nitride film 5 as an antireflection film, and functions as a barrier metal can be obtained. By the formation of the Ti nitride film 5, diffusion of a thin film layer of Cu which turns into a plating electrode can be prevented. By adjusting the thickness of the Ti nitride film 5, it functions as the antireflection film and the barrier metal, so that the halation of resist can be prevented at the same time as the barrier function, and the patterning of the Al electrode can be formed with high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a chip size package and a method for manufacturing the same. The chip size package (Chip Size Package) is also referred to as a CSP, and is a general term for packages having a size equal to or slightly larger than the chip size, and is a package for high-density mounting. The present invention relates to a barrier metal for a plating electrode used in a CSP.

[0002]

2. Description of the Related Art Conventionally, in this field, BGA (Ba
ll Grid Array), a structure with a plurality of solder balls arranged in a plane, a fine pitch BGA, a structure in which the ball pitch of the BGA is further narrowed and the outer shape is close to the chip size, etc. Are known. Recently, "Nikkei Micro Devices", August 1998
There is a wafer CSP described in Monthly Pages 44-71. This wafer CSP is basically a CSP in which wiring or array-like pads are formed by a wafer process (pre-process) before dicing a chip. It is expected that this technology will integrate the wafer process and the package process (post-process), thereby greatly reducing the package cost. Wafer CSP
Are classified into a sealing resin type and a rewiring type. The sealing resin mold has a structure in which the surface is covered with a sealing resin, similarly to a conventional package, and has a structure in which metal posts are formed on a wiring layer on the chip surface and the periphery thereof is solidified with the sealing resin.

It is generally said that when a package is mounted on a printed circuit board, stress generated due to a difference in thermal expansion between the printed circuit board and the printed circuit board concentrates on the metal post. It is believed to be decentralized.

On the other hand, the rewiring type has a structure in which a rewiring is formed without using a sealing resin as shown in FIG. That is, an Al electrode 52, a wiring layer 53, and an insulating layer 54 are stacked on the surface of the chip 51, a metal post 55 is formed on the wiring layer 53, and a solder bump 56 is formed thereon.
The wiring layer 53 is used as rewiring for arranging the solder bumps 56 on the chip in a predetermined array.

[0005] The sealing resin mold has a metal post of 100 μm.
By lengthening it and reinforcing it with sealing resin,
High reliability is obtained. However, the process of forming the sealing resin needs to be performed using a mold in a later step, and the process becomes complicated.

On the other hand, the rewiring type has an advantage that the process is relatively simple and most of the steps can be performed by a wafer process. However, there is a need to relieve stress in some way to increase reliability.

FIG. 10 omits the wiring layer 53 of FIG. 9 and forms an opening in which the Al electrode 52 is exposed. In this opening, a metal post 55 and the Al electrode 52 are formed.
, A barrier metal 58 is formed at least one layer, and a solder ball 56 is formed on the metal post 55.

[0008]

However, in FIG. 9, since the wiring layer 53 is formed by Cu plating, a Cu thin film is formed as a plating electrode, and a barrier metal is formed between the Cu thin film and the Al electrode 52. A Cr film was employed. In FIG. 10, since the metal post 55 is formed by Cu plating, a Cu thin film is also formed as a plating electrode, and Cr is employed as a barrier metal between the Cu thin film and the Al electrode 52. This thin film of Cr is used as the Al electrode 52
After forming the opening for exposing the hole, it was formed by the lift-off method, so that the processing accuracy was poor and there was a drawback that the number of steps increased by this amount.

[0009]

SUMMARY OF THE INVENTION A chip size package and a method of manufacturing the same according to the present invention have been made in view of the above problems, and
In a chip size package in which solder balls are formed on Al electrodes, the problem is solved by forming a TiN film on metal electrode pads.

A TiN film is formed on the metal electrode pad, and a Cu nitride film is formed on the TiN film exposed from the opening.
This is solved by forming a metal post on the Cu film. Also, in a chip size package employing a wiring layer mainly composed of Cu, the problem is solved by forming a Ti nitride film on a metal electrode pad. A TiN film is formed on the metal electrode pad, and the TiN film exposed from the opening is formed.
The problem is solved by forming a Cu film on the film and forming metal posts on the Cu film.

Further, the present invention solves the problem by forming the Ti nitride film on the metal electrode pad so as to have both the antireflection film and the barrier metal.

In the manufacturing method, an electrode material mainly composed of Al and a Ti nitride film are deposited, and the Ti nitride film is used as an anti-reflection film and patterned to form a metal electrode pad. Covering the chip surface including the electrode pad with an insulating layer, forming an opening in the insulating layer on the metal pad,
This problem is solved by forming a Cu film in the opening, forming a metal post on the Cu film, and then forming a solder bump on the metal post.

The Ti nitride film can be solved by adjusting its thickness so as to function as a barrier metal of the Cu film together with the antireflection film.

Further, an electrode material mainly composed of Al,
a first opening having a first opening for exposing a part of the metal electrode pad by depositing an i-film and patterning by utilizing the Ti nitride film as an anti-reflection film to form a metal electrode pad; Forming an insulating layer, forming a Cu film on the Ti nitride film exposed from the first opening, forming a wiring layer of Cu extending on a chip surface on the Cu film, A chip surface including a wiring layer is covered with a second insulating layer having a second opening exposing a part of the wiring layer, and a metal post is formed in the second opening. In the method of manufacturing a chip size package having a solder bump formed thereon, the Ti nitride film is solved by adjusting the film thickness so as to function as a barrier metal of the Cu film together with the antireflection film. Is what you do.

[0015]

Next, an embodiment of the present invention will be described. FIGS. 7 and 8 show solder balls formed directly on Al electrodes formed on the surface of an IC chip.
1 to 6 show an example in which a wiring layer is extended and formed thereon.

First, the former embodiment will be described.

As the number of elements of the semiconductor IC increases, one-layer metal, two-layer metal, three-layer metal, etc. are adopted.
A passivation film such as a Si nitride film or PIX is coated on the uppermost metal.

In FIG. 7 and FIG. 8, the metal of the uppermost layer (hereinafter referred to as Al electrode) is shown in FIG.
The interlayer insulating film in which the contact hole is formed is shown in FIG. Further, the passivation film is shown in FIG. Here, the passivation film 3 is made of a Si nitride film, an epoxy resin, PIX, or the like. The point of the present invention lies in the barrier layer 5 provided on the Al electrode 1. Here, a high melting point metal is preferable, and a Ti nitride film (TiN) 5 is used. Since this film 5 is effective as a barrier metal and also as an antireflection film, both can be provided by adjusting the film thickness, and the accuracy of photolithography can be improved. Can be prevented from diffusing into the Al electrode 1.

Subsequently, the passivation film 3 has
An opening 4 exposing the TiN film 5 is formed, and a Cu thin film layer 6 is formed here as a plating electrode of the metal post 7. The Cu thin film layer 6 is patterned so as to extend into and around the opening.

Further, a metal post 7 is formed on the Cu thin film layer 6. This metal post 7
Is made of, for example, Cu, Au, or the like having a good affinity for the solder ball 8. Here, the Cu thin film layer 6 is used as a plating electrode, and C
u metal posts are formed by plating.

Then, solder balls 8 are formed. Here, the solder balls 8 are formed on the underlying Cu by electrolytic plating.

A feature of the present invention is that a Ti nitride film is provided as a barrier metal in order to prevent the Cu thin film layer 6 from diffusing into the Al electrode 1. In addition, when the Al electrode 1 is applied, it is formed continuously and formed by self-alignment. Instead of forming Cr by lift-off as in the prior art, it can be formed simultaneously by patterning of the Al electrode, so that the number of photolithography steps can be reduced. Thus, highly accurate patterning of the barrier metal 5 can be performed.

FIG. 8 shows the shape of a solder ball. Here, the solder ball is considered as a part of a sphere, and the point S is shown as its center. When the outermost peripheral portion of the solder ball 8 and the lower layer film (here, the Cu thin film layer 6 is a metal post 7) is denoted by C, the solder ball 8
The point is that the extending surface of the surface extends inward from point C upward.

That is, a concave portion 9 is formed on the surface of the Al electrode 1 or the metal post 7, and the center S (or the dotted line extending horizontally from the point S) of the solder ball 8 is equal to or lower than the point C. If it is constituted so that it may become, solder ball 8
Does not cause a neck, and the strength can be improved.

In FIG. 10, the point S is located above the point C, and the upward and downward directions of the arrows have extending surfaces inward. Therefore, the portion of the solder ball that is in contact with the metal post or the barrier metal has a small diameter and a neck, and has a structure that is weak against stress.

In the present application, the size of the solder ball is assumed to be constant, and the amount of solder accommodated in the recess increases, so that the center S of the solder sinks downward. Moreover, since the solder ball spreads over the entire area of the formed metal post 7 (or Cu thin film layer 6), the height of the solder ball can be reduced accordingly. That is, the formation of the neck can be prevented and the height of the solder ball can be adjusted.

Next, a second embodiment will be described with reference to FIG. This embodiment employs a wiring layer 53 as shown in FIG. FIG. 6 shows a two-layer metal transistor, in which 10 and 11 are source and drain regions, and 12 is a gate. 13 is a source electrode and its wiring, and 14 is a drain electrode and its wiring. The Al electrode 1 is in contact with the drain electrode 14 as a second layer metal.

Also in this case, in the ordinary wire bonding type IC chip, the uppermost layer metal (portion which also functions as a bonding pad) is shown in FIG. 1 and the contact hole C of this Al electrode 1 is formed. The interlayer insulating film is shown in FIG. Further, the passivation film is shown in FIG. Here, the passivation film 3 is made of a Si nitride film, an epoxy resin, PIX, or the like.

Here, a Ti nitride film 5 which is a point of the present invention is formed on the Al electrode 1.

Subsequently, an opening 15 for exposing the Ti nitride film 5 is formed in the passivation film 3, where a Cu thin film layer 6 is formed as a plating electrode of a wiring layer. On this, the wiring layer 16 by Cu plating is formed.
Is formed.

Subsequently, a resin layer 17 made of an insulating resin such as polyimide is formed, and an opening 18 is formed at an end of the wiring layer 16.
In the opening 18, a thin film layer 19 of Cu is formed as a plating electrode of the metal post 7, and the metal post 7 is formed thereon. Also metal post 7
On top of this, a Ni thin film layer 20 and a Cu thin film layer (or Au layer) 21 are formed from below. These metal 1
9, 7, 20, and 21 are patterned so as to extend into and around the opening.

A solder ball 8 is formed on the Cu thin film layer (or Au thin film layer). Here, the solder balls 8 are formed by electrolytic plating using the underlying Cu thin film layer 21 as an electrode.

Next, a method of manufacturing the structure of FIG. 6 will be described more simply than FIG. First, a semiconductor substrate (wafer) on which an LSI having the Al electrode 1 is formed is prepared. Here, as described above, a two-layer metal IC is used.
The source electrode 13 and the drain electrode 14 of the transistor are formed as a first layer metal, and the Al electrode 1 in contact with the drain electrode 14 is formed as a second layer metal.

Here, after forming an opening of the interlayer insulating film 2 from which the drain electrode 14 is exposed, an electrode material mainly composed of Al and a Ti nitride film 5 are formed on the entire surface of the wafer, and an Al film is formed using the photoresist PR1 as a mask. Electrode 1 and Ti nitride film 5
Are dry-etched into a predetermined shape. Therefore,
The photoresist PR1 including the TiN film as a barrier metal can be formed at a time with the photoresist PR1, and the number of steps can be simplified.

The Ti nitride film 5 functions as a barrier metal for a Cu thin film layer 6 to be formed later. However, attention is also paid to the fact that the Ti nitride film is effective as an antireflection film. That is, it is also effective for preventing halation of the resist used in patterning. To prevent halation, a minimum of about 1200 ° to 1300 ° is required, and in order to provide a barrier metal function, it is preferably about 2000 ° to 3000 °. (See FIG. 1 above.) Subsequently, the surface of the semiconductor substrate is covered with a passivation film 3 such as a SiN film or PIX.

The Al electrode 1 also serves as a pad for external connection of the LSI, and functions as a wire bonding pad when it is not formed as a chip size package composed of solder balls.

In order to expose a part of the Al electrode 1,
The passivation film 3 is removed by etching,
A thin film layer 6 of Cu is formed on the entire surface. This Cu thin film layer 6
Will be the plating electrodes of the wiring layer 16 later.

Subsequently, for example, a photoresist layer PR is formed on the entire surface.
2, a portion corresponding to the wiring layer 16 is removed, and the Cu thin film layer 6 exposed in the opening is used as a plating electrode.
The wiring layer 16 is formed. This wiring layer 16 needs to be formed to a thickness of about 5 μm in order to secure mechanical strength.
Here, it is formed using a plating method, but may be formed by vapor deposition, sputtering, or the like. Thereafter, the photoresist layer PR2 is removed, and the Cu thin film layer 6 is etched away using the wiring layer 16 as a mask. Next, a polyimide layer 17 is applied to the entire surface, and the opening 1 is formed in the polyimide layer 17 on the wiring layer 16 by exposure and development.
8 is formed. The film thickness is at most 20 μm to 25 μm. The diameter of the opening is preferably about 50 μm. After the development, the polyimide layer may be baked at a temperature of about 200 ° C. Next, a Cu thin film layer 19 is formed on the entire surface as a plating electrode of the metal post 7. (Refer to FIG. 3 above.) Subsequently, a photoresist layer PR3 in which a metal post region to be formed is exposed is formed, and a metal post 7 made of Cu is formed via an electrode 19 for plating. Further, a Ni thin film layer 20 and a Cu thin film layer 21 are formed on the metal posts 7. (See FIG. 4 above.) Further, the solder plating layer 8 is formed via the photoresist layer PR3.
To form Finally, the photoresist layer PR3 is removed, and unnecessary portions of the seed layers 21, 20, 7, and 19 are removed by etching using the solder plating layer as a mask. Then, the semiconductor substrate is divided into chips along the scribe lines by a dicing process, thereby completing a chip-size package. Here, the timing of melting the solder into spherical solder balls is after removing the seed layer and before dicing, or after dicing.

Although the present invention has been described with reference to the rewiring type, it goes without saying that the present invention can also be implemented with a resin-sealed type.

[0040]

According to the present invention, by forming a Ti nitride film on a metal electrode pad, diffusion of a Cu thin film layer serving as a plating electrode can be prevented. In addition, the Ti nitride film functions as an anti-reflection film and a barrier metal by adjusting the thickness thereof, so that it is possible to prevent the halation of the resist simultaneously with the barrier function and to form the Al electrode with high precision. In addition, since the photolithography process using only the barrier metal can be omitted, the process can be simplified.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a method for manufacturing a chip size package according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a method of manufacturing a chip size package according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a method for manufacturing a chip size package according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating a method of manufacturing a chip size package according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating a method of manufacturing a chip size package according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating a method of manufacturing a chip size package according to the embodiment of the present invention.

FIG. 7 is a diagram illustrating a chip size package according to an embodiment of the present invention.

FIG. 8 is a diagram illustrating a chip size package according to an embodiment of the present invention.

FIG. 9 is a diagram illustrating a conventional chip size package.

FIG. 10 is a diagram illustrating a conventional chip size package.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hiroyuki Shinoki 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Nobuyuki Takai 2-chome, Keihanhondori, Moriguchi-shi, Osaka No. 5 Sanyo Electric Co., Ltd.

Claims (7)

[Claims] 1. An insulating layer for covering a chip surface including a metal electrode pad made of Al as a main material, an opening formed in the insulating layer on the metal pad, and a Cu formed in the opening.
In a chip size package comprising a metal post mainly composed of: and a solder bump fixed to the metal post, a barrier layer is formed on the metal electrode pad. . 2. An insulating layer for covering a chip surface including a metal electrode pad made of Al as a main material, an opening formed in the insulating layer on the metal pad, and Cu formed in the opening.
In a chip size package including a metal post mainly composed of: and a solder bump fixed to the metal post, a barrier layer is formed on the metal electrode pad, and the barrier layer is exposed from the opening. A chip size package, wherein the Cu film is formed on a layer, and the metal post is formed on the Cu film. 3. A wiring layer connected to a metal electrode pad mainly made of Al and extending on a chip surface and mainly made of Cu, an insulating layer covering the chip surface including the wiring layer, and the wiring In a chip size package including an opening formed in an insulating layer on a layer, a metal post formed in the opening, and a solder bump fixed to the metal post, Is a chip size package in which a barrier layer is formed. 4. A wiring layer mainly composed of Cu connected to a metal electrode pad mainly composed of Al and extending on a chip surface, an insulating layer covering the chip surface including the wiring layer, and the wiring In a chip size package including an opening formed in an insulating layer on a layer, a metal post formed in the opening, and a solder bump fixed to the metal post, A barrier layer is formed, on the barrier layer exposed from the opening,
A chip size package wherein the Cu film is formed and the metal post is formed on the Cu film. 5. The chip according to claim 1, wherein the barrier layer is a TiN film, and has both an antireflection film and a barrier metal on the metal electrode pad. Size package. 6. A metal electrode pad is formed by depositing an electrode material mainly composed of Al, depositing a Ti nitride film on the electrode material, and patterning the Ti nitride film as an anti-reflection film. Covering the chip surface including the metal electrode pad with an insulating layer, forming an opening in the insulating layer on the metal pad, forming a Cu film in the opening, and forming a metal post on the Cu film. In the method of manufacturing a chip size package in which a solder bump is formed on a metal post after the formation, the Ti nitride film is formed so as to function as a barrier metal of the Cu film together with an antireflection film. A method for manufacturing a chip size package, wherein the thickness is adjusted. 7. An electrode material mainly composed of Al is deposited, a TiN film is deposited on the electrode material, and the TiN film is used as an anti-reflection film and patterned to form the metal electrode pad. Forming a first insulating layer having a first opening exposing a part of the metal electrode pad;
Forming a Cu film on the Ti nitride film exposed from the opening, forming a wiring layer of Cu extending on the chip surface on the Cu film, and forming a wiring layer on the chip surface including the wiring layer,
A second opening having a second opening exposing a part of the wiring layer;
Forming a metal post in the second opening, and then forming a solder bump on the metal post. The method of manufacturing a chip size package, comprising: A method of manufacturing a chip size package, wherein the thickness of the Cu film is adjusted so as to function also as a barrier metal of the Cu film.