WO2018186131A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2018186131A1
WO2018186131A1 PCT/JP2018/009849 JP2018009849W WO2018186131A1 WO 2018186131 A1 WO2018186131 A1 WO 2018186131A1 JP 2018009849 W JP2018009849 W JP 2018009849W WO 2018186131 A1 WO2018186131 A1 WO 2018186131A1
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WO
WIPO (PCT)
Prior art keywords
separation
surface electrode
electrode
semiconductor chip
film
Prior art date
Application number
PCT/JP2018/009849
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French (fr)
Japanese (ja)
Inventor
正範 大島
英二 林
Original Assignee
株式会社デンソー
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Publication date
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Publication of WO2018186131A1 publication Critical patent/WO2018186131A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present disclosure relates to a semiconductor device having a surface electrode formed on the surface of a semiconductor substrate and a back electrode formed on the back surface.
  • a semiconductor device having a surface electrode formed on the surface of a semiconductor substrate and a back electrode formed on the back surface is known.
  • the thickness of the semiconductor substrate has been reduced in order to reduce the loss.
  • the structure such as the film thickness is different between the front electrode and the back electrode.
  • the semiconductor device may be warped due to the thin plate and the difference in the bimetal effect between the front and back sides.
  • the surface electrode to be soldered is divided into a plurality of parts in both the row direction and the column direction perpendicular to the plate thickness direction by a protective film in order to reduce warpage. .
  • the protective film is formed using a hygroscopic material such as polyimide.
  • a hygroscopic material such as polyimide.
  • This disclosure is intended to provide a semiconductor device that can effectively suppress the generation of voids in solder on a surface electrode while reducing warpage.
  • a semiconductor device includes a semiconductor substrate having a front surface and a back surface opposite to the front surface in the plate thickness direction, on which elements are formed, and provided on the front surface and soldered.
  • a protection formed using a hygroscopic material having a first separation part that divides the surface electrode in the column direction and a second separation part that extends in the column direction in the region and divides the surface electrode in the row direction A film, and a back electrode provided on the back surface.
  • the first separation part and the second separation part are provided apart from each other so as not to cross each other.
  • the protective film has the first separation portion extending in the row direction and the second separation portion extending in the column direction, and the surface electrode is thereby separated, the warp of the semiconductor device is reduced. Can be reduced.
  • the protective film does not have an intersection between the first separation part and the second separation part, the retention of water vapor generated by moisture absorption of the protective film is suppressed, and consequently, the generation of voids in the solder on the surface electrode is suppressed. can do.
  • a semiconductor device has a front surface and a back surface opposite to the front surface in the thickness direction, and is provided with a semiconductor substrate on which elements are formed, and is soldered.
  • a surface electrode, a peripheral portion provided around the surface electrode on the surface, and a column extending in a row direction orthogonal to the plate thickness direction in a region surrounded by the peripheral portion and orthogonal to the plate thickness direction and the row direction A first separation portion that divides the surface electrode in the direction, a second separation portion that extends in the column direction in the region and divides the surface electrode in the row direction, and an intersection of the first separation portion and the second separation portion
  • the first separation part and the second separation part are provided apart from the peripheral part so as not to be connected to the peripheral part.
  • the protective film has the first separation portion extending in the row direction and the second separation portion extending in the column direction, and the surface electrode is thereby separated, the warp of the semiconductor device is reduced. Can be reduced.
  • the protective film has a crossing portion, the first separation portion and the second separation portion are provided apart from the surrounding portion. Thereby, it can suppress that the water
  • FIG. 5 It is a top view for demonstrating void generation in a comparative example. It is sectional drawing which follows the XX line of FIG. 5 for demonstrating void generation
  • the thickness direction of the semiconductor substrate is referred to as the Z direction.
  • a direction perpendicular to the Z direction and the extending direction of the first separation portion is indicated as an X direction.
  • the direction orthogonal to both the Z direction and the X direction, that is, the extending direction of the second separation portion is indicated as the Y direction.
  • the shape along the XY plane is a planar shape.
  • the semiconductor module 10 includes a semiconductor chip 12, a sealing resin body 14, a signal terminal 18, a terminal 22, a heat sink 26, a main terminal 28, a heat sink 32, and a main terminal 34.
  • a semiconductor module 10 is used for a main inverter of a hybrid vehicle or an electric vehicle, for example.
  • the semiconductor module 10 includes one semiconductor chip 12.
  • the semiconductor module 10 constitutes one of six arms constituting a three-phase inverter. Since such a semiconductor module 10 includes one arm in the package, it is also referred to as a 1 in 1 package.
  • the semiconductor chip 12 is formed with an element in which a current flows in the Z direction which is the thickness direction, a so-called vertical element.
  • the semiconductor chip 12 corresponds to a semiconductor device. MOSFET, IGBT, etc. are employable as a vertical element.
  • the semiconductor chip 12 has electrodes on both sides in the Z direction.
  • a pad for the signal terminal 18 is provided on one surface.
  • the sealing resin body 14 is made of, for example, an epoxy resin.
  • the sealing resin body 14 is formed by transfer molding.
  • the sealing resin body 14 has a substantially rectangular planar shape.
  • the sealing resin body 14 has one surface 14a orthogonal to the Z direction, a back surface 14b opposite to the one surface 14a, and side surfaces.
  • the one surface 14a and the back surface 14b are flat surfaces, for example.
  • the sealing resin body 14 seals the semiconductor chip 12.
  • a signal terminal 18 is connected to a pad (a pad 129 described later) of the semiconductor chip 12 through a bonding wire 16.
  • the signal terminal 18 extends in the Y direction, and protrudes to the outside from one side surface 14 c of the sealing resin body 14. Thereby, the signal terminal 18 can be electrically connected to an external device.
  • the signal terminal 18 may be formed integrally with the heat sink 32 as a part of the lead frame, or the signal terminal 18 of another member may be connected to the heat sink 32.
  • a terminal 22 is connected to one electrode (surface electrode 121 described later) of the semiconductor chip 12 via a solder 20.
  • the terminal 22 is interposed between the semiconductor chip 12 and the heat sink 26.
  • the terminal 22 transfers heat generated by the semiconductor chip 12 to the heat sink 26.
  • the terminal 22 electrically relays the semiconductor chip 12 and the heat sink 26.
  • the terminal 22 is formed using a metal material (for example, Cu) in order to ensure thermal conductivity and electrical conductivity.
  • the terminal 22 has a substantially rectangular parallelepiped shape.
  • a heat sink 26 is connected to the surface of the terminal 22 opposite to the semiconductor chip 12 via a solder 24.
  • the heat sink 26 radiates heat generated by the semiconductor chip 12 to the outside of the semiconductor module 10.
  • the heat sink 26 electrically relays the semiconductor chip 12 and the main terminal 28.
  • the heat sink 26 is formed using a metal material (for example, Cu) having excellent thermal conductivity and electrical conductivity.
  • the surface of the heat sink 26 opposite to the terminal 22 is a heat radiating surface 26 a exposed from the one surface 14 a of the sealing resin body 14.
  • the one surface 14a and the heat radiation surface 26a are substantially flush.
  • the surface facing the terminal 22 and the side surface connecting the facing surface and the heat radiating surface 26 a are covered with the sealing resin body 14.
  • a main terminal 28 is connected to the heat sink 26.
  • the main terminal 28 is electrically connected to the semiconductor chip 12 via the terminal 22 and the heat sink 26.
  • the main terminal 28 extends from the heat sink 26 in the Y direction and on the side opposite to the signal terminal 18.
  • the main terminal 28 projects outward from a side surface 14d opposite to the side surface 14c from which the signal terminal 18 projects. Thereby, the main terminal 28 can be electrically connected to an external device.
  • the main terminal 28 may be formed integrally with the heat sink 26 as a part of the lead frame, or a separate main terminal 28 may be connected to the heat sink 26.
  • a heat sink 32 is connected to the other electrode of the semiconductor chip 12 (a back electrode 130 described later) via a solder 30. Like the heat sink 26, the heat sink 32 radiates the heat generated by the semiconductor chip 12 to the outside of the semiconductor module 10. The heat sink 32 electrically relays the semiconductor chip 12 and the main terminal 34.
  • the heat sink 32 is also formed using a metal material (for example, Cu) excellent in thermal conductivity and electrical conductivity.
  • a surface of the heat sink 32 opposite to the semiconductor chip 12 is a heat radiating surface 32 a exposed from the back surface 14 b of the sealing resin body 14.
  • the back surface 14b and the heat dissipation surface 32a are substantially flush.
  • the surface facing the semiconductor chip 12 and the side surface connecting the facing surface and the heat radiating surface 32 a are covered with the sealing resin body 14.
  • the main terminal 34 is connected to the heat sink 32.
  • the main terminal 34 is electrically connected to the semiconductor chip 12 via the heat sink 32.
  • the main terminal 34 extends from the heat sink 32 in the Y direction and on the same side as the main terminal 28.
  • the main terminal 34 protrudes from the same side surface 14 d as the main terminal 28. Thereby, the main terminal 34 can be electrically connected to an external device.
  • the main terminal 34 may be formed integrally with the heat sink 32 as a part of the lead frame, or a separate main terminal 34 may be connected to the heat sink 32. In a plan view from the Z direction, the main terminals 28 and 34 are arranged side by side in the X direction.
  • the semiconductor chip 12 configured as described above, the semiconductor chip 12, the bonding wire 16, a part of the signal terminal 18, the solder 20, 24, 30, the terminal 22, the part of the heat sink 26, the part of the main terminal 28, the heat sink.
  • a part of 32 and a part of the main terminal 34 are sealed with the sealing resin body 14.
  • heat sinks 26 and 32 are disposed on both sides of the semiconductor chip 12, and heat can be radiated to the outside by the heat radiating surfaces 26a and 32a.
  • semiconductor chip 12 semiconductor device
  • the semiconductor chip 12 includes a semiconductor substrate 120, a surface electrode 121, a protective film 125, a pad 129, and a back electrode 130.
  • the front electrode 121 and the back electrode 130 correspond to the above-described double-sided electrodes.
  • the semiconductor substrate 120 is made of a known semiconductor material such as Si (silicon) or SiC (silicon carbide).
  • the above-described vertical element is formed on the semiconductor substrate 120.
  • an n-channel IGBT and an FWD (commutation diode) connected in reverse parallel to the IGBT are formed on a semiconductor substrate 120 made of Si. That is, RC-IGBT is formed on the semiconductor substrate 120. Note that the IGBT and the FWD can be formed on different semiconductor substrates.
  • the semiconductor substrate 120 has a substantially rectangular planar shape.
  • the semiconductor substrate 120 has a front surface 120a and a back surface 120b opposite to the front surface 120a in the Z direction.
  • an IGBT emitter region, a trench gate, an FWD anode region, and the like are formed in the active region (main region).
  • the active area has a substantially rectangular shape in plan view.
  • a breakdown voltage structure such as a guard ring is formed in the outer peripheral region surrounding the active region.
  • an IGBT collector region and an FWD cathode region are formed on the surface layer on the back surface 120b side.
  • a surface electrode 121, a protective film 125, and a pad 129 are formed on the surface 120 a of the semiconductor substrate 120.
  • the surface electrode 121 is formed corresponding to the active region.
  • the surface electrode 121 is an electrode that is electrically connected to the emitter region and the anode region. For this reason, the surface electrode 121 is also referred to as an emitter electrode.
  • the surface electrode 121 not only functions as an emitter electrode but also functions as an anode electrode of the FWD.
  • the front electrode 121 is also referred to as a main electrode because a current flows between the front electrode 121 and the back electrode 130.
  • the surface electrode 121 is formed on one end side in the Y direction in the semiconductor substrate 120 having a substantially rectangular plane.
  • the surface electrode 121 has a base film 122 and a metal thin film.
  • the base film 122 is formed using a material whose main component is Al (aluminum).
  • the base film 122 is formed by sputtering using AlSi as a material.
  • the thickness of the base film 122 is 5 ⁇ m, for example.
  • a metal thin film is formed on the base film 122 for the purpose of improving the bonding strength with the solder 20 and improving the wettability with respect to the solder 20.
  • a Ni film 123 and an Au film 124 are provided as metal thin films.
  • the Ni film 123 is formed using a material mainly composed of Ni (nickel). When Ni is used, for example, the bonding strength with the solder 20 can be improved.
  • the Ni film 123 is a plating film.
  • the electroless Ni plating film contains P (phosphorus) in addition to Ni as the main component.
  • the thickness of the Ni film 123 is, for example, 5 ⁇ m.
  • the Au film 124 is formed using a material whose main component is Au (gold). When Au is used, for example, wettability with the solder 20 can be improved. In the present embodiment, the Au film 124 is a plating film. The thickness of the Au film 124 is, for example, less than 1 ⁇ m (nm order). Thus, the surface electrode 121 has a multilayer film structure.
  • the protective film 125 is formed using a hygroscopic material such as polyimide.
  • the protective film 125 includes a peripheral portion 126, a first separation portion 127, and a second separation portion 128.
  • the peripheral portion 126 is provided on the surface 120a so as to surround the surface electrode 121.
  • the peripheral portion 126 is provided on the outer peripheral region so as to surround the active region.
  • the peripheral portion 126 has a rectangular ring shape.
  • the thickness of the portion without the base film 122 for example, the thickness of the peripheral portion 126, is substantially equal to the thickness of the laminated portion of the base film 122, the Ni film 123, and the Au film 124 in the surface electrode 121.
  • the first separation unit 127 and the second separation unit 128 are provided in a region surrounded by the peripheral portion 126, that is, in an active region.
  • the first separation unit 127 extends along the X direction, which is a first direction orthogonal to the Z direction.
  • the X direction corresponds to the row direction.
  • the protective film 125 has a plurality of first separators 127.
  • the inner peripheral surface of the peripheral portion 126 has a substantially rectangular planar shape.
  • the peripheral portion 126 has a pair of surfaces (hereinafter referred to as a first surface) orthogonal to the X direction and a pair of surfaces (hereinafter referred to as a second surface) orthogonal to the Y direction as inner peripheral surfaces. is doing.
  • the length between the first surfaces (opposite distance) is longer than the length between the second surfaces (opposite distance). That is, the inner peripheral surface has the X direction as the long direction and the Y direction as the short direction.
  • the first separation portion 127 is continuous with the inner peripheral surface of the peripheral portion 126.
  • the first separation part 127 extends from each of the first surfaces. Specifically, two first separation portions 127 are extended from each of the first surfaces. In the plurality of first separation portions 127, the extending lengths from the first surface are substantially equal to each other. The extended length is shorter than 1 ⁇ 2 of the length (opposite distance) between the pair of first surfaces.
  • the first separator 127 divides the surface electrode 121 in the Y direction, which is the second direction orthogonal to the Z direction.
  • the Y direction corresponds to the column direction.
  • the surface electrode 121 is divided into substantially equal lengths in the Y direction by two first separation portions 127 that are continuous with the same first surface. That is, the surface electrode 121 is divided into three equal parts by the first separator 127.
  • the first separation unit 127 is separated into two in the X direction.
  • the first separation portion 127 is provided on the base film 122, and the Ni film 123 and the Au film 124 that are metal thin films are separated by the first separation portion 127.
  • the second separation unit 128 extends along the Y direction.
  • the protective film 125 has one second separation unit 128.
  • the second separation part 128 is also connected to the inner peripheral surface of the peripheral part 126.
  • the second separation unit 128 extends from the second surface.
  • the second separation unit 128 is provided so as to straddle the second surface.
  • the extending length of the second separation portion 128 is substantially equal to the length (opposite distance) between the pair of second surfaces.
  • the second separator 128 divides the surface electrode 121 in the X direction.
  • the surface electrodes 121 are partitioned by the second separator 128 into substantially equal lengths in the X direction. That is, the surface electrode 121 is divided into two equal parts by the second separator 128.
  • the second separation portion 128 is also provided on the base film 122, and the Ni film 123 and the Au film 124 that are metal thin films are separated by the second separation portion 128.
  • the second separation unit 128 is provided in the center of the active region in the X direction.
  • Each first separation unit 127 is provided apart from the second separation unit 128 so as not to intersect the second separation unit 128, that is, not to be connected to the second separation unit 128.
  • the surface electrode 121 (metal thin film) has two-fold symmetry around the center 121a.
  • the protective film 125 has a predetermined gap between the second separator 128 and each first separator 127 in the X direction.
  • the Ni film 123 and the Au film 124 that are metal thin films are also disposed in the gap, that is, the region where the first separation portion 127 and the second separation portion 128 are opposed to each other.
  • This opposing region is a first connecting portion 121b that connects portions separated by the first separating portion 127 in the surface electrode 121.
  • the surface electrode 121 has four first connecting portions 121b.
  • the pad 129 is an electrode to which the signal terminal 18 is electrically connected.
  • the pad 129 also has a multilayer structure similar to that of the surface electrode 121.
  • the pad 129 is formed at a position different from the surface electrode 121 on the surface 120a.
  • the pad 129 is electrically separated from the surface electrode 121.
  • the pad 129 is formed at the end on the opposite side of the surface electrode 121 formation region in the Y direction.
  • the semiconductor chip 12 has five pads 129.
  • the pad 129 the potential of the anode potential of the temperature sensor (temperature-sensitive diode) for detecting the temperature of the semiconductor substrate 120, the cathode potential, the gate electrode, the current sense, and the potential of the surface electrode 121 (emitter electrode) are similarly used. It has a Kelvin emitter for detection.
  • the cathode potential, anode potential, gate electrode, current sense, and Kelvin emitter are formed in this order from one end side.
  • the five pads 129 are collectively formed on one end side in the Y direction and formed side by side in the X direction on the substantially rectangular planar semiconductor substrate 120. Each pad 129 is surrounded by a peripheral portion 126.
  • a back electrode 130 is formed on the back surface 120 b of the semiconductor substrate 120.
  • the back electrode 130 is an electrode that is electrically connected to the collector region and the cathode region. For this reason, the back electrode 130 is also referred to as a collector electrode.
  • the back electrode 130 not only functions as a collector electrode, but also serves as an FWD cathode electrode.
  • a current flows between the surface electrode 121 and the surface electrode 121, it is also called a main electrode.
  • the back electrode 130 is formed on almost the entire back surface 120b.
  • the back electrode 130 also has a multilayer structure.
  • the back electrode 130 also has a base film and a metal thin film.
  • the base film is made of AlSi and is formed by sputtering.
  • the metal thin film includes a Ni film and an Au film.
  • the Ni film is formed by sputtering.
  • the Au film is a plating film.
  • the thickness of the Ni film on the back electrode 130 is made thinner than the thickness of the Ni film 123 on the front electrode 121. Thereby, the thickness of the back electrode 130 is made thinner than the thickness of the front electrode 121 (thickness of the laminated portion).
  • each element constituting the semiconductor module 10 is prepared. That is, the semiconductor chip 12, the signal terminal 18, the terminal 22, the heat sink 26 connected with the main terminal 28, and the heat sink 32 connected with the main terminal 34 are prepared.
  • the semiconductor chip 12 having the surface electrode 121 and the protective film 125 described above is prepared.
  • the semiconductor chip 12 is disposed on the opposite surface of the heat sink 32 via the solder 30.
  • the semiconductor chip 12 is arranged so that the back electrode 130 faces the heat sink 32.
  • the terminal 22 in which the solders 20 and 24 are arranged on both sides in advance as the incoming solder is arranged so that the solder 20 is on the semiconductor chip 12 side.
  • the quantity which can absorb the height variation in the semiconductor module 10 is arrange
  • the solder 20, 24, 30 is reflowed (1st reflow), thereby connecting the back electrode 130 of the semiconductor chip 12 and the heat sink 32 via the solder 30. Further, the surface electrode 121 of the semiconductor chip 12 and the terminal 22 are connected via the solder 20. Since there is no heat sink 26 to be connected yet, the solder 24 has a shape that rises with the center of the surface facing the heat sink 26 as a vertex due to surface tension.
  • the pads 129 of the semiconductor chip 12 and the signal terminals 18 are connected by the bonding wires 16.
  • a connection body in which the semiconductor chip 12, the signal terminal 18, the terminal 22, and the heat sink 32 are integrated is obtained.
  • connection body and the heat sink 26 are connected via the solder 24.
  • the heat sink 26 is disposed on a pedestal (not shown) so that the surface facing the terminal 22 faces up.
  • a connection body is arrange
  • the load of the heat sink 26 is applied so that the height of the semiconductor module 10 becomes a predetermined height.
  • a spacer (not shown) is disposed between the heat sink 26 and the base, and the spacer is brought into contact with both the heat sink 26 and the base. In this way, the height of the semiconductor module 10 is set to a predetermined height.
  • the sealing resin body 14 is molded by a transfer mold method.
  • the sealing resin body 14 is molded so that the heat sinks 26 and 32 are completely covered. Then, by cutting the molded sealing resin body 14 together with a part of the heat sinks 26 and 32, the heat radiation surfaces 26a and 32a of the heat sinks 26 and 32 are exposed.
  • the sealing resin body 14 may be molded in a state where the heat radiation surfaces 26a and 32a of the heat sinks 26 and 32 are pressed against and adhered to the cavity wall surface of the molding die. In this case, when the sealing resin body 14 is molded, the heat radiation surfaces 26 a and 32 a are exposed from the sealing resin body 14. For this reason, the cutting after shaping
  • the semiconductor module 10 can be obtained by removing unnecessary portions of the lead frame.
  • FIG. 6 shows a result of inspecting a solder void by an ultrasonic flaw detector (SAT: Scanning Acoustic Tomograph) from the Z direction in a soldered state, that is, in a semiconductor module state.
  • FIG. 10 shows a simplified structure of the semiconductor chip 12.
  • r is added to the end of the reference numerals of the related elements in the present embodiment. 9 to 12, the flow of water vapor during reflow is indicated by arrows.
  • the inventor made a prototype of the semiconductor chip 12r having the configuration shown in FIG.
  • the first separation portion 127r extends along the X direction so as to straddle the first surface of the peripheral portion 126r, and intersects the second separation portion 128r near the center in the X direction.
  • the protective film 125r has an intersecting portion 131r formed by intersecting the first separating portion 127r and the second separating portion 128r. Other points are the same as in the present embodiment (see FIG. 2).
  • the first separation portion 127r and the second separation portion 128r provided in the peripheral portion 126r have lower wettability with respect to the solder 20r than the surface electrode 121r. Therefore, during reflow, the solder 20r does not wet and spread on the first separation portion 127r and the second separation portion 128r, and the non-wetting portion 36r is formed as shown in FIGS.
  • the non-wetting portion 36r is formed at the interface between the solder 20r, the first separation portion 127r, the second separation portion 128r, and the solder 20r.
  • the non-wetting portion 36r is a portion where the solder 20r can be pulled without getting wet. This non-wetting part 36r was confirmed by SAT.
  • the non-wetting portion 36r is confirmed in the configuration in which the surface electrode 121r is separated by the protective film 125r.
  • a void 38r may occur in the solder 20r.
  • the void 38r was generated in the solder 20r at the intersecting portion 131 and the portion directly above the periphery.
  • the void 38r is formed including the non-wetting portion 36r on the protective film 125 (the first separation portion 127r and the second separation portion 128r).
  • the void 38r is opened at least on the surface of the solder 20r on the semiconductor chip 12 side. In this test, the void 38r penetrated the solder 20r. It was also found that the void 38r is more likely to occur as the time from the end of the first reflow to the start of the second reflow is longer.
  • the surface electrode 121 in the solder 20r. It became clear that a void 38r could occur in the upper part.
  • the protective film 125r has a hygroscopic property, and moisture in the protective film 125r is vaporized during reflow.
  • the water vapor moves in the protective film 125r or in the non-wetting portion 36r that is an interface with the solder 20r.
  • a part of the water vapor moves in a direction approaching the intersection 131r.
  • water vapor collects and stays at the intersecting portion 131r or the unwetting portion 36r immediately above it from the first separation portion 127r and the second separation portion 128r (or the non-wetting portion 36r) connected to the intersecting portion 131r. .
  • the semiconductor chip 12r is warped to some extent as shown in FIG. Specifically, a concave warp occurs on the surface electrode 121r side. In FIG. 10, the back electrode 130r is omitted for convenience.
  • the rear surface electrode 130r which is the convex side is arranged upward, and the front surface electrode 121r which is the concave side is arranged downward, so that the intersecting portion is passed through the first separation portion 127r and the second separation portion 128r (or the non-wetting portion 36r)
  • Water vapor collects and stays at 131r.
  • the water vapor in the surrounding portion 126r also moves toward the intersecting portion 131r. This is the second presumed cause that the void 38r is generated around the intersection 131r.
  • the protective film 125 includes a first separation portion 127 extending in the X direction and a second separation portion 128 extending in the Y direction, whereby the surface electrode 121 is partitioned in both the X direction and the Y direction. It has been. Therefore, the warp of the semiconductor chip 12 can be reduced.
  • the protective film 125 does not have a crossing portion between the first separation portion 127 and the second separation portion 128. Therefore, even if a part of the water vapor formed by vaporization of the water in the protective film 125 during reflow moves from each of the first separation unit 127 and the second separation unit 128 toward the portion corresponding to the intersection 131r, As shown in FIG. 11, they are not collected in one place.
  • the first connecting portion 121b of the surface electrode 121 is present in the opposing region between the first separating portion 127 and the second separating portion 128, and the water vapor in the first separating portion 127 and the water vapor in the second separating portion 128 are present. Does not cross. Therefore, it can suppress that a void arises in the part on the surface electrode 121 in the solder 20.
  • the first separation portion 127 and the second separation portion 128 are not connected, and the first connection portion is interposed therebetween. Since 121b exists, the water vapor in the 1st separation part 127 and the water vapor in the 2nd separation part 128 do not cross. Also by this, it can suppress that water vapor
  • FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 2, and corresponds to FIG. 8 (comparative example). As shown in FIG. 13, even in the portion where the void 38r is generated in the comparative example, no void is generated, and the non-wetting portion 36 is merely formed on the protective film 125 (second separation portion 128 in FIG. 13).
  • the first separation unit 127 is divided into a plurality of pieces in the X direction that is the extending direction. Therefore, it is possible to suppress the generation of voids on the surface electrode 121 while effectively reducing the warpage of the semiconductor chip 12.
  • it is divided into a plurality in the longitudinal direction.
  • the first separation part 127 having a long length between both ends is divided into a plurality of parts. Therefore, it is possible to effectively suppress water vapor from being collected near the center in the longitudinal direction.
  • each of the first separation unit 127 and the second separation unit 128 is connected to the peripheral portion 126.
  • the first separation unit 127 and the second separation unit 128 are not connected and the first connection unit 121b exists between them, the water vapor (moisture) in the surrounding portion 126 passes through the first separation unit 127. It does not intersect with the water vapor in the second separation part 128. Therefore, it is possible to suppress the generation of voids even though the first separation unit 127 and the second separation unit 128 are configured to be continuous with the peripheral portion 126.
  • the Ni film 123 that is the most rigid film among the plurality of thin films is divided by the first separation part 127 and the second separation part 128 of the protective film 125.
  • that rigidity is large means that the expansion
  • the temperature of the semiconductor chip 12 becomes highest near the center of the active region, that is, near the center 121a of the surface electrode 121 by driving the element.
  • the first connecting portion 121b that is, the Ni film 123 and the Au film 124 are arranged in the opposing region of the first separation portion 127 and the second separation portion 128, and the solder 20 is connected (joined). Is done. Therefore, the heat of the semiconductor chip 12 can be effectively radiated to the terminal 22 side.
  • the first separation unit 127 may not be divided, and only the second separation unit 128 may be divided into a plurality of pieces.
  • the length of the protective film 125 disposed on the surface electrode 121 (the base film 122) is longer, the possibility that water vapor stays on the surface electrode 121 is increased. It is better to divide the separation unit 127.
  • the numbers of the first separation unit 127 and the second separation unit 128 that are connected to the same surface of the peripheral portion 126 are not limited to the above example. For example, you may have two 2nd isolation
  • the semiconductor chip 12 of this embodiment not only the first separation unit 127 but also the second separation unit 128 is divided into a plurality of parts. And the 2nd separation part 128 is divided
  • the opposing region between the first separation parts 127 and the opposing region between the second separation parts 128 are integrally connected. That is, the first separation unit 127 and the second separation unit 128 are divided at the same position.
  • the Ni film 123 and the Au film 124 that are metal thin films are arranged in the facing region, and thereby, the second connecting portion 121c to which the solder 20 is connected is formed.
  • the 2nd connection part 121c has comprised the plane substantially cross shape.
  • the surface electrode 121 has two second connecting portions 121c.
  • the second connecting portion 121c connects the portions separated in the X direction by the second separating portion 128 in the surface electrode 121 and also connects the portions separated in the Y direction by the first separating portion 127. .
  • each of the first separation unit 127 and the second separation unit 128 is divided into a plurality of parts, and thus has no intersection. As shown in FIG. 16, the water vapor in the first separator 127 and the water vapor in the second separator 128 do not intersect. Further, the water vapor in the divided first separation unit 127 does not intersect, and the water vapor in the divided second separation unit 128 does not intersect. Therefore, it is possible to effectively suppress the occurrence of voids in the portion of the solder 20 on the surface electrode 121 while reducing the warp of the semiconductor chip 12.
  • the water vapor (moisture) in the surrounding portion 126 does not intersect with the water vapor in the other divided first separation portion 127 and second separation portion 128 through the first separation portion 127.
  • the water vapor in the peripheral portion 126 does not intersect with the water vapor in the other divided second separation portion 128 or the first separation portion 127 through the second separation portion 128. Also by this, it can suppress that a void arises.
  • the second connecting portion 121c has a substantially cross shape in a plane, and has a larger area along the XY plane than the first connecting portion 121b. For this reason, the 2nd connection part 121c has a larger connection area with the solder 20 than the 1st connection part 121b. Since the second connecting portion 121c is provided in the vicinity of the center 121a that is at a high temperature, the heat of the semiconductor chip 12 can be radiated more effectively.
  • the number of divisions is not limited to the above example. Further, the numbers of the first separation unit 127 and the second separation unit 128 connected to the same surface of the peripheral portion 126 are not limited to the above example.
  • the protective film 125 has an intersecting portion 131 where the first separating portion 127 and the second separating portion 128 intersect.
  • the protective film 125 has one second separator 128 and two first separators 127.
  • the two first separators 127 have the same length, and the surface electrode 121 is divided into three equal parts in the Y direction by the first separators 127.
  • the second separator 128 is provided at the center in the X direction, and the surface electrode 121 is divided into two equal parts in the X direction by the second separator 128.
  • the protective film 125 has two intersecting portions 131.
  • the first separation portion 127 is provided away from the peripheral portion 126 so as not to be connected to the peripheral portion 126.
  • a Ni film 123 and an Au film 124 which are metal thin films, are arranged in regions facing both ends of the first separation part 127 and the inner peripheral surface of the peripheral part 126, whereby the outer peripheral connection to which the solder 20 is connected.
  • a portion 121d is formed.
  • the second separation portion 128 is provided away from the peripheral portion 126 so as not to be continuous with the peripheral portion 126.
  • a Ni film 123 and an Au film 124, which are metal thin films, are arranged in regions opposite to both ends of the second separation part 128 and the inner peripheral surface of the peripheral part 126, whereby the outer peripheral connection to which the solder 20 is connected.
  • a portion 121e is formed.
  • the surface electrode 121 has six outer peripheral connection parts 121d and 121e.
  • the outer periphery connecting portion 121 d connects the portions separated in the Y direction by the first separation portion 127 in the surface electrode 121 in the vicinity of the outer peripheral end of the surface electrode 121.
  • the outer periphery connecting portion 121 e connects the portions separated in the X direction by the second separation portion 128 in the surface electrode 121 in the vicinity of the outer peripheral end of the surface electrode 121.
  • the protective film 125 has an intersection 131.
  • the first separation portion 127 and the second separation portion 128 are separated from the peripheral portion 126.
  • the water vapor (moisture) in the peripheral portion 126 does not intersect with the water vapor in the first separation portion 127 or the second separation portion 128. That is, the surrounding water vapor does not reach the intersection 131.
  • the water vapor collected at the intersection 131 can be reduced.
  • the length of the 1st separation part 127 and the 2nd separation part 128 is shortened for the outer periphery connection parts 121d and 121e, and thereby, water vapor collected at the intersection part 131 can be reduced.
  • voids are formed on the portion of the solder 20 on the surface electrode 121 while reducing the warp of the semiconductor chip 12 by the protective film 125. It can be suppressed from occurring.
  • the first separation unit 127 and the second separation unit 128 are provided apart from the peripheral portion 126, and the first separation unit 127 and the second separation unit 128 are disposed between the peripheral portion 126.
  • the number of the 1st separation part 127 and the 2nd separation part 128 is not limited to the said example.
  • a configuration having one first separation unit 127 and two second separation units 128 may be employed.
  • the semiconductor chip 12 shown in FIG. 19 is configured by combining the second embodiment and the third embodiment.
  • the first separation unit 127 and the second separation unit 128 do not have an intersecting portion and are provided so as not to be connected to the peripheral portion 126.
  • the surface electrode 121 has the 2nd connection part 121c and the outer periphery connection parts 121d and 121e.
  • first separation unit 127 In the first embodiment and the second embodiment, an example in which there is no intersection between the first separation unit 127 and the second separation unit 128 is shown.
  • the closer to the center 121a the easier it is for water vapor to collect from the surroundings. Therefore, it may be configured such that only the vicinity of the center 121a does not intersect and intersects at a position away from the center 121a.
  • first connecting portion 121b is formed by disposing the Ni film 123 and the Au film 124, which are metal thin films, in the facing region between the first separation portion 127 and the second separation portion 128.
  • second connecting portion 121c is formed in the facing region between the first separation portions 127 and the facing region between the second separation portions 128 has been shown.
  • region of the 1st separation part 127, the 2nd separation part 128, and the surrounding part 126 was shown.
  • a configuration in which the metal thin film is not disposed in the facing region and the base film 122 is exposed may be employed.
  • a 1 in 1 package including one semiconductor chip 12 is shown as the semiconductor module 10, it is not limited to this.
  • the present invention can also be applied to a 2-in-1 package that includes two semiconductor chips 12 and constitutes an upper and lower arm for one phase, and a 6-in1 package that includes six semiconductor chips 12 and constitutes an upper- and lower-arm for three phases.
  • the present invention can also be applied to a configuration that does not include the sealing resin body 14.
  • the present invention can be applied to a configuration in which the heat sinks 26 and 32 are not exposed from the sealing resin body 14.
  • the present invention is not limited to this.
  • a configuration in which the terminal 22 is not provided and the heat sink 26 is connected to the surface electrode 121 of the semiconductor chip 12 via solder may be employed.

Abstract

Provided is a semiconductor device that comprises: a semiconductor substrate (120) that has a front surface (120a) and a rear surface (120b) opposing the front surface in a plate thickness direction, and that includes an element formed thereon; a front surface electrode (121) soldered onto the front surface of the semiconductor substrate; a protective film (125) formed using a hygroscopic material; and a rear surface electrode (130) provided on the rear surface of the semiconductor substrate. The protective film includes: a peripheral section (126) provided so as to surround the front surface electrode on the front surface of the semiconductor substrate; a first separation section (127) extending in the row direction orthogonal to the plate thickness direction in a region surrounded by the peripheral section and dividing the front surface electrode in the column direction orthogonal to the plate thickness direction and row direction; and a second separation section (128) extending in the column direction in the region and dividing the front surface electrode in the row direction. The first separation section and the second separation section are provided in a separated manner from each other so as to avoid intersection.

Description

半導体装置Semiconductor device 関連出願の相互参照Cross-reference of related applications
　本出願は、２０１７年４月６日に出願された日本出願番号２０１７－７６０８６号に基づくもので、ここにその記載内容を援用する。 This application is based on Japanese Application No. 2017-76086 filed on Apr. 6, 2017, the contents of which are incorporated herein by reference.
　本開示は、半導体基板の表面に形成された表面電極と、裏面に形成された裏面電極を有する半導体装置に関する。 The present disclosure relates to a semiconductor device having a surface electrode formed on the surface of a semiconductor substrate and a back electrode formed on the back surface.
　従来、半導体基板の表面に形成された表面電極と、裏面に形成された裏面電極を有する半導体装置が知られている。このような半導体装置では、近年、低損失化のために、半導体基板の厚みが薄くなってきている。また、表面電極と裏面電極とで、膜厚などの構成が異なる。このように、薄板化や表裏でのバイメタル効果の違いから、半導体装置に反りが生じることがある。 Conventionally, a semiconductor device having a surface electrode formed on the surface of a semiconductor substrate and a back electrode formed on the back surface is known. In such a semiconductor device, in recent years, the thickness of the semiconductor substrate has been reduced in order to reduce the loss. In addition, the structure such as the film thickness is different between the front electrode and the back electrode. As described above, the semiconductor device may be warped due to the thin plate and the difference in the bimetal effect between the front and back sides.
　特許文献１に開示された半導体装置では、反りを低減するために、はんだ付けされる表面電極が、保護膜により、板厚方向に直交する行方向及び列方向の両方向において複数に分割されている。 In the semiconductor device disclosed in Patent Document 1, the surface electrode to be soldered is divided into a plurality of parts in both the row direction and the column direction perpendicular to the plate thickness direction by a protective film in order to reduce warpage. .
特開２０１４－２４１３３４号公報JP 2014-241334 A
　保護膜は、ポリイミドなどの吸湿性材料を用いて形成されている。本発明者が鋭意検討したところ、はんだのリフロー時に保護膜中の水分が気化（水蒸気化）して、保護膜における行方向に延設された部分と列方向に延設された部分との交差部に滞留し、これにより表面電極上においてはんだにボイドが生じることが明らかとなった。 The protective film is formed using a hygroscopic material such as polyimide. As a result of intensive studies by the present inventor, when the solder reflows, the moisture in the protective film evaporates (vaporizes), and the portion of the protective film that extends in the row direction and the portion of the protective film that extends in the column direction intersect. It has become clear that voids are generated in the solder on the surface electrode.
　本開示は、反りを低減しつつ、表面電極上のはんだにボイドが生じるのを効果的に抑制できる半導体装置を提供することを目的とする。 This disclosure is intended to provide a semiconductor device that can effectively suppress the generation of voids in solder on a surface electrode while reducing warpage.
　本開示の第一の態様によれば、半導体装置は、表面及び該表面と板厚方向に反対の裏面を有し、素子が形成された半導体基板と、表面上に設けられ、はんだ付けされる表面電極と、表面上において表面電極を取り囲むように設けられた周囲部と、周囲部により囲まれる領域内において板厚方向に直交する行方向に延設され、板厚方向及び行方向に直交する列方向において表面電極を区切る第１分離部と、領域内において列方向に延設され、行方向において表面電極を区切る第２分離部と、を有し、吸湿性材料を用いて形成された保護膜と、裏面に設けられた裏面電極と、を備える。第１分離部及び第２分離部が、交差しないように互いに離れて設けられている。 According to the first aspect of the present disclosure, a semiconductor device includes a semiconductor substrate having a front surface and a back surface opposite to the front surface in the plate thickness direction, on which elements are formed, and provided on the front surface and soldered. A surface electrode, a peripheral portion provided on the surface so as to surround the surface electrode, and a region extending in a row direction orthogonal to the plate thickness direction in a region surrounded by the peripheral portion, and orthogonal to the plate thickness direction and the row direction A protection formed using a hygroscopic material, having a first separation part that divides the surface electrode in the column direction and a second separation part that extends in the column direction in the region and divides the surface electrode in the row direction A film, and a back electrode provided on the back surface. The first separation part and the second separation part are provided apart from each other so as not to cross each other.
　この半導体装置によれば、保護膜が、行方向に延びる第１分離部と列方向に延びる第２分離部を有しており、これにより表面電極が区切られているため、半導体装置の反りを低減することができる。 According to this semiconductor device, since the protective film has the first separation portion extending in the row direction and the second separation portion extending in the column direction, and the surface electrode is thereby separated, the warp of the semiconductor device is reduced. Can be reduced.
　また、保護膜に、第１分離部と第２分離部との交差部がないため、保護膜の吸湿により生じた水蒸気の滞留を抑制し、ひいては表面電極上のはんだにボイドが生じるのを抑制することができる。 In addition, since the protective film does not have an intersection between the first separation part and the second separation part, the retention of water vapor generated by moisture absorption of the protective film is suppressed, and consequently, the generation of voids in the solder on the surface electrode is suppressed. can do.
　本開示の第二の態様によれば、半導体装置は、表面及び該表面と板厚方向に反対の裏面を有し、素子が形成された半導体基板と、表面上に設けられ、はんだ付けされる表面電極と、表面上において表面電極の周囲に設けられた周囲部と、周囲部により囲まれる領域内において板厚方向に直交する行方向に延設され、板厚方向及び行方向に直交する列方向において表面電極を区切る第１分離部と、領域内において列方向に延設され、行方向において表面電極を区切る第２分離部と、第１分離部と第２分離部との交差部分である交差部と、を有し、吸湿性材料を用いて形成された保護膜と、裏面に設けられた裏面電極と、を備える。第１分離部及び第２分離部が、周囲部に連ならないように周囲部に対して離れて設けられている。 According to the second aspect of the present disclosure, a semiconductor device has a front surface and a back surface opposite to the front surface in the thickness direction, and is provided with a semiconductor substrate on which elements are formed, and is soldered. A surface electrode, a peripheral portion provided around the surface electrode on the surface, and a column extending in a row direction orthogonal to the plate thickness direction in a region surrounded by the peripheral portion and orthogonal to the plate thickness direction and the row direction A first separation portion that divides the surface electrode in the direction, a second separation portion that extends in the column direction in the region and divides the surface electrode in the row direction, and an intersection of the first separation portion and the second separation portion A protective film formed using a hygroscopic material, and a back electrode provided on the back surface. The first separation part and the second separation part are provided apart from the peripheral part so as not to be connected to the peripheral part.
　この半導体装置によれば、保護膜が、行方向に延びる第１分離部と列方向に延びる第２分離部を有しており、これにより表面電極が区切られているため、半導体装置の反りを低減することができる。 According to this semiconductor device, since the protective film has the first separation portion extending in the row direction and the second separation portion extending in the column direction, and the surface electrode is thereby separated, the warp of the semiconductor device is reduced. Can be reduced.
　また、保護膜が交差部を有するものの、第１分離部及び第２分離部が周囲部に対して離れて設けられている。これにより、周囲部の水分（水蒸気）が、第１分離部又は第２分離部を通じて交差部に集まるのを抑制することができる。また、第１分離部及び第２分離部が周囲部に連なる構成に較べて、交差部に連なる保護膜の長さが短い。したがって、水蒸気が交差部に滞留するのを抑制し、ひいては表面電極上のはんだにボイドが生じるのを抑制することができる。 In addition, although the protective film has a crossing portion, the first separation portion and the second separation portion are provided apart from the surrounding portion. Thereby, it can suppress that the water | moisture content (water vapor | steam) of a surrounding part collects in an intersection part through a 1st separation part or a 2nd separation part. Further, the length of the protective film connected to the intersecting portion is shorter than the configuration in which the first separating portion and the second separating portion are connected to the peripheral portion. Therefore, it is possible to suppress the water vapor from staying at the intersecting portion and to suppress the generation of voids in the solder on the surface electrode.
　本開示についての上記目的およびその他の目的、特徴や利点は、添付の図面を参照しながら下記の詳細な記述により、より明確になる。
第１実施形態に係る半導体チップが適用された半導体パッケージの概略構成を示す断面図である。 半導体チップの概略構成を示す平面図である。 図２のIII-III線に沿う断面図である。 図２のIV-IV線に沿う断面図である。 比較例を示す平面図である。 比較例において、はんだに生じるボイドを示す平面図である。 比較例において、図６のVII-VII線に沿う断面図である。 比較例において、図６のVIII-VIII線に沿う断面図である。 比較例においてボイド発生を説明するための平面図である。 比較例においてボイド発生を説明するための図５のＸ-Ｘ線に沿う断面図である。 ボイド抑制を説明するための平面図であり、図９に対応している。 ボイド抑制を説明するための断面図であり、図１０に対応している。 図２のXIII-XIII線に対応する断面図である。 第２実施形態に係る半導体チップの概略構成を示す平面図である。 図１４のXV-XV線に沿う断面図である。 ボイド抑制を説明するための平面図であり、図９に対応している。 第３実施形態に係る半導体チップの概略構成を示す平面図である。 ボイド抑制を説明するための断面図であり、図１０に対応している。 変形例を示す平面図である。 The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings.
It is sectional drawing which shows schematic structure of the semiconductor package to which the semiconductor chip concerning 1st Embodiment was applied. It is a top view which shows schematic structure of a semiconductor chip. It is sectional drawing which follows the III-III line of FIG. It is sectional drawing which follows the IV-IV line of FIG. It is a top view which shows a comparative example. In a comparative example, it is a top view which shows the void which arises in solder. In a comparative example, it is sectional drawing which follows the VII-VII line of FIG. In a comparative example, it is sectional drawing which follows the VIII-VIII line of FIG. It is a top view for demonstrating void generation in a comparative example. It is sectional drawing which follows the XX line of FIG. 5 for demonstrating void generation | occurrence | production in a comparative example. It is a top view for demonstrating void suppression, and respond | corresponds to FIG. It is sectional drawing for demonstrating void suppression, and respond | corresponds to FIG. It is sectional drawing corresponding to the XIII-XIII line | wire of FIG. It is a top view which shows schematic structure of the semiconductor chip which concerns on 2nd Embodiment. It is sectional drawing which follows the XV-XV line | wire of FIG. It is a top view for demonstrating void suppression, and respond | corresponds to FIG. It is a top view which shows schematic structure of the semiconductor chip which concerns on 3rd Embodiment. It is sectional drawing for demonstrating void suppression, and respond | corresponds to FIG. It is a top view which shows a modification.
　図面を参照しながら、複数の実施形態を説明する。複数の実施形態において、機能的に及び／又は構造的に対応する部分には同一の参照符号を付与する。以下において、半導体基板の板厚方向をＺ方向と示す。Ｚ方向に直交し、且つ、第１分離部の延設方向をＸ方向と示す。Ｚ方向及びＸ方向の両方向に直交する方向、すなわち第２分離部の延設方向をＹ方向と示す。特に断りのない限り、ＸＹ平面に沿う形状を平面形状とする。 A plurality of embodiments will be described with reference to the drawings. In several embodiments, functionally and / or structurally corresponding parts are given the same reference numerals. In the following, the thickness direction of the semiconductor substrate is referred to as the Z direction. A direction perpendicular to the Z direction and the extending direction of the first separation portion is indicated as an X direction. The direction orthogonal to both the Z direction and the X direction, that is, the extending direction of the second separation portion is indicated as the Y direction. Unless otherwise specified, the shape along the XY plane is a planar shape.
　（第１実施形態）
　先ず、図１に基づき、本実施形態に係る半導体チップが適用された半導体モジュールについて説明する。 (First embodiment)
First, a semiconductor module to which the semiconductor chip according to the present embodiment is applied will be described with reference to FIG.
　図１に示すように、半導体モジュール１０は、半導体チップ１２、封止樹脂体１４、信号端子１８、ターミナル２２、ヒートシンク２６、主端子２８、ヒートシンク３２、及び主端子３４を備えている。このような半導体モジュール１０は、たとえばハイブリッド車や電気自動車の主機インバータに用いられる。 As shown in FIG. 1, the semiconductor module 10 includes a semiconductor chip 12, a sealing resin body 14, a signal terminal 18, a terminal 22, a heat sink 26, a main terminal 28, a heat sink 32, and a main terminal 34. Such a semiconductor module 10 is used for a main inverter of a hybrid vehicle or an electric vehicle, for example.
　半導体モジュール１０は、半導体チップ１２をひとつ備えている。半導体モジュール１０は、三相インバータを構成する６つのアームのうちのひとつを構成する。このような半導体モジュール１０は、パッケージ内にひとつのアームを備えるため、１ｉｎ１パッケージとも称される。 The semiconductor module 10 includes one semiconductor chip 12. The semiconductor module 10 constitutes one of six arms constituting a three-phase inverter. Since such a semiconductor module 10 includes one arm in the package, it is also referred to as a 1 in 1 package.
　半導体チップ１２には、板厚方向であるＺ方向に電流が流れる素子、所謂縦型素子が形成されている。半導体チップ１２が、半導体装置に相当する。縦型素子としては、ＭＯＳＦＥＴ、ＩＧＢＴなどを採用することができる。半導体チップ１２は、Ｚ方向における両面に電極を有している。また、一方の面に、信号端子１８用のパッドを有している。 The semiconductor chip 12 is formed with an element in which a current flows in the Z direction which is the thickness direction, a so-called vertical element. The semiconductor chip 12 corresponds to a semiconductor device. MOSFET, IGBT, etc. are employable as a vertical element. The semiconductor chip 12 has electrodes on both sides in the Z direction. In addition, a pad for the signal terminal 18 is provided on one surface.
　封止樹脂体１４は、たとえばエポキシ系樹脂からなる。封止樹脂体１４は、トランスファ成形により形成されている。封止樹脂体１４は、平面略矩形状をなしている。封止樹脂体１４は、Ｚ方向に直交する一面１４ａ、一面１４ａと反対の裏面１４ｂ、及び側面を有している。一面１４ａ及び裏面１４ｂは、たとえば平坦面となっている。封止樹脂体１４は、半導体チップ１２を封止している。 The sealing resin body 14 is made of, for example, an epoxy resin. The sealing resin body 14 is formed by transfer molding. The sealing resin body 14 has a substantially rectangular planar shape. The sealing resin body 14 has one surface 14a orthogonal to the Z direction, a back surface 14b opposite to the one surface 14a, and side surfaces. The one surface 14a and the back surface 14b are flat surfaces, for example. The sealing resin body 14 seals the semiconductor chip 12.
　半導体チップ１２のパッド（後述するパッド１２９）には、ボンディングワイヤ１６を介して、信号端子１８が接続されている。信号端子１８は、Ｙ方向に延設されており、封止樹脂体１４の一の側面１４ｃから外部に突出している。これにより、信号端子１８は、外部機器との電気的な接続が可能となっている。信号端子１８は、リードフレームの一部として、ヒートシンク３２と一体的に形成されてもよいし、別部材の信号端子１８がヒートシンク３２に接続されてもよい。 A signal terminal 18 is connected to a pad (a pad 129 described later) of the semiconductor chip 12 through a bonding wire 16. The signal terminal 18 extends in the Y direction, and protrudes to the outside from one side surface 14 c of the sealing resin body 14. Thereby, the signal terminal 18 can be electrically connected to an external device. The signal terminal 18 may be formed integrally with the heat sink 32 as a part of the lead frame, or the signal terminal 18 of another member may be connected to the heat sink 32.
　半導体チップ１２の一方の電極（後述する表面電極１２１）には、はんだ２０を介してターミナル２２が接続されている。ターミナル２２は、半導体チップ１２とヒートシンク２６との間に介在している。ターミナル２２は、半導体チップ１２の生じた熱をヒートシンク２６に伝達する。ターミナル２２は、半導体チップ１２とヒートシンク２６とを電気的に中継する。このため、ターミナル２２は、熱伝導性及び電気伝導性を確保すべく、金属材料（たとえばＣｕ）を用いて形成されている。ターミナル２２は、略直方体状をなしている。 A terminal 22 is connected to one electrode (surface electrode 121 described later) of the semiconductor chip 12 via a solder 20. The terminal 22 is interposed between the semiconductor chip 12 and the heat sink 26. The terminal 22 transfers heat generated by the semiconductor chip 12 to the heat sink 26. The terminal 22 electrically relays the semiconductor chip 12 and the heat sink 26. For this reason, the terminal 22 is formed using a metal material (for example, Cu) in order to ensure thermal conductivity and electrical conductivity. The terminal 22 has a substantially rectangular parallelepiped shape.
　ターミナル２２における半導体チップ１２と反対側の面には、はんだ２４を介してヒートシンク２６が接続されている。ヒートシンク２６は、半導体チップ１２の生じた熱を、半導体モジュール１０の外部に放熱する。ヒートシンク２６は、半導体チップ１２と主端子２８とを電気的に中継する。ヒートシンク２６は、ターミナル２２同様、熱伝導性及び電気伝導性に優れる金属材料（たとえばＣｕ）を用いて形成されている。 A heat sink 26 is connected to the surface of the terminal 22 opposite to the semiconductor chip 12 via a solder 24. The heat sink 26 radiates heat generated by the semiconductor chip 12 to the outside of the semiconductor module 10. The heat sink 26 electrically relays the semiconductor chip 12 and the main terminal 28. Like the terminal 22, the heat sink 26 is formed using a metal material (for example, Cu) having excellent thermal conductivity and electrical conductivity.
　ヒートシンク２６におけるターミナル２２と反対の面は、封止樹脂体１４の一面１４ａから露出された放熱面２６ａとなっている。本実施形態では、一面１４ａ及び放熱面２６ａが略面一となっている。ヒートシンク２６において、ターミナル２２との対向面、及び、該対向面と放熱面２６ａをつなぐ側面は、封止樹脂体１４によって被覆されている。 The surface of the heat sink 26 opposite to the terminal 22 is a heat radiating surface 26 a exposed from the one surface 14 a of the sealing resin body 14. In the present embodiment, the one surface 14a and the heat radiation surface 26a are substantially flush. In the heat sink 26, the surface facing the terminal 22 and the side surface connecting the facing surface and the heat radiating surface 26 a are covered with the sealing resin body 14.
　ヒートシンク２６には、主端子２８が連なっている。この主端子２８は、ターミナル２２及びヒートシンク２６を介して、半導体チップ１２と電気的に接続されている。主端子２８は、ヒートシンク２６から、Ｙ方向であって信号端子１８とは反対側に延設されている。主端子２８は、信号端子１８が突出する側面１４ｃと反対の側面１４ｄから外部に突出している。これにより、主端子２８は、外部機器との電気的な接続が可能となっている。主端子２８は、リードフレームの一部として、ヒートシンク２６と一体的に形成されてもよいし、別部材の主端子２８がヒートシンク２６に接続されてもよい。 A main terminal 28 is connected to the heat sink 26. The main terminal 28 is electrically connected to the semiconductor chip 12 via the terminal 22 and the heat sink 26. The main terminal 28 extends from the heat sink 26 in the Y direction and on the side opposite to the signal terminal 18. The main terminal 28 projects outward from a side surface 14d opposite to the side surface 14c from which the signal terminal 18 projects. Thereby, the main terminal 28 can be electrically connected to an external device. The main terminal 28 may be formed integrally with the heat sink 26 as a part of the lead frame, or a separate main terminal 28 may be connected to the heat sink 26.
　半導体チップ１２の他方の電極（後述する裏面電極１３０）には、はんだ３０を介してヒートシンク３２が接続されている。ヒートシンク３２は、ヒートシンク２６同様、半導体チップ１２の生じた熱を、半導体モジュール１０の外部に放熱する。ヒートシンク３２は、半導体チップ１２と主端子３４とを電気的に中継する。ヒートシンク３２も、熱伝導性及び電気伝導性に優れる金属材料（たとえばＣｕ）を用いて形成されている。 A heat sink 32 is connected to the other electrode of the semiconductor chip 12 (a back electrode 130 described later) via a solder 30. Like the heat sink 26, the heat sink 32 radiates the heat generated by the semiconductor chip 12 to the outside of the semiconductor module 10. The heat sink 32 electrically relays the semiconductor chip 12 and the main terminal 34. The heat sink 32 is also formed using a metal material (for example, Cu) excellent in thermal conductivity and electrical conductivity.
　ヒートシンク３２における半導体チップ１２と反対の面は、封止樹脂体１４の裏面１４ｂから露出された放熱面３２ａとなっている。本実施形態では、裏面１４ｂ及び放熱面３２ａが略面一となっている。ヒートシンク３２において、半導体チップ１２との対向面、及び、該対向面と放熱面３２ａをつなぐ側面は、封止樹脂体１４によって被覆されている。 A surface of the heat sink 32 opposite to the semiconductor chip 12 is a heat radiating surface 32 a exposed from the back surface 14 b of the sealing resin body 14. In the present embodiment, the back surface 14b and the heat dissipation surface 32a are substantially flush. In the heat sink 32, the surface facing the semiconductor chip 12 and the side surface connecting the facing surface and the heat radiating surface 32 a are covered with the sealing resin body 14.
　ヒートシンク３２には、主端子３４が連なっている。この主端子３４は、ヒートシンク３２を介して、半導体チップ１２と電気的に接続されている。主端子３４は、ヒートシンク３２から、Ｙ方向であって主端子２８と同じ側に延設されている。主端子３４は、主端子２８と同じ側面１４ｄから外部に突出している。これにより、主端子３４は、外部機器との電気的な接続が可能となっている。主端子３４は、リードフレームの一部として、ヒートシンク３２と一体的に形成されてもよいし、別部材の主端子３４がヒートシンク３２に接続されてもよい。Ｚ方向からの平面視において、主端子２８，３４は、Ｘ方向に並んで配置されている。 The main terminal 34 is connected to the heat sink 32. The main terminal 34 is electrically connected to the semiconductor chip 12 via the heat sink 32. The main terminal 34 extends from the heat sink 32 in the Y direction and on the same side as the main terminal 28. The main terminal 34 protrudes from the same side surface 14 d as the main terminal 28. Thereby, the main terminal 34 can be electrically connected to an external device. The main terminal 34 may be formed integrally with the heat sink 32 as a part of the lead frame, or a separate main terminal 34 may be connected to the heat sink 32. In a plan view from the Z direction, the main terminals 28 and 34 are arranged side by side in the X direction.
　このように構成される半導体モジュール１０では、半導体チップ１２、ボンディングワイヤ１６、信号端子１８の一部、はんだ２０，２４，３０、ターミナル２２、ヒートシンク２６の一部、主端子２８の一部、ヒートシンク３２の一部、及び主端子３４の一部が、封止樹脂体１４にて封止されている。そして、Ｚ方向において、半導体チップ１２の両側にヒートシンク２６，３２が配置され、放熱面２６ａ，３２ａにより外部に放熱可能とされている。 In the semiconductor module 10 configured as described above, the semiconductor chip 12, the bonding wire 16, a part of the signal terminal 18, the solder 20, 24, 30, the terminal 22, the part of the heat sink 26, the part of the main terminal 28, the heat sink. A part of 32 and a part of the main terminal 34 are sealed with the sealing resin body 14. In the Z direction, heat sinks 26 and 32 are disposed on both sides of the semiconductor chip 12, and heat can be radiated to the outside by the heat radiating surfaces 26a and 32a.
　次に、図２～図４に基づき、半導体チップ１２（半導体装置）について説明する。 Next, the semiconductor chip 12 (semiconductor device) will be described with reference to FIGS.
　図２、図３、及び図４に示すように、半導体チップ１２は、半導体基板１２０、表面電極１２１、保護膜１２５、パッド１２９、及び裏面電極１３０を備えている。表面電極１２１及び裏面電極１３０が、上記した両面の電極に相当する。 2, 3, and 4, the semiconductor chip 12 includes a semiconductor substrate 120, a surface electrode 121, a protective film 125, a pad 129, and a back electrode 130. The front electrode 121 and the back electrode 130 correspond to the above-described double-sided electrodes.
　半導体基板１２０は、Ｓｉ（シリコン）やＳｉＣ（シリコンカーバイド）など、周知の半導体材料からなる。半導体基板１２０には、上記した縦型素子が形成されている。本実施形態では、Ｓｉを構成材料とする半導体基板１２０に、ｎチャネル型のＩＧＢＴと、ＩＧＢＴに逆並列に接続されたＦＷＤ（転流ダイオード）が形成されている。すなわち、半導体基板１２０に、ＲＣ－ＩＧＢＴが形成されている。なお、ＩＧＢＴとＦＷＤを互いに異なる半導体基板に形成することもできる。 The semiconductor substrate 120 is made of a known semiconductor material such as Si (silicon) or SiC (silicon carbide). The above-described vertical element is formed on the semiconductor substrate 120. In this embodiment, an n-channel IGBT and an FWD (commutation diode) connected in reverse parallel to the IGBT are formed on a semiconductor substrate 120 made of Si. That is, RC-IGBT is formed on the semiconductor substrate 120. Note that the IGBT and the FWD can be formed on different semiconductor substrates.
　半導体基板１２０は、平面略矩形状をなしている。半導体基板１２０は、Ｚ方向において、表面１２０ａ及び表面１２０ａと反対の裏面１２０ｂを有している。表面１２０ａ側の表層において、アクティブ領域（メイン領域）には、ＩＧＢＴのエミッタ領域、トレンチゲート、ＦＷＤのアノード領域などが形成されている。アクティブ領域は、平面略矩形状をなしている。アクティブ領域を取り囲む外周領域には、ガードリングなどの耐圧構造部が形成されている。一方、裏面１２０ｂ側の表層には、ＩＧＢＴのコレクタ領域及びＦＷＤのカソード領域が形成されている。 The semiconductor substrate 120 has a substantially rectangular planar shape. The semiconductor substrate 120 has a front surface 120a and a back surface 120b opposite to the front surface 120a in the Z direction. In the surface layer on the surface 120a side, an IGBT emitter region, a trench gate, an FWD anode region, and the like are formed in the active region (main region). The active area has a substantially rectangular shape in plan view. A breakdown voltage structure such as a guard ring is formed in the outer peripheral region surrounding the active region. On the other hand, an IGBT collector region and an FWD cathode region are formed on the surface layer on the back surface 120b side.
　半導体基板１２０の表面１２０ａには、表面電極１２１、保護膜１２５、及びパッド１２９が形成されている。表面電極１２１は、アクティブ領域に対応して形成されている。表面電極１２１は、エミッタ領域及びアノード領域と電気的に接続された電極である。このため、表面電極１２１は、エミッタ電極とも称される。表面電極１２１は、エミッタ電極として機能するだけでなく、ＦＷＤのアノード電極としても機能する。表面電極１２１は、裏面電極１３０との間に電流が流れるため、主電極とも称される。表面電極１２１は、平面略矩形状の半導体基板１２０において、Ｙ方向における一端側に形成されている。 A surface electrode 121, a protective film 125, and a pad 129 are formed on the surface 120 a of the semiconductor substrate 120. The surface electrode 121 is formed corresponding to the active region. The surface electrode 121 is an electrode that is electrically connected to the emitter region and the anode region. For this reason, the surface electrode 121 is also referred to as an emitter electrode. The surface electrode 121 not only functions as an emitter electrode but also functions as an anode electrode of the FWD. The front electrode 121 is also referred to as a main electrode because a current flows between the front electrode 121 and the back electrode 130. The surface electrode 121 is formed on one end side in the Y direction in the semiconductor substrate 120 having a substantially rectangular plane.
　表面電極１２１は、下地膜１２２及び金属薄膜を有している。下地膜１２２は、Ａｌ（アルミニウム）を主成分とする材料を用いて形成されている。本実施形態では、下地膜１２２が、ＡｌＳｉを材料とし、スパッタにより形成されている。下地膜１２２の厚みは、たとえば５μｍとなっている。 The surface electrode 121 has a base film 122 and a metal thin film. The base film 122 is formed using a material whose main component is Al (aluminum). In the present embodiment, the base film 122 is formed by sputtering using AlSi as a material. The thickness of the base film 122 is 5 μm, for example.
　下地膜１２２上には、はんだ２０との接合強度向上、はんだ２０に対する濡れ性向上などを目的として、金属薄膜が形成されている。本実施形態では、金属薄膜として、Ｎｉ膜１２３及びＡｕ膜１２４を有している。Ｎｉ膜１２３は、Ｎｉ（ニッケル）を主成分とする材料を用いて形成されている。Ｎｉを用いると、たとえば、はんだ２０との接合強度を向上することができる。 A metal thin film is formed on the base film 122 for the purpose of improving the bonding strength with the solder 20 and improving the wettability with respect to the solder 20. In the present embodiment, a Ni film 123 and an Au film 124 are provided as metal thin films. The Ni film 123 is formed using a material mainly composed of Ni (nickel). When Ni is used, for example, the bonding strength with the solder 20 can be improved.
　本実施形態では、Ｎｉ膜１２３がめっき膜とされている。詳しくは、主成分であるＮｉに加えて、Ｐ（リン）を含む無電解Ｎｉめっき膜とされている。Ｎｉ膜１２３の厚みは、たとえば５μｍとなっている。 In this embodiment, the Ni film 123 is a plating film. Specifically, the electroless Ni plating film contains P (phosphorus) in addition to Ni as the main component. The thickness of the Ni film 123 is, for example, 5 μm.
　Ａｕ膜１２４は、Ａｕ（金）を主成分とする材料を用いて形成されている。Ａｕを用いると、たとえば、はんだ２０との濡れ性を向上することができる。本実施形態では、Ａｕ膜１２４がめっき膜とされている。Ａｕ膜１２４の厚みは、たとえば１μｍ未満（ｎｍオーダ）とされている。このように、表面電極１２１は、多層膜構造をなしている。 The Au film 124 is formed using a material whose main component is Au (gold). When Au is used, for example, wettability with the solder 20 can be improved. In the present embodiment, the Au film 124 is a plating film. The thickness of the Au film 124 is, for example, less than 1 μm (nm order). Thus, the surface electrode 121 has a multilayer film structure.
　保護膜１２５は、ポリイミドなどの吸湿性を有する材料を用いて形成されている。保護膜１２５は、周囲部１２６、第１分離部１２７、及び第２分離部１２８を有している。周囲部１２６は、表面１２０ａ上において、表面電極１２１を取り囲むように設けられている。周囲部１２６は、アクティブ領域を取り囲むように、外周領域上に設けられている。周囲部１２６は矩形環状をなしている。保護膜１２５において下地膜１２２の無い部分の厚み、たとえば周囲部１２６の厚みは、表面電極１２１における下地膜１２２、Ｎｉ膜１２３、及びＡｕ膜１２４の積層部分の厚みとほぼ等しくされている。 The protective film 125 is formed using a hygroscopic material such as polyimide. The protective film 125 includes a peripheral portion 126, a first separation portion 127, and a second separation portion 128. The peripheral portion 126 is provided on the surface 120a so as to surround the surface electrode 121. The peripheral portion 126 is provided on the outer peripheral region so as to surround the active region. The peripheral portion 126 has a rectangular ring shape. In the protective film 125, the thickness of the portion without the base film 122, for example, the thickness of the peripheral portion 126, is substantially equal to the thickness of the laminated portion of the base film 122, the Ni film 123, and the Au film 124 in the surface electrode 121.
　第１分離部１２７及び第２分離部１２８は、周囲部１２６により囲まれる領域、すなわちアクティブ領域内に設けられている。第１分離部１２７は、Ｚ方向に直交する第１方向であるＸ方向に沿って延設されている。Ｘ方向が行方向に相当する。保護膜１２５は、複数の第１分離部１２７を有している。 The first separation unit 127 and the second separation unit 128 are provided in a region surrounded by the peripheral portion 126, that is, in an active region. The first separation unit 127 extends along the X direction, which is a first direction orthogonal to the Z direction. The X direction corresponds to the row direction. The protective film 125 has a plurality of first separators 127.
　周囲部１２６の内周面は、平面略矩形状をなしている。周囲部１２６は、内周面として、Ｘ方向に直交する一組の面（以下、第１面と示す）と、Ｙ方向に直交する一組の面（以下、第２面と示す）を有している。第１面間の長さ（対向距離）は、第２面間の長さ（対向距離）よりも長くされている。すなわち、内周面は、Ｘ方向を長手方向、Ｙ方向を短手方向としている。 The inner peripheral surface of the peripheral portion 126 has a substantially rectangular planar shape. The peripheral portion 126 has a pair of surfaces (hereinafter referred to as a first surface) orthogonal to the X direction and a pair of surfaces (hereinafter referred to as a second surface) orthogonal to the Y direction as inner peripheral surfaces. is doing. The length between the first surfaces (opposite distance) is longer than the length between the second surfaces (opposite distance). That is, the inner peripheral surface has the X direction as the long direction and the Y direction as the short direction.
　第１分離部１２７は、周囲部１２６の内周面に連なっている。第１分離部１２７は、第１面のそれぞれから延設されている。詳しくは、第１面のそれぞれから、２つの第１分離部１２７が延設されている。複数の第１分離部１２７において、第１面からの延設長さは互いにほぼ等しくされている。延設長さは、一組の第１面間の長さ（対向距離）の１／２よりも短くされている。 The first separation portion 127 is continuous with the inner peripheral surface of the peripheral portion 126. The first separation part 127 extends from each of the first surfaces. Specifically, two first separation portions 127 are extended from each of the first surfaces. In the plurality of first separation portions 127, the extending lengths from the first surface are substantially equal to each other. The extended length is shorter than ½ of the length (opposite distance) between the pair of first surfaces.
　第１分離部１２７は、Ｚ方向に直交する第２方向であるＹ方向において、表面電極１２１を区切っている。Ｙ方向が列方向に相当する。本実施形態では、表面電極１２１が、同じ第１面に連なる２つの第１分離部１２７により、Ｙ方向において互いに略等しい長さに区切られている。すなわち、表面電極１２１は、第１分離部１２７により三等分されている。第１分離部１２７は、Ｘ方向において２つに分離されている。第１分離部１２７は下地膜１２２上に設けられており、金属薄膜であるＮｉ膜１２３及びＡｕ膜１２４が第１分離部１２７により区切られている。 The first separator 127 divides the surface electrode 121 in the Y direction, which is the second direction orthogonal to the Z direction. The Y direction corresponds to the column direction. In the present embodiment, the surface electrode 121 is divided into substantially equal lengths in the Y direction by two first separation portions 127 that are continuous with the same first surface. That is, the surface electrode 121 is divided into three equal parts by the first separator 127. The first separation unit 127 is separated into two in the X direction. The first separation portion 127 is provided on the base film 122, and the Ni film 123 and the Au film 124 that are metal thin films are separated by the first separation portion 127.
　第２分離部１２８は、Ｙ方向に沿って延設されている。保護膜１２５は、第２分離部１２８をひとつ有している。第２分離部１２８も、周囲部１２６の内周面に連なっている。第２分離部１２８は、第２面から延設されている。第２分離部１２８は、第２面間を跨ぐように設けられている。第２分離部１２８の延設長さは、一組の第２面間の長さ（対向距離）とほぼ等しくされている。 The second separation unit 128 extends along the Y direction. The protective film 125 has one second separation unit 128. The second separation part 128 is also connected to the inner peripheral surface of the peripheral part 126. The second separation unit 128 extends from the second surface. The second separation unit 128 is provided so as to straddle the second surface. The extending length of the second separation portion 128 is substantially equal to the length (opposite distance) between the pair of second surfaces.
　第２分離部１２８は、Ｘ方向において、表面電極１２１を区切っている。本実施形態では、表面電極１２１が、第２分離部１２８により、Ｘ方向において互いに略等しい長さに区切られている。すなわち、表面電極１２１は、第２分離部１２８により二等分されている。第２分離部１２８も下地膜１２２上に設けられており、金属薄膜であるＮｉ膜１２３及びＡｕ膜１２４が第２分離部１２８により区切られている。第２分離部１２８は、Ｘ方向において、アクティブ領域の中央に設けられている。各第１分離部１２７は、第２分離部１２８と交差しないように、すなわち第２分離部１２８に連ならないように、第２分離部１２８に対して離れて設けられている。 The second separator 128 divides the surface electrode 121 in the X direction. In the present embodiment, the surface electrodes 121 are partitioned by the second separator 128 into substantially equal lengths in the X direction. That is, the surface electrode 121 is divided into two equal parts by the second separator 128. The second separation portion 128 is also provided on the base film 122, and the Ni film 123 and the Au film 124 that are metal thin films are separated by the second separation portion 128. The second separation unit 128 is provided in the center of the active region in the X direction. Each first separation unit 127 is provided apart from the second separation unit 128 so as not to intersect the second separation unit 128, that is, not to be connected to the second separation unit 128.
　このような保護膜１２５により、表面電極１２１（金属薄膜）は、その中心１２１ａ周りに２回対称性を有している。保護膜１２５は、Ｘ方向において、第２分離部１２８と各第１分離部１２７との間に、所定のギャップを有している。本実施形態では、上記ギャップ、すなわち第１分離部１２７と第２分離部１２８との対向領域にも、金属薄膜であるＮｉ膜１２３及びＡｕ膜１２４が配置されている。この対向領域は、表面電極１２１において第１分離部１２７により区切られた部分を連結する第１連結部１２１ｂとされている。表面電極１２１は、４つの第１連結部１２１ｂを有している。 By such a protective film 125, the surface electrode 121 (metal thin film) has two-fold symmetry around the center 121a. The protective film 125 has a predetermined gap between the second separator 128 and each first separator 127 in the X direction. In the present embodiment, the Ni film 123 and the Au film 124 that are metal thin films are also disposed in the gap, that is, the region where the first separation portion 127 and the second separation portion 128 are opposed to each other. This opposing region is a first connecting portion 121b that connects portions separated by the first separating portion 127 in the surface electrode 121. The surface electrode 121 has four first connecting portions 121b.
　パッド１２９は、信号端子１８が電気的に接続される電極である。パッド１２９も、表面電極１２１と同様の多層膜構造をなしている。パッド１２９は、表面１２０ａにおいて、表面電極１２１とは別の位置に形成されている。パッド１２９は、表面電極１２１と電気的に分離されている。パッド１２９は、Ｙ方向において、表面電極１２１の形成領域とは反対側の端部に形成されている。 The pad 129 is an electrode to which the signal terminal 18 is electrically connected. The pad 129 also has a multilayer structure similar to that of the surface electrode 121. The pad 129 is formed at a position different from the surface electrode 121 on the surface 120a. The pad 129 is electrically separated from the surface electrode 121. The pad 129 is formed at the end on the opposite side of the surface electrode 121 formation region in the Y direction.
　本実施形態では、半導体チップ１２が、５つのパッド１２９を有している。詳しくは、パッド１２９として、半導体基板１２０の温度を検出する温度センサ（感温ダイオード）のアノード電位用、同じくカソード電位用、ゲート電極用、電流センス用、表面電極１２１（エミッタ電極）の電位を検出するケルビンエミッタ用を有している。本実施形態では、Ｘ方向において、一端側から、カソード電位用、アノード電位用、ゲート電極用、電流センス用、ケルビンエミッタ用の順に形成されている。５つのパッド１２９は、平面略矩形状の半導体基板１２０において、Ｙ方向の一端側にまとめって形成されるとともに、Ｘ方向に並んで形成されている。各パッド１２９は、周囲部１２６によって取り囲まれている。 In the present embodiment, the semiconductor chip 12 has five pads 129. Specifically, as the pad 129, the potential of the anode potential of the temperature sensor (temperature-sensitive diode) for detecting the temperature of the semiconductor substrate 120, the cathode potential, the gate electrode, the current sense, and the potential of the surface electrode 121 (emitter electrode) are similarly used. It has a Kelvin emitter for detection. In the present embodiment, in the X direction, the cathode potential, anode potential, gate electrode, current sense, and Kelvin emitter are formed in this order from one end side. The five pads 129 are collectively formed on one end side in the Y direction and formed side by side in the X direction on the substantially rectangular planar semiconductor substrate 120. Each pad 129 is surrounded by a peripheral portion 126.
　半導体基板１２０の裏面１２０ｂには、裏面電極１３０が形成されている。裏面電極１３０は、コレクタ領域及びカソード領域と電気的に接続された電極である。このため、裏面電極１３０は、コレクタ電極とも称される。裏面電極１３０は、コレクタ電極として機能するだけでなく、ＦＷＤのカソード電極も兼ねている。また、表面電極１２１との間に電流が流れるため、主電極とも称される。 A back electrode 130 is formed on the back surface 120 b of the semiconductor substrate 120. The back electrode 130 is an electrode that is electrically connected to the collector region and the cathode region. For this reason, the back electrode 130 is also referred to as a collector electrode. The back electrode 130 not only functions as a collector electrode, but also serves as an FWD cathode electrode. In addition, since a current flows between the surface electrode 121 and the surface electrode 121, it is also called a main electrode.
　裏面電極１３０は、裏面１２０ｂのほぼ全面に形成されている。裏面電極１３０も多層膜構造をなしている。図示を省略するが、裏面電極１３０も下地膜及び金属薄膜を有している。下地膜は、ＡｌＳｉを材料とし、スパッタにより形成されている。本実施形態では、金属薄膜として、Ｎｉ膜及びＡｕ膜を有している。Ｎｉ膜は、スパッタにより形成されている。Ａｕ膜は、めっき膜とされている。裏面電極１３０におけるＮｉ膜の厚みは、表面電極１２１におけるＮｉ膜１２３の厚みよりも薄くされている。これにより、裏面電極１３０の厚みは、表面電極１２１の厚み（積層部分の厚み）よりも薄くされている。 The back electrode 130 is formed on almost the entire back surface 120b. The back electrode 130 also has a multilayer structure. Although not shown, the back electrode 130 also has a base film and a metal thin film. The base film is made of AlSi and is formed by sputtering. In the present embodiment, the metal thin film includes a Ni film and an Au film. The Ni film is formed by sputtering. The Au film is a plating film. The thickness of the Ni film on the back electrode 130 is made thinner than the thickness of the Ni film 123 on the front electrode 121. Thereby, the thickness of the back electrode 130 is made thinner than the thickness of the front electrode 121 (thickness of the laminated portion).
　次に、半導体モジュール１０の製造方法の一例について説明する。 Next, an example of a method for manufacturing the semiconductor module 10 will be described.
　先ず、半導体モジュール１０を構成する各要素を準備する。すなわち、半導体チップ１２、信号端子１８、ターミナル２２、主端子２８が連なるヒートシンク２６、及び主端子３４が連なるヒートシンク３２をそれぞれ準備する。上記した表面電極１２１及び保護膜１２５を有する半導体チップ１２を準備する。 First, each element constituting the semiconductor module 10 is prepared. That is, the semiconductor chip 12, the signal terminal 18, the terminal 22, the heat sink 26 connected with the main terminal 28, and the heat sink 32 connected with the main terminal 34 are prepared. The semiconductor chip 12 having the surface electrode 121 and the protective film 125 described above is prepared.
　次いで、ヒートシンク３２の対向面上に、はんだ３０を介して、半導体チップ１２を配置する。裏面電極１３０がヒートシンク３２と対向するように、半導体チップ１２を配置する。次に、たとえば予め両面にはんだ２０，２４が迎えはんだとして配置されたターミナル２２を、はんだ２０が半導体チップ１２側となるように配置する。はんだ２４については、半導体モジュール１０における高さばらつきを吸収可能な量を配置しておく。 Next, the semiconductor chip 12 is disposed on the opposite surface of the heat sink 32 via the solder 30. The semiconductor chip 12 is arranged so that the back electrode 130 faces the heat sink 32. Next, for example, the terminal 22 in which the solders 20 and 24 are arranged on both sides in advance as the incoming solder is arranged so that the solder 20 is on the semiconductor chip 12 side. About the solder 24, the quantity which can absorb the height variation in the semiconductor module 10 is arrange | positioned.
　そして、この積層状態で、はんだ２０，２４，３０をリフロー（１ｓｔリフロー）させることにより、はんだ３０を介して、半導体チップ１２の裏面電極１３０とヒートシンク３２を接続する。また、はんだ２０を介して、半導体チップ１２の表面電極１２１とターミナル２２を接続する。はんだ２４については、接続対象であるヒートシンク２６がまだないので、表面張力により、ヒートシンク２６との対向面の中心を頂点として盛り上がった形状となる。 Then, in this laminated state, the solder 20, 24, 30 is reflowed (1st reflow), thereby connecting the back electrode 130 of the semiconductor chip 12 and the heat sink 32 via the solder 30. Further, the surface electrode 121 of the semiconductor chip 12 and the terminal 22 are connected via the solder 20. Since there is no heat sink 26 to be connected yet, the solder 24 has a shape that rises with the center of the surface facing the heat sink 26 as a vertex due to surface tension.
　次いで、半導体チップ１２のパッド１２９と信号端子１８を、ボンディングワイヤ１６により接続する。以上により、半導体チップ１２、信号端子１８、ターミナル２２、及びヒートシンク３２が一体化された接続体を得る。 Next, the pads 129 of the semiconductor chip 12 and the signal terminals 18 are connected by the bonding wires 16. Thus, a connection body in which the semiconductor chip 12, the signal terminal 18, the terminal 22, and the heat sink 32 are integrated is obtained.
　次いで、はんだ２４を介して、上記した接続体とヒートシンク２６を接続する。詳しくは、ターミナル２２との対向面が上になるようにしてヒートシンク２６を図示しない台座上に配置する。そして、ターミナル２２がヒートシンク２６に対向するように、接続体をヒートシンク２６上に配置し、はんだ２０，２４，３０をリフロー（２ｎｄリフロー）させる。この２ｎｄリフローでは、ヒートシンク２６側から荷重を加えることで、半導体モジュール１０の高さが所定の高さとなるようにする。詳しくは、図示しないスペーサを、ヒートシンク２６と台座との間に配置し、スペーサを、ヒートシンク２６と台座の両方に接触させる。このようにして、半導体モジュール１０の高さが所定の高さとなるようにする。 Next, the connection body and the heat sink 26 are connected via the solder 24. Specifically, the heat sink 26 is disposed on a pedestal (not shown) so that the surface facing the terminal 22 faces up. And a connection body is arrange | positioned on the heat sink 26 so that the terminal 22 may oppose the heat sink 26, and the solder 20, 24, 30 is reflowed (2nd reflow). In this 2nd reflow, the load of the heat sink 26 is applied so that the height of the semiconductor module 10 becomes a predetermined height. Specifically, a spacer (not shown) is disposed between the heat sink 26 and the base, and the spacer is brought into contact with both the heat sink 26 and the base. In this way, the height of the semiconductor module 10 is set to a predetermined height.
　次いで、トランスファモールド法により封止樹脂体１４の成形を行う。本実施形態では、ヒートシンク２６，３２が完全に被覆されるように、封止樹脂体１４を成形する。そして、成形した封止樹脂体１４をヒートシンク２６，３２の一部ごと切削することにより、ヒートシンク２６，３２の放熱面２６ａ，３２ａを露出させる。 Next, the sealing resin body 14 is molded by a transfer mold method. In the present embodiment, the sealing resin body 14 is molded so that the heat sinks 26 and 32 are completely covered. Then, by cutting the molded sealing resin body 14 together with a part of the heat sinks 26 and 32, the heat radiation surfaces 26a and 32a of the heat sinks 26 and 32 are exposed.
　なお、ヒートシンク２６，３２の放熱面２６ａ，３２ａを成形金型のキャビティ壁面に押し当て、密着させた状態で、封止樹脂体１４を成形してもよい。この場合、封止樹脂体１４を成形した時点で、放熱面２６ａ，３２ａが封止樹脂体１４から露出される。このため、成形後の切削が不要となる。 The sealing resin body 14 may be molded in a state where the heat radiation surfaces 26a and 32a of the heat sinks 26 and 32 are pressed against and adhered to the cavity wall surface of the molding die. In this case, when the sealing resin body 14 is molded, the heat radiation surfaces 26 a and 32 a are exposed from the sealing resin body 14. For this reason, the cutting after shaping | molding becomes unnecessary.
　そして、リードフレームの不要部分を除去することで、半導体モジュール１０を得ることができる。 Then, the semiconductor module 10 can be obtained by removing unnecessary portions of the lead frame.
　次に、図５～図１３に基づき、上記した半導体チップ１２及び該半導体チップ１２を備える半導体モジュール１０の効果について説明する。図５～図１０は、比較例を示している。図６は、はんだ付けした状態、すなわち半導体モジュールの状態で、Ｚ方向から超音波探傷装置（SAT：Scanning Acoustic Tomograph）により、はんだのボイドを検査した結果を示している。図１０では、半導体チップ１２の構造を簡素化して図示している。比較例における各要素の符号については、本実施形態の関連する要素の符号末尾にｒを追加したものとしている。図９～図１２では、リフロー時の水蒸気の流れを矢印で示している。 Next, the effects of the semiconductor chip 12 and the semiconductor module 10 including the semiconductor chip 12 will be described with reference to FIGS. 5 to 10 show comparative examples. FIG. 6 shows a result of inspecting a solder void by an ultrasonic flaw detector (SAT: Scanning Acoustic Tomograph) from the Z direction in a soldered state, that is, in a semiconductor module state. FIG. 10 shows a simplified structure of the semiconductor chip 12. Regarding the reference numerals of the elements in the comparative example, r is added to the end of the reference numerals of the related elements in the present embodiment. 9 to 12, the flow of water vapor during reflow is indicated by arrows.
　本発明者は、図５に示す構成の半導体チップ１２ｒを試作した。半導体チップ１２ｒにおいて、第１分離部１２７ｒは、周囲部１２６ｒの第１面間を跨ぐようにＸ方向に沿って延設されており、Ｘ方向の中央付近で、第２分離部１２８ｒと交差している。すなわち、保護膜１２５ｒが、第１分離部１２７ｒと第２分離部１２８ｒとが交差してなる交差部１３１ｒを有している。それ以外の点は、本実施形態（図２参照）と同じとされている。 The inventor made a prototype of the semiconductor chip 12r having the configuration shown in FIG. In the semiconductor chip 12r, the first separation portion 127r extends along the X direction so as to straddle the first surface of the peripheral portion 126r, and intersects the second separation portion 128r near the center in the X direction. ing. That is, the protective film 125r has an intersecting portion 131r formed by intersecting the first separating portion 127r and the second separating portion 128r. Other points are the same as in the present embodiment (see FIG. 2).
　そして、本発明者は、半導体チップ１２ｒを用いて、上記した製造方法により半導体モジュールを形成し、得られた半導体モジュールについてＳＡＴにより検査を行った。 And this inventor formed the semiconductor module with the manufacturing method mentioned above using the semiconductor chip 12r, and inspected the obtained semiconductor module by SAT.
　周囲部１２６ｒ内に設けられた第１分離部１２７ｒ及び第２分離部１２８ｒは、はんだ２０ｒに対する濡れ性が表面電極１２１ｒに対して低い。このため、リフロー時において、はんだ２０ｒが第１分離部１２７ｒ及び第２分離部１２８ｒ上に濡れ拡がらず、図６及び図７に示すように、不濡れ部３６ｒが形成される。不濡れ部３６ｒは、はんだ２０ｒと、第１分離部１２７ｒ及び第２分離部１２８ｒとはんだ２０ｒとの界面に形成される。不濡れ部３６ｒは、はんだ２０ｒが濡れずに引けた部分である。ＳＡＴにより、この不濡れ部３６ｒが確認された。不濡れ部３６ｒは、保護膜１２５ｒによる表面電極１２１ｒを区切る構成において確認されるものである。 The first separation portion 127r and the second separation portion 128r provided in the peripheral portion 126r have lower wettability with respect to the solder 20r than the surface electrode 121r. Therefore, during reflow, the solder 20r does not wet and spread on the first separation portion 127r and the second separation portion 128r, and the non-wetting portion 36r is formed as shown in FIGS. The non-wetting portion 36r is formed at the interface between the solder 20r, the first separation portion 127r, the second separation portion 128r, and the solder 20r. The non-wetting portion 36r is a portion where the solder 20r can be pulled without getting wet. This non-wetting part 36r was confirmed by SAT. The non-wetting portion 36r is confirmed in the configuration in which the surface electrode 121r is separated by the protective film 125r.
　さらに、図６及び図８に示すように、はんだ２０ｒにボイド３８ｒが生じることがあることが明らかとなった。ボイド３８ｒは、はんだ２０ｒにおいて交差部１３１及びその周辺の直上部分に生じた。ボイド３８ｒは、保護膜１２５（第１分離部１２７ｒ及び第２分離部１２８ｒ）上の不濡れ部３６ｒを含んで形成される。ボイド３８ｒは、少なくとも、はんだ２０ｒにおける半導体チップ１２側の面に開口している。この試験では、ボイド３８ｒが、はんだ２０ｒを貫通していた。また、１ｓｔリフロー終了後から２ｎｄリフロー開始までの時間が長いほど、ボイド３８ｒが発生しやすいことも明らかとなった。 Furthermore, as shown in FIG. 6 and FIG. 8, it has been clarified that a void 38r may occur in the solder 20r. The void 38r was generated in the solder 20r at the intersecting portion 131 and the portion directly above the periphery. The void 38r is formed including the non-wetting portion 36r on the protective film 125 (the first separation portion 127r and the second separation portion 128r). The void 38r is opened at least on the surface of the solder 20r on the semiconductor chip 12 side. In this test, the void 38r penetrated the solder 20r. It was also found that the void 38r is more likely to occur as the time from the end of the first reflow to the start of the second reflow is longer.
　このように、保護膜１２５ｒが交差部１３１ｒを有し、第１分離部１２７ｒ及び第２分離部１２８ｒにより、表面電極１２１（金属薄膜）が複数に分割される構成では、はんだ２０ｒにおいて表面電極１２１上の部分にボイド３８ｒが生じうることが明らかとなった。 In this way, in the configuration in which the protective film 125r has the intersection 131r and the surface electrode 121 (metal thin film) is divided into a plurality of parts by the first separation part 127r and the second separation part 128r, the surface electrode 121 in the solder 20r. It became clear that a void 38r could occur in the upper part.
　保護膜１２５ｒは吸湿性を有しており、リフロー時に、保護膜１２５ｒ中の水分が気化する。水蒸気は保護膜１２５ｒ内、又は、はんだ２０ｒとの界面である不濡れ部３６ｒ内を移動する。たとえば第１分離部１２７ｒにおいて、水蒸気の一部は交差部１３１ｒに近づく方向に移動する。図９に示すように、交差部１３１ｒ又はその直上の不濡れ部３６ｒには、交差部１３１ｒに連なる第１分離部１２７ｒ及び第２分離部１２８ｒ（又は不濡れ部３６ｒ）から水蒸気が集まり滞留する。これが、交差部１３１ｒの周辺にボイド３８ｒが生じる第１の推定原因である。 The protective film 125r has a hygroscopic property, and moisture in the protective film 125r is vaporized during reflow. The water vapor moves in the protective film 125r or in the non-wetting portion 36r that is an interface with the solder 20r. For example, in the first separation unit 127r, a part of the water vapor moves in a direction approaching the intersection 131r. As shown in FIG. 9, water vapor collects and stays at the intersecting portion 131r or the unwetting portion 36r immediately above it from the first separation portion 127r and the second separation portion 128r (or the non-wetting portion 36r) connected to the intersecting portion 131r. . This is the first estimation cause that the void 38r is generated around the intersection 131r.
　また、半導体基板１２０ｒの薄板化や表裏でのバイメタル効果の違いから、表面電極１２１ｒを保護膜１２５ｒによって分割しても、図１０に示すように、半導体チップ１２ｒに少なからず反りが生じる。具体的には、表面電極１２１ｒ側に凹の反りが生じる。図１０では、便宜上、裏面電極１３０ｒを省略している。２ｎｄリフロー時に、凸側である裏面電極１３０ｒが上方、凹側である表面電極１２１ｒが下方の配置となるため、第１分離部１２７ｒ及び第２分離部１２８ｒ（又は不濡れ部３６ｒ）を通じて交差部１３１ｒに水蒸気が集まり滞留する。特に周囲部１２６ｒの水蒸気も、交差部１３１ｒ側に移動する。これが、交差部１３１ｒの周辺にボイド３８ｒが生じる第２の推定原因である。 Further, due to the thinning of the semiconductor substrate 120r and the difference in bimetal effect between the front and back surfaces, even if the surface electrode 121r is divided by the protective film 125r, the semiconductor chip 12r is warped to some extent as shown in FIG. Specifically, a concave warp occurs on the surface electrode 121r side. In FIG. 10, the back electrode 130r is omitted for convenience. At the time of 2nd reflow, the rear surface electrode 130r which is the convex side is arranged upward, and the front surface electrode 121r which is the concave side is arranged downward, so that the intersecting portion is passed through the first separation portion 127r and the second separation portion 128r (or the non-wetting portion 36r) Water vapor collects and stays at 131r. In particular, the water vapor in the surrounding portion 126r also moves toward the intersecting portion 131r. This is the second presumed cause that the void 38r is generated around the intersection 131r.
　本実施形態では、保護膜１２５が、Ｘ方向に延びる第１分離部１２７とＹ方向に延びる第２分離部１２８を有しており、これにより表面電極１２１がＸ方向及びＹ方向の両方向において区切られている。したがって、半導体チップ１２の反りを低減することができる。 In the present embodiment, the protective film 125 includes a first separation portion 127 extending in the X direction and a second separation portion 128 extending in the Y direction, whereby the surface electrode 121 is partitioned in both the X direction and the Y direction. It has been. Therefore, the warp of the semiconductor chip 12 can be reduced.
　また、保護膜１２５に、第１分離部１２７と第２分離部１２８との交差部がない。したがって、リフロー時に保護膜１２５中の水分が気化してなる水蒸気の一部が、第１分離部１２７及び第２分離部１２８のそれぞれから交差部１３１ｒに相当する部分に向かって移動しても、図１１に示すように、一箇所に集まることはない。第１分離部１２７と第２分離部１２８との対向領域には、表面電極１２１の第１連結部１２１ｂが存在しており、第１分離部１２７中の水蒸気と第２分離部１２８中の水蒸気が交わらない。したがって、はんだ２０における表面電極１２１上の部分にボイドが生じるのを抑制することができる。 In addition, the protective film 125 does not have a crossing portion between the first separation portion 127 and the second separation portion 128. Therefore, even if a part of the water vapor formed by vaporization of the water in the protective film 125 during reflow moves from each of the first separation unit 127 and the second separation unit 128 toward the portion corresponding to the intersection 131r, As shown in FIG. 11, they are not collected in one place. The first connecting portion 121b of the surface electrode 121 is present in the opposing region between the first separating portion 127 and the second separating portion 128, and the water vapor in the first separating portion 127 and the water vapor in the second separating portion 128 are present. Does not cross. Therefore, it can suppress that a void arises in the part on the surface electrode 121 in the solder 20. FIG.
　また、図１２に示すように、半導体チップ１２が、表面電極１２１側を凹として反っていても、第１分離部１２７と第２分離部１２８とが連なっておらず、間に第１連結部１２１ｂが存在しているため、第１分離部１２７中の水蒸気と第２分離部１２８中の水蒸気が交わらない。これによっても、水蒸気が局所的に集まるのを抑制し、ひいては、はんだ２０における表面電極１２１上の部分にボイドが生じるのを抑制することができる。 In addition, as shown in FIG. 12, even if the semiconductor chip 12 is warped with the surface electrode 121 side being concave, the first separation portion 127 and the second separation portion 128 are not connected, and the first connection portion is interposed therebetween. Since 121b exists, the water vapor in the 1st separation part 127 and the water vapor in the 2nd separation part 128 do not cross. Also by this, it can suppress that water vapor | steam gathers locally, and can suppress that a void arises in the part on the surface electrode 121 in the solder 20 by extension.
　以上により、本実施形態の半導体チップ１２及び該半導体チップ１２を備える半導体モジュール１０によれば、保護膜１２５によって半導体チップ１２の反りを低減しつつ、はんだ２０における表面電極１２１上の部分にボイドが生じるのを抑制することができる。図１３は、図２のXIII-XIII線に沿う断面図であり、図８（比較例）に対応している。図１３に示すように、比較例においてボイド３８ｒが生じる部分においても、ボイドが生じず、保護膜１２５（図１３では第２分離部１２８）上に不濡れ部３６が形成されるに留まる。 As described above, according to the semiconductor chip 12 of the present embodiment and the semiconductor module 10 including the semiconductor chip 12, voids are formed on the portion of the solder 20 on the surface electrode 121 while reducing the warp of the semiconductor chip 12 by the protective film 125. It can be suppressed from occurring. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 2, and corresponds to FIG. 8 (comparative example). As shown in FIG. 13, even in the portion where the void 38r is generated in the comparative example, no void is generated, and the non-wetting portion 36 is merely formed on the protective film 125 (second separation portion 128 in FIG. 13).
　さらに本実施形態では、第１分離部１２７及び第２分離部１２８のうち、第１分離部１２７が、その延設方向であるＸ方向において複数の分割されている。したがって、半導体チップ１２の反りを効果的に低減しつつ、表面電極１２１上にボイドが生じるのを抑制することができる。特に本実施形態では、長手方向において複数に分割されている。換言すれば、両端間の長さの長い第１分離部１２７が複数に分割されている。したがって、長手方向の中央付近に水蒸気が集まるのを効果的に抑制することができる。 Further, in the present embodiment, among the first separation unit 127 and the second separation unit 128, the first separation unit 127 is divided into a plurality of pieces in the X direction that is the extending direction. Therefore, it is possible to suppress the generation of voids on the surface electrode 121 while effectively reducing the warpage of the semiconductor chip 12. In particular, in this embodiment, it is divided into a plurality in the longitudinal direction. In other words, the first separation part 127 having a long length between both ends is divided into a plurality of parts. Therefore, it is possible to effectively suppress water vapor from being collected near the center in the longitudinal direction.
　また、第１分離部１２７及び第２分離部１２８のそれぞれが、周囲部１２６に連なっている。しかしながら、第１分離部１２７と第２分離部１２８とが連なっておらず、間に第１連結部１２１ｂが存在しているため、周囲部１２６の水蒸気（水分）が、第１分離部１２７を通じて、第２分離部１２８中の水蒸気と交わらない。したがって、第１分離部１２７及び第２分離部１２８が周囲部１２６に連なる構成でありながら、ボイドが生じるのを抑制することができる。 In addition, each of the first separation unit 127 and the second separation unit 128 is connected to the peripheral portion 126. However, since the first separation unit 127 and the second separation unit 128 are not connected and the first connection unit 121b exists between them, the water vapor (moisture) in the surrounding portion 126 passes through the first separation unit 127. It does not intersect with the water vapor in the second separation part 128. Therefore, it is possible to suppress the generation of voids even though the first separation unit 127 and the second separation unit 128 are configured to be continuous with the peripheral portion 126.
　また、多層膜構造の表面電極１２１において、複数の薄膜のうち、最も剛性の大きい膜であるＮｉ膜１２３が、保護膜１２５の第１分離部１２７及び第２分離部１２８によって区切られている。これにより、半導体チップ１２の反りを低減することができる。なお、剛性が大きいとは、温度差による膜自体の膨張、収縮する力が大きいことを言う。剛性の大きいＮｉ膜１２３を区切ることで、表裏でのバイメタル効果の差を小さくし、反りを低減することができる。 Also, in the surface electrode 121 having a multilayer structure, the Ni film 123 that is the most rigid film among the plurality of thin films is divided by the first separation part 127 and the second separation part 128 of the protective film 125. Thereby, the curvature of the semiconductor chip 12 can be reduced. In addition, that rigidity is large means that the expansion | swelling and shrinkage | contraction force of the film | membrane itself by a temperature difference are large. By dividing the Ni film 123 having high rigidity, the difference in the bimetal effect between the front and back surfaces can be reduced, and the warpage can be reduced.
　ところで、半導体チップ１２の温度は、素子の駆動によりアクティブ領域の中心付近、すなわち表面電極１２１の中心１２１ａ付近で最も高くなる。本実施形態では、第１分離部１２７と第２分離部１２８との対向領域には、第１連結部１２１ｂ、すなわちＮｉ膜１２３及びＡｕ膜１２４が配置されており、はんだ２０が接続（接合）される。したがって、半導体チップ１２の熱を、ターミナル２２側に効果的に放熱させることができる。 By the way, the temperature of the semiconductor chip 12 becomes highest near the center of the active region, that is, near the center 121a of the surface electrode 121 by driving the element. In the present embodiment, the first connecting portion 121b, that is, the Ni film 123 and the Au film 124 are arranged in the opposing region of the first separation portion 127 and the second separation portion 128, and the solder 20 is connected (joined). Is done. Therefore, the heat of the semiconductor chip 12 can be effectively radiated to the terminal 22 side.
　なお、第１分離部１２７を分割せず、第２分離部１２８のみを複数に分割してもよい。しかしながら、表面電極１２１（下地膜１２２）上に配置される保護膜１２５の長さが長いほど、水蒸気が表面電極１２１上に滞留する可能性が高まるため、上記したように、長手側の第１分離部１２７を分割したほうが良い。 Note that the first separation unit 127 may not be divided, and only the second separation unit 128 may be divided into a plurality of pieces. However, as the length of the protective film 125 disposed on the surface electrode 121 (the base film 122) is longer, the possibility that water vapor stays on the surface electrode 121 is increased. It is better to divide the separation unit 127.
　周囲部１２６の同一面に連なる第１分離部１２７及び第２分離部１２８それぞれの数は上記例に限定されない。たとえば第２面間を繋ぐ第２分離部１２８を２つ有してもよい。この場合、第１分離部１２７は、Ｘ方向においてたとえば３つに分割される。 The numbers of the first separation unit 127 and the second separation unit 128 that are connected to the same surface of the peripheral portion 126 are not limited to the above example. For example, you may have two 2nd isolation | separation parts 128 which connect between 2nd surfaces. In this case, the first separation unit 127 is divided into, for example, three parts in the X direction.
　（第２実施形態）
　本実施形態は、先行実施形態を参照できる。このため、先行実施形態に示した半導体モジュール１０及び半導体チップ１２と共通する部分についての説明は省略する。 (Second Embodiment)
This embodiment can refer to the preceding embodiment. For this reason, the description of the parts common to the semiconductor module 10 and the semiconductor chip 12 shown in the previous embodiment is omitted.
　図１４及び図１５に示すように、本実施形態の半導体チップ１２では、第１分離部１２７だけでなく、第２分離部１２８も複数に分割されている。そして、第１分離部１２７と第２分離部１２８が交差しないように、第２分離部１２８は、その延設方向であるＹ方向において３つに分割されている。３つの第２分離部１２８のうち、両端に位置する第２分離部１２８はそれぞれ周囲部１２６に連なっている。残りの第２分離部１２８は、周囲部１２６から離れて設けられ、保護膜１２５における他の部分に対して独立している。 14 and 15, in the semiconductor chip 12 of this embodiment, not only the first separation unit 127 but also the second separation unit 128 is divided into a plurality of parts. And the 2nd separation part 128 is divided | segmented into three in the Y direction which is the extension direction so that the 1st separation part 127 and the 2nd separation part 128 may not cross | intersect. Of the three second separators 128, the second separators 128 located at both ends are connected to the peripheral part 126. The remaining second separation portion 128 is provided apart from the peripheral portion 126 and is independent of other portions of the protective film 125.
　第１分離部１２７間の対向領域と、第２分離部１２８間の対向領域とが一体的に連なっている。すなわち、同じ位置で、第１分離部１２７と第２分離部１２８が分割されている。本実施形態では、対向領域に金属薄膜であるＮｉ膜１２３及びＡｕ膜１２４が配置され、これにより、はんだ２０が接続される第２連結部１２１ｃが形成されている。第２連結部１２１ｃは、平面略十字状をなしている。表面電極１２１は、２つの第２連結部１２１ｃを有している。第２連結部１２１ｃは、表面電極１２１において、第２分離部１２８によりＸ方向において区切られた部分同士を連結するとともに、第１分離部１２７によりＹ方向において区切られた部分同士を連結している。 The opposing region between the first separation parts 127 and the opposing region between the second separation parts 128 are integrally connected. That is, the first separation unit 127 and the second separation unit 128 are divided at the same position. In the present embodiment, the Ni film 123 and the Au film 124 that are metal thin films are arranged in the facing region, and thereby, the second connecting portion 121c to which the solder 20 is connected is formed. The 2nd connection part 121c has comprised the plane substantially cross shape. The surface electrode 121 has two second connecting portions 121c. The second connecting portion 121c connects the portions separated in the X direction by the second separating portion 128 in the surface electrode 121 and also connects the portions separated in the Y direction by the first separating portion 127. .
　次に、上記した半導体チップ１２及び該半導体チップ１２を備える半導体モジュール１０の効果について説明する。 Next, the effects of the semiconductor chip 12 and the semiconductor module 10 including the semiconductor chip 12 will be described.
　本実施形態では、第１分離部１２７及び第２分離部１２８がそれぞれ複数に分割され、これにより交差部を有さない。図１６に示すように、第１分離部１２７中の水蒸気と第２分離部１２８中の水蒸気が交わらない。また、分割された第１分離部１２７中の水蒸気が交わらず、分割された第２分離部１２８中の水蒸気が交わらない。したがって、半導体チップ１２の反りを低減しつつ、はんだ２０における表面電極１２１上の部分にボイドが生じるのを効果的に抑制することができる。 In the present embodiment, each of the first separation unit 127 and the second separation unit 128 is divided into a plurality of parts, and thus has no intersection. As shown in FIG. 16, the water vapor in the first separator 127 and the water vapor in the second separator 128 do not intersect. Further, the water vapor in the divided first separation unit 127 does not intersect, and the water vapor in the divided second separation unit 128 does not intersect. Therefore, it is possible to effectively suppress the occurrence of voids in the portion of the solder 20 on the surface electrode 121 while reducing the warp of the semiconductor chip 12.
　また、周囲部１２６の水蒸気（水分）が、第１分離部１２７を通じて、分割された他の第１分離部１２７や第２分離部１２８中の水蒸気と交わらない。同じく、周囲部１２６の水蒸気が、第２分離部１２８を通じて、分割された他の第２分離部１２８や第１分離部１２７中の水蒸気と交わらない。これによっても、ボイドが生じるのを抑制することができる。 Also, the water vapor (moisture) in the surrounding portion 126 does not intersect with the water vapor in the other divided first separation portion 127 and second separation portion 128 through the first separation portion 127. Similarly, the water vapor in the peripheral portion 126 does not intersect with the water vapor in the other divided second separation portion 128 or the first separation portion 127 through the second separation portion 128. Also by this, it can suppress that a void arises.
　また、第２連結部１２１ｃは、平面略十字状をなしており、第１連結部１２１ｂよりもＸＹ平面に沿う面積が大きい。このため、第１連結部１２１ｂよりも第２連結部１２１ｃのほうが、はんだ２０との接続面積が大きい。高温となる中心１２１ａの近傍に、第２連結部１２１ｃを設けているため、半導体チップ１２の熱を、さらに効果的に放熱させることができる。 Further, the second connecting portion 121c has a substantially cross shape in a plane, and has a larger area along the XY plane than the first connecting portion 121b. For this reason, the 2nd connection part 121c has a larger connection area with the solder 20 than the 1st connection part 121b. Since the second connecting portion 121c is provided in the vicinity of the center 121a that is at a high temperature, the heat of the semiconductor chip 12 can be radiated more effectively.
　なお、第１分離部１２７がＸ方向において２つに分割され、第２分離部１２８がＹ方向において３つに分割される例を示したが、分割数は上記例に限定されない。また、周囲部１２６の同一面に連なる第１分離部１２７及び第２分離部１２８それぞれの数も、上記例に限定されない。 Although the example in which the first separation unit 127 is divided into two in the X direction and the second separation unit 128 is divided into three in the Y direction is shown, the number of divisions is not limited to the above example. Further, the numbers of the first separation unit 127 and the second separation unit 128 connected to the same surface of the peripheral portion 126 are not limited to the above example.
　（第３実施形態）
　本実施形態は、先行実施形態を参照できる。このため、先行実施形態に示した半導体モジュール１０及び半導体チップ１２と共通する部分についての説明は省略する。 (Third embodiment)
This embodiment can refer to the preceding embodiment. For this reason, the description of the parts common to the semiconductor module 10 and the semiconductor chip 12 shown in the previous embodiment is omitted.
　図１７に示すように、本実施形態の半導体チップ１２において、保護膜１２５は、第１分離部１２７と第２分離部１２８とが交差する交差部１３１を有している。保護膜１２５は、ひとつの第２分離部１２８と２つの第１分離部１２７を有している。２つの第１分離部１２７は互いに同じ長さを有しており、この第１分離部１２７により、表面電極１２１がＹ方向において三等分されている。第２分離部１２８はＸ方向における中央に設けられており、この第２分離部１２８により、表面電極１２１がＸ方向において二等分されている。保護膜１２５は、２つの交差部１３１を有している。 As shown in FIG. 17, in the semiconductor chip 12 of the present embodiment, the protective film 125 has an intersecting portion 131 where the first separating portion 127 and the second separating portion 128 intersect. The protective film 125 has one second separator 128 and two first separators 127. The two first separators 127 have the same length, and the surface electrode 121 is divided into three equal parts in the Y direction by the first separators 127. The second separator 128 is provided at the center in the X direction, and the surface electrode 121 is divided into two equal parts in the X direction by the second separator 128. The protective film 125 has two intersecting portions 131.
　第１分離部１２７は、周囲部１２６に連ならないように周囲部１２６に対して離れて設けられている。第１分離部１２７の両端のそれぞれと周囲部１２６の内周面との対向領域には、金属薄膜であるＮｉ膜１２３及びＡｕ膜１２４が配置され、これにより、はんだ２０が接続される外周連結部１２１ｄが形成されている。同じく、第２分離部１２８は、周囲部１２６に連ならないように周囲部１２６に対して離れて設けられている。第２分離部１２８の両端のそれぞれと周囲部１２６の内周面との対向領域には、金属薄膜であるＮｉ膜１２３及びＡｕ膜１２４が配置され、これにより、はんだ２０が接続される外周連結部１２１ｅが形成されている。 The first separation portion 127 is provided away from the peripheral portion 126 so as not to be connected to the peripheral portion 126. A Ni film 123 and an Au film 124, which are metal thin films, are arranged in regions facing both ends of the first separation part 127 and the inner peripheral surface of the peripheral part 126, whereby the outer peripheral connection to which the solder 20 is connected. A portion 121d is formed. Similarly, the second separation portion 128 is provided away from the peripheral portion 126 so as not to be continuous with the peripheral portion 126. A Ni film 123 and an Au film 124, which are metal thin films, are arranged in regions opposite to both ends of the second separation part 128 and the inner peripheral surface of the peripheral part 126, whereby the outer peripheral connection to which the solder 20 is connected. A portion 121e is formed.
　表面電極１２１は、６つの外周連結部１２１ｄ，１２１ｅを有している。外周連結部１２１ｄは、表面電極１２１において、第１分離部１２７によりＹ方向において区切られた部分同士を、表面電極１２１の外周端付近で連結している。外周連結部１２１ｅは、表面電極１２１において、第２分離部１２８によりＸ方向において区切られた部分同士を、表面電極１２１の外周端付近で連結している。 The surface electrode 121 has six outer peripheral connection parts 121d and 121e. The outer periphery connecting portion 121 d connects the portions separated in the Y direction by the first separation portion 127 in the surface electrode 121 in the vicinity of the outer peripheral end of the surface electrode 121. The outer periphery connecting portion 121 e connects the portions separated in the X direction by the second separation portion 128 in the surface electrode 121 in the vicinity of the outer peripheral end of the surface electrode 121.
　次に、上記した半導体チップ１２及び該半導体チップ１２を備える半導体モジュール１０の効果について説明する。 Next, the effects of the semiconductor chip 12 and the semiconductor module 10 including the semiconductor chip 12 will be described.
　本実施形態では、保護膜１２５が交差部１３１を有している。しかしながら、第１分離部１２７及び第２分離部１２８が、周囲部１２６に対して離れている。これにより、周囲部１２６の水蒸気（水分）が、第１分離部１２７や第２分離部１２８の水蒸気と交わらない。すなわち、交差部１３１まで周囲部の水蒸気が到達しない。これにより、交差部１３１に集まる水蒸気を低減することができる。また、外周連結部１２１ｄ，１２１ｅの分、第１分離部１２７及び第２分離部１２８の長さが短くされており、これにより、交差部１３１に集まる水蒸気を低減することができる。 In the present embodiment, the protective film 125 has an intersection 131. However, the first separation portion 127 and the second separation portion 128 are separated from the peripheral portion 126. Thereby, the water vapor (moisture) in the peripheral portion 126 does not intersect with the water vapor in the first separation portion 127 or the second separation portion 128. That is, the surrounding water vapor does not reach the intersection 131. Thereby, the water vapor collected at the intersection 131 can be reduced. Moreover, the length of the 1st separation part 127 and the 2nd separation part 128 is shortened for the outer periphery connection parts 121d and 121e, and thereby, water vapor collected at the intersection part 131 can be reduced.
　特に、図１８に示すように、半導体チップ１２が、表面電極１２１側を凹として反っていても、外周連結部１２１ｄ，１２１ｅを有することで、周囲部１２６中の水蒸気が交差部１３１まで到達しない。 In particular, as shown in FIG. 18, even if the semiconductor chip 12 is warped with the surface electrode 121 side being concave, the water vapor in the peripheral portion 126 does not reach the intersecting portion 131 by having the outer peripheral coupling portions 121 d and 121 e. .
　以上により、本実施形態の半導体チップ１２及び該半導体チップ１２を備える半導体モジュール１０によれば、保護膜１２５によって半導体チップ１２の反りを低減しつつ、はんだ２０における表面電極１２１上の部分にボイドが生じるのを抑制することができる。 As described above, according to the semiconductor chip 12 of the present embodiment and the semiconductor module 10 including the semiconductor chip 12, voids are formed on the portion of the solder 20 on the surface electrode 121 while reducing the warp of the semiconductor chip 12 by the protective film 125. It can be suppressed from occurring.
　また、本実施形態では、第１分離部１２７及び第２分離部１２８が周囲部１２６に対して離れて設けられており、第１分離部１２７及び第２分離部１２８と周囲部１２６との間に外周連結部１２１ｄ，１２１ｅが設けられている。これにより、熱応力が集中しやすい表面電極１２１の外周端付近において、はんだ２０との接続面積を稼ぐことができる。すなわち、表面電極１２１に対するはんだ２０の接続信頼性を向上することもできる。 Further, in the present embodiment, the first separation unit 127 and the second separation unit 128 are provided apart from the peripheral portion 126, and the first separation unit 127 and the second separation unit 128 are disposed between the peripheral portion 126. Are provided with outer peripheral connecting portions 121d and 121e. Thereby, the connection area with the solder 20 can be earned in the vicinity of the outer peripheral end of the surface electrode 121 where thermal stress tends to concentrate. That is, the connection reliability of the solder 20 to the surface electrode 121 can be improved.
　なお、第１分離部１２７及び第２分離部１２８の数は上記例に限定されない。たとえば、１つの第１分離部１２７と２つの第２分離部１２８を有する構成としてもよい。 In addition, the number of the 1st separation part 127 and the 2nd separation part 128 is not limited to the said example. For example, a configuration having one first separation unit 127 and two second separation units 128 may be employed.
　本開示は、実施形態に準拠して記述されたが、本開示は当該実施形態や構造に限定されるものではないと理解される。本開示は、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらに一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本開示の範疇や思想範囲に入るものである。 Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or the structure. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.
　先行実施形態を組み合わせた構成としてもよい。たとえば図１９に示す半導体チップ１２は、第２実施形態と第３実施形態を組み合わせた構成とされている。第１分離部１２７及び第２分離部１２８は、交差部を有さず、且つ、周囲部１２６に連ならないように設けられている。表面電極１２１は、第２連結部１２１ｃと外周連結部１２１ｄ，１２１ｅを有している。なお、第１実施形態と第３実施形態を組み合わせ、表面電極１２１が、第１連結部１２１ｂと外周連結部１２１ｄ，１２１ｅを有する構成としてもよい。 It is good also as a structure which combined previous embodiment. For example, the semiconductor chip 12 shown in FIG. 19 is configured by combining the second embodiment and the third embodiment. The first separation unit 127 and the second separation unit 128 do not have an intersecting portion and are provided so as not to be connected to the peripheral portion 126. The surface electrode 121 has the 2nd connection part 121c and the outer periphery connection parts 121d and 121e. In addition, it is good also as a structure which the surface electrode 121 has the 1st connection part 121b and the outer periphery connection parts 121d and 121e combining the 1st Embodiment and 3rd Embodiment.
　第１実施形態及び第２実施形態において、第１分離部１２７と第２分離部１２８との交差部が無い例を示した。しかしながら、中心１２１ａに近いほど、周りから水蒸気が集まりやすい。そこで、中心１２１ａ近傍のみ交差しないようにし、中心１２１ａから離れた位置では交差するようにしてもよい。 In the first embodiment and the second embodiment, an example in which there is no intersection between the first separation unit 127 and the second separation unit 128 is shown. However, the closer to the center 121a, the easier it is for water vapor to collect from the surroundings. Therefore, it may be configured such that only the vicinity of the center 121a does not intersect and intersects at a position away from the center 121a.
　第１分離部１２７と第２分離部１２８との対向領域に、金属薄膜であるＮｉ膜１２３及びＡｕ膜１２４が配置されて第１連結部１２１ｂが形成される例を示した。同じく、第１分離部１２７間の対向領域及び第２分離部１２８間の対向領域に、第２連結部１２１ｃが形成される例を示した。また、第１分離部１２７と第２分離部１２８と周囲部１２６との対向領域に、外周連結部１２１ｄ，１２１ｅが形成される例を示した。しかしながら、上記した対向領域に、金属薄膜が配置されず、下地膜１２２が露出する構成としてもよい。 An example is shown in which the first connecting portion 121b is formed by disposing the Ni film 123 and the Au film 124, which are metal thin films, in the facing region between the first separation portion 127 and the second separation portion 128. Similarly, the example in which the second connecting portion 121c is formed in the facing region between the first separation portions 127 and the facing region between the second separation portions 128 has been shown. Moreover, the example in which the outer periphery connection parts 121d and 121e were formed in the opposing area | region of the 1st separation part 127, the 2nd separation part 128, and the surrounding part 126 was shown. However, a configuration in which the metal thin film is not disposed in the facing region and the base film 122 is exposed may be employed.
　半導体モジュール１０として、半導体チップ１２をひとつ備える１ｉｎ１パッケージの例を示したが、これに限定されるものではない。半導体チップ１２を２つ備え、一相分の上下アームを構成する２ｉｎ１パッケージ、６つの半導体チップ１２を備え、三相分の上下アームを構成する６ｉｎ１パッケージなどにも適用できる。 Although an example of a 1 in 1 package including one semiconductor chip 12 is shown as the semiconductor module 10, it is not limited to this. The present invention can also be applied to a 2-in-1 package that includes two semiconductor chips 12 and constitutes an upper and lower arm for one phase, and a 6-in1 package that includes six semiconductor chips 12 and constitutes an upper- and lower-arm for three phases.
　半導体モジュール１０が封止樹脂体１４を備える例を示したが、封止樹脂体１４を備えない構成にも適用できる。 Although the example in which the semiconductor module 10 includes the sealing resin body 14 has been shown, the present invention can also be applied to a configuration that does not include the sealing resin body 14.
　各ヒートシンク２６，３２の放熱面２６ａ，３２ａが、封止樹脂体１４から露出される例を示したが、封止樹脂体１４から露出されない構成にも適用できる。 Although the example in which the heat radiating surfaces 26a and 32a of the heat sinks 26 and 32 are exposed from the sealing resin body 14 is shown, the present invention can be applied to a configuration in which the heat sinks 26 and 32 are not exposed from the sealing resin body 14.
　半導体モジュール１０が、ターミナル２２を備える例を示したがこれに限定されない。ターミナル２２を備えず、ヒートシンク２６が、はんだを介して半導体チップ１２の表面電極１２１に接続される構成を採用することもできる。 Although an example in which the semiconductor module 10 includes the terminal 22 has been shown, the present invention is not limited to this. A configuration in which the terminal 22 is not provided and the heat sink 26 is connected to the surface electrode 121 of the semiconductor chip 12 via solder may be employed.

Claims (9)

  1. 　表面（１２０ａ）及び該表面と板厚方向に反対の裏面（１２０ｂ）を有し、素子が形成された半導体基板（１２０）と、
    　前記表面上に設けられ、はんだ付けされる表面電極（１２１）と、
    　前記表面上において前記表面電極を取り囲むように設けられた周囲部（１２６）と、前記周囲部により囲まれる領域内において前記板厚方向に直交する行方向に延設され、前記板厚方向及び前記行方向に直交する列方向において前記表面電極を区切る第１分離部（１２７）と、前記領域内において前記列方向に延設され、前記行方向において前記表面電極を区切る第２分離部（１２８）と、を有し、吸湿性材料を用いて形成された保護膜（１２５）と、
    　前記裏面に設けられた裏面電極（１３０）と、を備え、
    　前記第１分離部及び前記第２分離部が、交差しないように互いに離れて設けられている半導体装置。     A semiconductor substrate (120) having a front surface (120a) and a back surface (120b) opposite to the front surface in the thickness direction, on which an element is formed;
    A surface electrode (121) provided on the surface and soldered;
    A peripheral portion (126) provided on the surface so as to surround the surface electrode, and extending in a row direction orthogonal to the plate thickness direction in a region surrounded by the peripheral portion, A first separation portion (127) that divides the surface electrode in a column direction orthogonal to the row direction, and a second separation portion (128) that extends in the column direction within the region and divides the surface electrode in the row direction. And a protective film (125) formed using a hygroscopic material,
    A back electrode (130) provided on the back surface,
    A semiconductor device in which the first separation portion and the second separation portion are provided apart from each other so as not to cross each other.
  2. 　前記第１分離部と前記第２分離部が交差しないように、前記第１分離部及び前記第２分離部の少なくとも一方が、延設方向において複数に分割されている請求項１に記載の半導体装置。 2. The semiconductor according to claim 1, wherein at least one of the first separation part and the second separation part is divided into a plurality in the extending direction so that the first separation part and the second separation part do not intersect. apparatus.
  3. 　前記第１分離部及び前記第２分離部のうち、両端間の長さが長いほうが複数に分割されている請求項２に記載の半導体装置。 3. The semiconductor device according to claim 2, wherein, of the first separation unit and the second separation unit, the longer one between both ends is divided into a plurality of portions.
  4. 　前記第１分離部及び前記第２分離部の両方が、それぞれの延設方向において複数に分割されるとともに、同じ位置で分割されている請求項２又は請求項３に記載の半導体装置。 4. The semiconductor device according to claim 2, wherein both of the first separation unit and the second separation unit are divided into a plurality of portions in the respective extending directions and are divided at the same position.
  5. 　前記行方向において、前記第１分離部の両端が前記周囲部に連なり、
    　前記列方向において、前記第２分離部の両端が前記周囲部に連なっている請求項１～４いずれか１項に記載の半導体装置。     In the row direction, both ends of the first separation part are connected to the peripheral part,
    The semiconductor device according to any one of claims 1 to 4, wherein both ends of the second separation portion are connected to the peripheral portion in the column direction.
  6. 　前記第１分離部及び前記第２分離部が、前記周囲部に連ならないように前記周囲部に対して離れて設けられている請求項１～４いずれか１項に記載の半導体装置。 5. The semiconductor device according to claim 1, wherein the first separation portion and the second separation portion are provided apart from the peripheral portion so as not to be connected to the peripheral portion.
  7. 　表面（１２０ａ）及び該表面と板厚方向に反対の裏面（１２０ｂ）を有し、素子が形成された半導体基板（１２０）と、
    　前記表面上に設けられ、はんだ付けされる表面電極（１２１）と、
    　前記表面上において前記表面電極の周囲に設けられた周囲部（１２６）と、前記周囲部により囲まれる領域内において前記板厚方向に直交する行方向に延設され、前記板厚方向及び前記行方向に直交する列方向において前記表面電極を区切る第１分離部（１２７）と、前記領域内において前記列方向に延設され、前記行方向において前記表面電極を区切る第２分離部（１２８）と、前記第１分離部と前記第２分離部との交差部分である交差部（１３１）と、を有し、吸湿性材料を用いて形成された保護膜（１２５）と、
    　前記裏面に設けられた裏面電極（１３０）と、を備え、
    　前記第１分離部及び前記第２分離部が、前記周囲部に連ならないように前記周囲部に対して離れて設けられている半導体装置。     A semiconductor substrate (120) having a front surface (120a) and a back surface (120b) opposite to the front surface in the thickness direction, on which an element is formed;
    A surface electrode (121) provided on the surface and soldered;
    A peripheral portion (126) provided around the surface electrode on the surface, and extending in a row direction perpendicular to the plate thickness direction in a region surrounded by the peripheral portion, the plate thickness direction and the row A first separation portion (127) that divides the surface electrode in a column direction orthogonal to the direction, and a second separation portion (128) that extends in the column direction within the region and divides the surface electrode in the row direction. A protective film (125) formed using a hygroscopic material, and an intersection (131) that is an intersection of the first separation part and the second separation part,
    A back electrode (130) provided on the back surface,
    The semiconductor device, wherein the first separation portion and the second separation portion are provided apart from the peripheral portion so as not to be connected to the peripheral portion.
  8. 　前記表面電極は、複数の薄膜を積層して形成され、
    　前記保護膜により、前記薄膜のうちの最も剛性の大きい膜（１２３）が区切られている請求項１～７いずれか１項に記載の半導体装置。     The surface electrode is formed by laminating a plurality of thin films,
    The semiconductor device according to any one of claims 1 to 7, wherein a film (123) having the highest rigidity among the thin films is partitioned by the protective film.
  9. 　前記表面電極側に凹の反りが生じている請求項１～８いずれか１項に記載の半導体装置。

          9. The semiconductor device according to claim 1, wherein a concave warp is generated on the surface electrode side.

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03184396A (en) * 1989-12-13 1991-08-12 Fujitsu Ltd Structure for preventing swelling of polyimide layer on multi-layer wiring board
JP2000183108A (en) * 1998-12-18 2000-06-30 Nec Corp Semiconductor integrated circuit device and its manufacture
JP2005116962A (en) * 2003-10-10 2005-04-28 Denso Corp Package type semiconductor device
JP2011066377A (en) * 2009-08-18 2011-03-31 Denso Corp Semiconductor device and method of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03184396A (en) * 1989-12-13 1991-08-12 Fujitsu Ltd Structure for preventing swelling of polyimide layer on multi-layer wiring board
JP2000183108A (en) * 1998-12-18 2000-06-30 Nec Corp Semiconductor integrated circuit device and its manufacture
JP2005116962A (en) * 2003-10-10 2005-04-28 Denso Corp Package type semiconductor device
JP2011066377A (en) * 2009-08-18 2011-03-31 Denso Corp Semiconductor device and method of manufacturing the same

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