JPH03184396A - Structure for preventing swelling of polyimide layer on multi-layer wiring board - Google Patents

Structure for preventing swelling of polyimide layer on multi-layer wiring board

Info

Publication number
JPH03184396A
JPH03184396A JP32302689A JP32302689A JPH03184396A JP H03184396 A JPH03184396 A JP H03184396A JP 32302689 A JP32302689 A JP 32302689A JP 32302689 A JP32302689 A JP 32302689A JP H03184396 A JPH03184396 A JP H03184396A
Authority
JP
Japan
Prior art keywords
conductor pattern
conductor
polyimide layer
hole
polyimide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP32302689A
Other languages
Japanese (ja)
Other versions
JPH0795629B2 (en
Inventor
Toshio Matsuzaki
松崎 壽夫
Hiroaki Toshima
博彰 戸島
Takashi Otsuka
孝 大塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP32302689A priority Critical patent/JPH0795629B2/en
Publication of JPH03184396A publication Critical patent/JPH03184396A/en
Publication of JPH0795629B2 publication Critical patent/JPH0795629B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To prevent a polyimide layer from being swollen by forming a second conductor pattern on the polyimide layer, connected to a first conductor pattern through the side walls of through holes, and providing opening parts in the through holes for exposing part of the first conductor pattern. CONSTITUTION:An insulating substrate 22 including therein through holes 23 at predetermined portions thereof is formed, and conductor paste is printed and baked by printing means to form a first conductor pattern 25 and a third conductor pattern 30. Then, a photosensitive polyimide solution is deposited by spin-coating and the like and the polyimide solution is pre-baked to form polyimide films 33, 34. Further, transparent holes 27, 31 are provided and the polyimide films 33, 34 are cured to form polyimide layers 26, 32. Thereafter, conductor thin films 35, 36 are deposited on the surface and back of the board and unnecessary portions of the conductor thin films 35, 36 are removed to form a second conductor pattern 2a having therein an opening 37 and a fourth conductor pattern 33 having therein an opening 38.

Description

【発明の詳細な説明】 〔概要〕 高集積化ハイブリッドIC等に使用され、層間絶縁層に
ポリイミドを使用した多層配線基板に関し、 該ポリイミド層が製造過程で膨らむことがないようにす
ることを目的とし、 透孔内に導体が埋設されたバイアホールを有する絶縁基
板と、 該絶縁基板上に該導体と同時に形威された第1の導体パ
ターンと、 該第1の導体パターンを被覆し少なくとも該導体の真上
で該第1の導体パターンのそれぞれに直通する透孔を有
するポリイミド層を具え、該ポリイミド層の上に形成し
該透孔の側面を通って該第1の導体パターンに接続され
る第2の導体パターンには、該透孔内に該第1の導体パ
ターンの一部を表呈させる開口部を設けてなることを特
徴とするまたは、 透孔内に導体が埋設されたバイアホールを有する絶縁基
板、該絶縁基板の表面には少なくとも第1の導体パター
ン、該第1の導体パターンの所要部に連通ずる透孔を有
する第1のポリイミド層。
[Detailed Description of the Invention] [Summary] The purpose of this invention is to prevent the polyimide layer from swelling during the manufacturing process in a multilayer wiring board that is used in highly integrated hybrid ICs and uses polyimide as an interlayer insulating layer. an insulating substrate having a via hole in which a conductor is embedded; a first conductive pattern formed on the insulating substrate at the same time as the conductor; A polyimide layer having a through hole directly above the conductor and directly connected to each of the first conductor patterns, formed on the polyimide layer and connected to the first conductor pattern through the side surface of the through hole. The second conductor pattern has an opening in the through hole that exposes a part of the first conductor pattern, or a via in which a conductor is buried in the through hole. An insulating substrate having a hole, at least a first conductor pattern on the surface of the insulating substrate, and a first polyimide layer having a through hole communicating with a desired portion of the first conductor pattern.

該第1のポリイミド層の透孔にて該第1の導体パターン
に連通ずる第2の導体パターン、該第2の導体パターン
の所要部を表呈せしめる第2のポリイミド層が設けられ
、該絶縁基板の裏面には少なくとも第3の導体パターン
、該第3の導体パターンの所要部に連通ずる透孔を有す
る第3のポリイミド層、該第3のポリイミド層の透孔に
て該第3の導体パターンに連通ずる第4の導体パターン
が設けられ、 該第3のポリイミド層形成後に形威された該第4の導体
パターンが、該第3の導体パターンと対向しない箇所に
透孔のあけられた導体薄膜から形威されてなることを特
徴とし構成する。
A second conductor pattern communicating with the first conductor pattern through the through hole of the first polyimide layer, a second polyimide layer exposing a required portion of the second conductor pattern, and At least a third conductive pattern is provided on the back surface of the substrate, a third polyimide layer having a through hole communicating with a required portion of the third conductive pattern, and a third conductor formed through the through hole of the third polyimide layer. A fourth conductive pattern communicating with the pattern is provided, and the fourth conductive pattern formed after forming the third polyimide layer has a through hole in a location not facing the third conductive pattern. It is characterized by being formed from a conductive thin film.

〔産業上の利用分野〕[Industrial application field]

本発明は、高集積化ハイブリッドIC等に使用される多
層配線基板、特に眉間絶縁層として形威されたポリイミ
ド層の膨らみ防止構造に関する。
The present invention relates to a multilayer wiring board used for highly integrated hybrid ICs and the like, and in particular to a structure for preventing swelling of a polyimide layer formed as an insulating layer between the eyebrows.

〔従来の技術〕[Conventional technology]

第6図は従来技術による多層配線基板の要部の断面図で
ある。
FIG. 6 is a sectional view of a main part of a multilayer wiring board according to the prior art.

第6図において多層配線基板1は、透孔3に導体4を埋
設してなるバイアホールが形成された絶縁基板(セラミ
ック基板)2の表面に第1の導体パターン5.所要部に
おいて第1の導体パターン5が表呈する透孔7を有する
ポリイミド層6.透孔7内で第1の導体パターン5に接
続された第2の導体パターン8が形成され、絶縁基板2
の裏面に第3の導体パターン9.所要部において第3の
導体パターン9が表呈する透孔10を有するポリイミド
層11.透孔10内で第3の導体パターン9に接続され
た第4の導体パターン12が形威されてなる。
In FIG. 6, a multilayer wiring board 1 has a first conductor pattern 5. A polyimide layer 6 having through holes 7 through which the first conductor pattern 5 is exposed at required portions. A second conductor pattern 8 connected to the first conductor pattern 5 is formed within the through hole 7, and the insulating substrate 2
A third conductor pattern 9. A polyimide layer 11 having through holes 10 through which third conductive patterns 9 are exposed at required portions. A fourth conductive pattern 12 connected to the third conductive pattern 9 is formed within the through hole 10.

かかる多層配線基板1において、導体パターン5.9が
印刷にて形威されるとき、導体4と導体パターン5.9
は導体ペースト(例えばAg Pdペースト)を使用し
同時に形威されるが、導体パターン5.9が導体薄膜よ
り形威されるとき導体ペースト(例えばCuペースト)
を使用する導体4は、クリーンシート時の透孔4に導体
ペーストを充填せしめ、基板1と同時に焼成される。
In such a multilayer wiring board 1, when the conductor pattern 5.9 is printed, the conductor 4 and the conductor pattern 5.9
is simultaneously formed using a conductor paste (e.g. Ag Pd paste), but when the conductor pattern 5.9 is formed from a conductor thin film, a conductor paste (e.g. Cu paste) is used.
The conductor 4 to be used is prepared by filling the through holes 4 of the clean sheet with conductor paste and firing at the same time as the substrate 1.

一般に2層構成することで厚さ20μm程度であるポリ
イミド層6,11は、300’C程度乃至それ以上の温
度で焼成されることになる。
The polyimide layers 6 and 11, which are generally two-layered and have a thickness of about 20 μm, are fired at a temperature of about 300'C or more.

かかる多層配線基板1の製造過程において、第6図に一
点鎖線で示す如きポリイミド層13を形威し、導体パタ
ーン5を介して導体4の導通テストを能率的に行うには
、図中に破線で示す如く導体パターンを形成する前の導
体膜14を利用することが行われている。
In the process of manufacturing such a multilayer wiring board 1, in order to form the polyimide layer 13 as shown by the dashed line in FIG. As shown in FIG. 1, a conductor film 14 before forming a conductor pattern is used.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

第7図は従来の多層配線基板におけるポリイミド層の膨
らみの説明図である。
FIG. 7 is an explanatory diagram of a bulge in a polyimide layer in a conventional multilayer wiring board.

第7図(イ)は導体パターン5,9が印刷にて形成され
た場合であり、基板2の表面と裏面に形成した導体パタ
ーン5,9の印刷時に、透孔3に充填された導体4には
図示する如き空洞15ができ易く、ポリイくド層6の形
成に先立つ洗浄の残滓が空洞15に取り込まれると、該
残滓がポリイミド層6の焼成時にガス化し、ポリイミド
層6の一部に膨らみ16ができ易いという欠点があった
FIG. 7(A) shows a case where the conductor patterns 5 and 9 are formed by printing, and when the conductor patterns 5 and 9 formed on the front and back surfaces of the substrate 2 are printed, the conductor 4 is filled in the through hole 3. A cavity 15 as shown in the figure is likely to be formed, and when the residue of cleaning prior to the formation of the polyimide layer 6 is taken into the cavity 15, the residue is gasified during the firing of the polyimide layer 6 and becomes a part of the polyimide layer 6. There was a drawback that a bulge 16 was easily formed.

第7図(II+)は導体パターン5,9が薄膜より形成
された場合であり、導体パターン12の形成に先立って
、導体パターン12を形成させる導体膜16と導体パタ
ーン8との導通(バイアホール)チエツクを使用とする
と、ポリイミド層13の焼成時にポリイミド層11より
発生したガスおよび水蒸気によって、ポリイミド111
に膨らみ17ができ易いという欠点があった。
FIG. 7 (II+) shows a case where the conductor patterns 5 and 9 are formed of thin films, and prior to forming the conductor pattern 12, the conductor film 16 on which the conductor pattern 12 is formed and the conductor pattern 8 are electrically connected (via holes). ) check is used, gas and water vapor generated from the polyimide layer 11 during firing of the polyimide layer 13 cause the polyimide 111 to
There was a drawback that a bulge 17 was easily formed.

本発明の目的は、膨らみ16および17ができないよう
にすることである。
The purpose of the invention is to prevent bulges 16 and 17 from forming.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の第1の手段はその実施例を示す第1図によれば
、透孔23内に導体24が埋設されたバイアホールを有
する絶縁基板22と、 絶縁基板22上に導体24と同時に形成された第1の導
体パターン25と、 第1の導体パターン25を被覆し少なくとも導体24の
真上で第1の導体パターン25のそれぞれに直通する透
孔27を有するポリイミド層26を具え、ポリイミド層
26の上に形成し透孔27の側面を通って第1の導体パ
ターン25に接続される第2の導体パターン29には、
透孔27内に第1の導体パターン25の一部を表呈させ
る開口部を設けてなることを特徴とする多層配線基板2
1である。
According to FIG. 1 showing an embodiment of the present invention, the first means of the present invention includes an insulating substrate 22 having a via hole in which a conductor 24 is embedded in a through hole 23, and a conductor 24 formed on the insulating substrate 22 at the same time. a polyimide layer 26 covering the first conductor pattern 25 and having through holes 27 directly above the conductor 24 and directly communicating with each of the first conductor patterns 25; The second conductor pattern 29 formed on the through hole 26 and connected to the first conductor pattern 25 through the side surface of the through hole 27 includes:
A multilayer wiring board 2 characterized in that an opening for exposing a part of a first conductor pattern 25 is provided in a through hole 27.
It is 1.

本発明の第2の手段はその実施例を示す第2図によれば
、透孔43内に導体44が埋設されたバイアホールを有
する絶縁基板42、絶縁基板42の表面には少なくとも
第1の導体パターン45.第1の導体パターン45の所
要部に連通ずる透孔47を有する第1のポリイミド層4
6.第1のポリイミド層46の透孔47にて第1の導体
パターン45に連通ずる第2の導体パターン48.第2
の導体パターン48の所要部を表呈せしめる第2のポリ
イミド層49が設けられ、絶縁基板42の裏面には少な
くとも第3の導体パターン50.第3の導体パターン5
0の所要部に連通ずる透孔52を有する第3のポリイミ
ド層51.第3のポリイミド層51の透孔52にて第3
の導体パターン50に連通ずる第4の導体パターン53
が設けられ、第3のポリイミド層51形戒後に形成され
た第4の導体パターン53が、第3の導体パターン50
と対向しない箇所に透孔55のあけられた導体薄膜54
から形成されてなることを特徴とする多層配線基板41
である。
According to FIG. 2 showing an embodiment of the second means of the present invention, an insulating substrate 42 has a via hole in which a conductor 44 is embedded in a through hole 43, and at least a first Conductor pattern 45. A first polyimide layer 4 having through holes 47 communicating with required parts of the first conductor pattern 45
6. A second conductor pattern 48 . communicates with the first conductor pattern 45 through a hole 47 in the first polyimide layer 46 . Second
A second polyimide layer 49 is provided to expose the required portions of the conductor pattern 50 .On the back surface of the insulating substrate 42 , at least a third conductor pattern 50 . Third conductor pattern 5
A third polyimide layer 51. At the through hole 52 of the third polyimide layer 51, the third
A fourth conductive pattern 53 communicating with the conductive pattern 50 of
is provided, and the fourth conductor pattern 53 formed after the third polyimide layer 51 is connected to the third conductor pattern 50.
A conductive thin film 54 having a through hole 55 in a location not facing the conductor thin film 54.
A multilayer wiring board 41 characterized in that it is formed from
It is.

〔作用〕[Effect]

上記第1の手段によれば、絶縁基板のバイアホール導体
に空洞ができ、該空洞内に洗浄液残滓等が取り残されけ
も、該残滓等のガス、水蒸気は該導体に直通するポリイ
くド層の透孔、第2の導体パターンに設けた開口部より
排除されるため、ポリイミド層に膨らみができないよう
になる。
According to the first means, even if a cavity is formed in the via-hole conductor of the insulating substrate and cleaning liquid residue is left behind in the cavity, gas and water vapor such as the residue are removed from the polyimide layer that directly communicates with the conductor. Since the polyimide layer is removed from the through hole and the opening provided in the second conductor pattern, no bulge is formed in the polyimide layer.

また、上記第2の手段によれば、第3のポリイミド層の
焼成に際して第2のポリイミド層より発生するガス、水
蒸気は、導体薄膜に設けられた透孔より排除され、第2
のポリイミド層に膨らみができないようになる。
Further, according to the second means, gas and water vapor generated from the second polyimide layer during firing of the third polyimide layer are removed through the through holes provided in the conductive thin film, and
This prevents bulges from forming in the polyimide layer.

〔実施例〕〔Example〕

以下に、図面を用いて本発明によるポリイミド層の膨ら
み防止構造を有する多層配線基板について説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A multilayer wiring board having a polyimide layer bulge prevention structure according to the present invention will be described below with reference to the drawings.

第1図は本発明の第1の実施例による多層配線基板の要
部を示す断面図、第2図は本発明の第2の実施例による
多層配線基板の要部を示す断面図、第3図は第1図に示
す多層配線基板の主要工程図、第4図は第2図に示す多
層配線基板の主要工程図、第5図は第4図に示す第5の
導体薄膜の平面図である。
FIG. 1 is a sectional view showing the main parts of a multilayer wiring board according to the first embodiment of the present invention, FIG. 2 is a sectional view showing the main parts of the multilayer wiring board according to the second embodiment of the invention, and FIG. The figure is a main process diagram of the multilayer wiring board shown in Fig. 1, Fig. 4 is a main process diagram of the multilayer wiring board shown in Fig. 2, and Fig. 5 is a plan view of the fifth conductive thin film shown in Fig. 4. be.

第1図において多層配線基板21は、透孔23に導体2
4を埋設してなるバイアホールが形成された絶縁基板(
セラ稟ツタ基板)22の表面に、印刷による第1の導体
パターン25.少なくとも各導体24の真上で第1の導
体パターン25に直通する透孔27を有するポリイミド
層26.所要部において透孔27の側面を通り第1の導
体パターン25に接続されるように薄膜より形成された
第2の導体パターン29が形成されてなる。
In FIG. 1, the multilayer wiring board 21 has a conductor 2 in the through hole 23.
An insulating substrate with a via hole formed by burying 4 (
A printed first conductor pattern 25. A polyimide layer 26 having through holes 27 directly above each conductor 24 and communicating directly with the first conductor pattern 25 . A second conductor pattern 29 made of a thin film is formed so as to pass through the side surface of the through hole 27 and be connected to the first conductor pattern 25 at a required portion.

導体ペーストを透孔23に充填し形成される導体24は
、第1の導体パターン25と同一工程で印刷・焼威し形
成される。
The conductor 24, which is formed by filling the through hole 23 with conductor paste, is formed by printing and burning in the same process as the first conductor pattern 25.

第2の導体パターン2つには、透孔27の側面を通り第
1の導体パターン25に接続された部分で、透孔27内
に第1の導体パターン25の一部を表呈させる開口部3
7が形成される。
The two second conductor patterns have an opening that passes through the side surface of the through hole 27 and is connected to the first conductor pattern 25, exposing a part of the first conductor pattern 25 inside the through hole 27. 3
7 is formed.

そして絶縁基板22の裏面には、印刷による第3の導体
パターン30.少なくとも各導体24に直通する透孔3
1を有するポリイミド層32.所要部において透孔31
の側面を通り第3の導体パターン30に接続された第4
の導体パターン33が形成されてなる。
A third conductive pattern 30 is printed on the back surface of the insulating substrate 22. Through hole 3 that communicates directly with at least each conductor 24
1. Polyimide layer 32. Through holes 31 in required parts
The fourth conductor pattern 30 is connected to the third conductor pattern 30 through the side surface of the conductor pattern 30.
A conductor pattern 33 is formed.

第4の導体パターン33には、透孔31の側面を通り第
3の導体パターン30に接続された部分で、透孔31内
に第3の導体パターン30の一部を表呈させる開口部3
8が形成される。
The fourth conductor pattern 33 has an opening 3 that passes through the side surface of the through hole 31 and is connected to the third conductor pattern 30, exposing a part of the third conductor pattern 30 inside the through hole 31.
8 is formed.

このように構成された多層配線基板21は、導体24内
に第7図に示す如き空洞15ができることがあっても、
空洞15より発生するガスおよび水蒸気は、透孔27.
31または開口部37.38を通って排出されるため、
ポリイミド層26.32に、第7図に示す如き膨らみ1
6ができないようになる。
In the multilayer wiring board 21 configured in this way, even if a cavity 15 as shown in FIG. 7 is formed in the conductor 24,
Gas and water vapor generated from the cavity 15 are passed through the through holes 27.
31 or through openings 37.38,
The polyimide layer 26.32 has a bulge 1 as shown in FIG.
I can no longer do 6.

以下、第3図を用いて多層配線基板21の主要製造工程
を説明する。
Hereinafter, the main manufacturing steps of the multilayer wiring board 21 will be explained using FIG. 3.

第3図(イ)において、所定部に透孔23のあいた絶縁
基板22を作成する。
In FIG. 3(A), an insulating substrate 22 having through holes 23 in predetermined portions is prepared.

第3図(II+)において、印刷手段によって導体ペー
ストを印刷焼成し導体24.第1の導体パターン25、
第3の導体パターン30を形成させる。
In FIG. 3 (II+), a conductor paste is printed and fired by a printing means to form a conductor 24. first conductor pattern 25,
A third conductor pattern 30 is formed.

第3図(ハ)において、スピンコード等によって感光性
ポリイミド液を被着せしめ、そのポリイミド液を例えば
130’Cで30分プリベーク処理してポリイミド膜3
3.34を形成させる。
In FIG. 3(C), a photosensitive polyimide liquid is applied using a spin cord or the like, and the polyimide liquid is prebaked at, for example, 130'C for 30 minutes to form a polyimide film 3.
3.34 is formed.

次いで第3図(ニ)に示す如く、透孔27.31を設け
てからキュア処理し、ポリイミド層26,32を形成さ
せる。
Next, as shown in FIG. 3(d), through holes 27 and 31 are formed and then cured to form polyimide layers 26 and 32.

しかるのち、第3図0)に示す如く表面と裏面に導体薄
膜35.36を被着し、導体薄膜35.36の不要部を
除去して、第3図(へ)に示す如く開口部37を有する
第2の導体パターン29と、開口部38を有する第4の
導体パターン33が形成される。
Thereafter, conductive thin films 35 and 36 are deposited on the front and back surfaces as shown in FIG. A second conductor pattern 29 having an opening 38 and a fourth conductor pattern 33 having an opening 38 are formed.

次頁の表は、多層配線基板21について調査した不良発
生率と、従来技術による不良発生率とを比較させたもの
である。ただし、本発明および従来技術による試料にお
いて、印刷用導体ペーストにはAg Pdペーストを使
用し、ポリイミド層は130度で30分プリベーク処理
したのち300度30分。
The table on the next page compares the failure rate investigated for the multilayer wiring board 21 with the failure rate according to the prior art. However, in the samples according to the present invention and the prior art, Ag Pd paste was used as the printing conductor paste, and the polyimide layer was prebaked at 130 degrees for 30 minutes and then at 300 degrees for 30 minutes.

400度30分のキュア処理を施し、ポリイミド層の上
に被着した導体パターン形成用薄膜はクロームと銅の2
層構成とし、さらに多層配線基板21のポリイミド層に
形成させた透孔27は直径0.2mn+である。
After curing at 400 degrees for 30 minutes, the conductive pattern forming thin film deposited on the polyimide layer is made of two layers: chrome and copper.
In addition to the layered structure, the through hole 27 formed in the polyimide layer of the multilayer wiring board 21 has a diameter of 0.2 mm+.

上記表において、ポリイミドキュア後、熱衝撃試験後は
前工程の良品を対象として実施し、熱衝撃試験は一55
度〜125度の温度サイクルを1000回行ったもので
ある。
In the above table, after polyimide curing and thermal shock test, the test was conducted on good products from the previous process, and the thermal shock test
A temperature cycle of 1000 degrees to 125 degrees was performed.

そして、本発明構成の試料については、さらに、−55
度〜125度の温度サイクルを1000回追加したが、
その後の不良率も0%であった。
And, for the sample configured according to the present invention, -55
I added 1000 temperature cycles from ℃ to 125℃,
The defective rate thereafter was also 0%.

第2図において多層配線基板41は、透孔43に導体4
4を埋設してなるバイアホールが形成された絶縁基板(
セラ壽フク基板)42の表面に、薄膜にてなる第1の導
体パターン45.第1の導体パターン45の所定部を表
呈せしめる透孔47を有する第1のポリイミド層46.
透孔47内で第1の導体パターン45に接続されるよう
に薄膜よりなる第2の導体パターン48.第2の導体パ
ターン48の所定部を表呈せしめる第2のポリイミド層
49が形成されてなる。
In FIG. 2, the multilayer wiring board 41 has a conductor 4 in the through hole 43.
An insulating substrate with a via hole formed by burying 4 (
A first conductor pattern 45 made of a thin film is formed on the surface of the ceramic substrate 42. A first polyimide layer 46 having a through hole 47 exposing a predetermined portion of the first conductor pattern 45.
A second conductor pattern 48 made of a thin film is connected to the first conductor pattern 45 within the through hole 47 . A second polyimide layer 49 is formed to expose a predetermined portion of the second conductive pattern 48.

導体44は焼成前の絶縁基板42にあけられた透孔43
に導体ペーストを充填し、絶縁基板42と共に焼威し形
成される。
The conductor 44 is a through hole 43 made in the insulating substrate 42 before firing.
is filled with a conductive paste and fired together with the insulating substrate 42.

そして絶縁基板42の裏面には、薄膜にてなる第3の導
体パターン50.第3の導体パターン50の所定部を表
呈せしめる透孔52を有する第3のボリイごド層51.
透孔52内で第3の導体パターン50に接続された第4
の導体パターン53が形成されてなる。
A third conductive pattern 50 made of a thin film is formed on the back surface of the insulating substrate 42. A third solid iron layer 51 having a through hole 52 exposing a predetermined portion of the third conductor pattern 50.
A fourth conductor pattern connected to the third conductor pattern 50 within the through hole 52
A conductor pattern 53 is formed.

第4の導体パターン53を形成する前の導体薄膜(図中
に破線で示す薄膜)54には、第5図に示す如く多数の
例えば直径200μm程度の透孔55が、第4の導体パ
ターン53の形成を損なうことなく、かつ、第3の導体
パターン50と対向しない箇所に設けられる。
As shown in FIG. 5, a large number of through holes 55 with a diameter of about 200 μm, for example, are formed in the conductor thin film 54 (thin film indicated by broken lines in the figure) before the fourth conductor pattern 53 is formed. The third conductor pattern 50 is provided without impairing the formation of the third conductor pattern 50 and at a location not facing the third conductor pattern 50.

第4の導体パターン53は、ポリイミド層49を形成し
、導体薄膜54と各第2の導体パターン48との導通テ
ストが終了したのち、導体薄膜54の不要部を除去して
形成されるようになる。
The fourth conductive pattern 53 is formed by forming the polyimide layer 49 and removing unnecessary parts of the conductive thin film 54 after completing a continuity test between the conductive thin film 54 and each second conductive pattern 48. Become.

このように構成された多層配線基板41は、ポリイミド
N49の焼成に際し、導体薄膜54の被着されたポリイ
ミド層51からガスおよび水蒸気が発生してもそれらは
透孔55より排除され、ポリイミド層51には第7図に
示す如き膨らみ17ができないようになる。
In the multilayer wiring board 41 configured in this manner, even if gas and water vapor are generated from the polyimide layer 51 to which the conductive thin film 54 is applied during firing of the polyimide N49, they are removed through the through holes 55, and the polyimide layer 51 A bulge 17 as shown in FIG. 7 will no longer be formed.

以下、第4図を用いて多層配線基板41の主要製造工程
を説明する。
Hereinafter, the main manufacturing steps of the multilayer wiring board 41 will be explained using FIG. 4.

第4図(イ)において、透孔43に導体44が同時焼成
された絶縁基板41を製造する。
In FIG. 4(a), an insulating substrate 41 with a conductor 44 co-fired in a through hole 43 is manufactured.

第4図(El)において、絶縁基板41の表面と裏面に
導体薄膜56を被着したのち、第4図(ハ)に示す如く
導体薄膜56の不要部を除去して導体パターン45と5
0を形成させる。
In FIG. 4 (El), after a conductive thin film 56 is deposited on the front and back surfaces of the insulating substrate 41, unnecessary parts of the conductive thin film 56 are removed as shown in FIG. 4 (c), and the conductive patterns 45 and 56 are
0 is formed.

第4図(=)において、焼成の完了したポリイミド層4
6と51を形成させる。
In FIG. 4 (=), the polyimide layer 4 after firing is completed.
6 and 51 are formed.

第4図0)において、ポリイミド層46と51をそれぞ
れに覆う導体薄膜57を被着させる。
In FIG. 40), a thin conductive film 57 is deposited over the polyimide layers 46 and 51, respectively.

次いで第4図(へ)に示す如く、ポリイミド層46に被
着された導体薄膜57の不要部を除去して導体パターン
48を形成し、ポリイミド層51に被着された導体薄膜
57の不要部を除去して、多数の透孔55のあいた導体
薄膜54を形成させる。
Next, as shown in FIG. 4(f), an unnecessary portion of the conductive thin film 57 deposited on the polyimide layer 46 is removed to form a conductive pattern 48, and an unnecessary portion of the conductive thin film 57 deposited on the polyimide layer 51 is removed. is removed to form a conductive thin film 54 with a large number of through holes 55.

次いで第4図(ト)に示す如く、焼成の完了したポリイ
ミド層49を形成し、各導体パターン48と導体膜54
との導通テストを終了したのち、第4図(チ)に示す如
く導体薄膜54の不要部を除去し導体パターン53を形
成させる。
Next, as shown in FIG. 4(g), a fired polyimide layer 49 is formed, and each conductor pattern 48 and conductor film 54 are formed.
After completing the continuity test with the conductive film 54, unnecessary portions of the conductive thin film 54 are removed to form a conductive pattern 53, as shown in FIG. 4(H).

〔発明の効果〕〔Effect of the invention〕

以上説明したように、第1図、第3図を用いて説明した
如く本発明の第1の手段によれば、絶縁基板のバイアホ
ール導体に空洞ができ、該空洞内に洗浄液残滓等が取り
残されけも、該残滓等のガス、水蒸気は該導体に直通す
るポリイミド層の透孔、第2の導体層の開口部より排除
されるため、ポリイミド層に膨らみができないようにな
る。
As explained above, according to the first means of the present invention as explained using FIG. 1 and FIG. Gases, such as the residue, and water vapor are removed from the through holes in the polyimide layer that communicate directly with the conductor and the openings in the second conductor layer, so that the polyimide layer is prevented from swelling.

また、第2図、第4図を用いて説明した如く本発明の第
2の手段によれば、第3のポリイミド層の焼成に際して
第2のポリイミド層より発生するガス、水蒸気は、導体
薄膜に設けられた透孔より排除され、第2のボリイくド
層に膨らみができないようになる。
Furthermore, as explained using FIGS. 2 and 4, according to the second means of the present invention, gas and water vapor generated from the second polyimide layer during firing of the third polyimide layer are transferred to the conductive thin film. It is removed through the provided through hole, and no bulge is formed in the second voluminous layer.

その結果、ポリイミド層を眉間絶縁層とした多層配線基
板の製造歩留まりおよび、信頼性が向上されるようにな
った。
As a result, the manufacturing yield and reliability of a multilayer wiring board using a polyimide layer as an insulating layer between the eyebrows has been improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例による多層配線基板の要
部、 第2図は本発明の第2の実施例による多層配線基板の要
部、 第3図は第1図に示す多層配線基板の主要工程図、 第4図は第2図に示す多層配線基板の主要工程図、 第5図は第4図に示す第5の導体薄膜の平面図、第6図
は従゛来の多層配線基板の要部、第7図は従来の多層配
線基板におけるボリイミド層の膨らみの説明図、 である。 図中において、 21.41は多層配線基板、 22.42は絶縁基板、 23、43はバイアホールの透孔、 24.44はバイアホールの導体、 25.45は第1の導体パターン、 26はポリイミド層、 27はポリイミド層の透孔、 29.48は第2の導体パターン、 37.38は開口部、 46は第1のポリイミド層、 47は第1のポリイミド層の透孔、 49は第2のポリイミド層、 50は第3の導体パターン、 51は第3のポリイミド層、 52は第3のポリイミド層の透孔、 53は第4の導体パターン、 54は導体薄膜、 55は導体薄膜にあけられた透孔、 を示す。 第1図にホす多I配縫蟇抜の主嘗工程図宴 3 図 (−5r) 冥2図tこ示、イ多唇O己篠基本反の主、1と工jjL
ロ嵩 4 図
1 shows the main parts of a multilayer wiring board according to the first embodiment of the present invention, FIG. 2 shows the main parts of the multilayer wiring board according to the second embodiment of the invention, and FIG. 3 shows the multilayer wiring board shown in FIG. 1. Fig. 4 is a main process diagram of the multilayer wiring board shown in Fig. 2, Fig. 5 is a plan view of the fifth conductive thin film shown in Fig. 4, and Fig. 6 is a diagram of the conventional wiring board. Main parts of a multilayer wiring board, FIG. 7 is an explanatory diagram of the bulge of a polyimide layer in a conventional multilayer wiring board. In the figure, 21.41 is a multilayer wiring board, 22.42 is an insulating substrate, 23 and 43 are through holes of via holes, 24.44 is a conductor of via holes, 25.45 is a first conductor pattern, and 26 is a polyimide layer; 27 is a through hole in the polyimide layer; 29.48 is a second conductor pattern; 37.38 is an opening; 46 is a first polyimide layer; 47 is a through hole in the first polyimide layer; 2 polyimide layer, 50 is the third conductor pattern, 51 is the third polyimide layer, 52 is the through hole of the third polyimide layer, 53 is the fourth conductor pattern, 54 is the conductor thin film, 55 is the conductor thin film A drilled through hole is shown. Figure 1 shows the master's process of sewing and removing the needles. Figure 3 (-5r).
Figure 4

Claims (2)

【特許請求の範囲】[Claims] (1)透孔(23)内に導体(24)が埋設されたバイ
アホールを有する絶縁基板(22)と、 該絶縁基板(22)上に該導体(24)と同時に形成さ
れた第1の導体パターン(25)と、 該第1の導体パターン(25)を被覆し少なくとも該導
体(24)の真上で該第1の導体パターン(25)のそ
れぞれに直通する透孔(27)を有するポリイミド層(
26)を具え、 該ポリイミド層(26)の上に形成し該透孔(27)の
側面を通って該第1の導体パターン(25)に接続され
る第2の導体パターン(29)には、該透孔(27)内
に該第1の導体パターン(25)の一部を表呈させる開
口部(37,38)を設けてなることを特徴とする多層
配線基板におけるポリイミド層の膨らみ防止構造。
(1) An insulating substrate (22) having a via hole in which a conductor (24) is embedded in a through hole (23), and a first insulating substrate (22) having a via hole in which a conductor (24) is embedded in the through hole (23); a conductor pattern (25), and a through hole (27) that covers the first conductor pattern (25) and directly communicates with each of the first conductor patterns (25) at least directly above the conductor (24). Polyimide layer (
26), a second conductor pattern (29) formed on the polyimide layer (26) and connected to the first conductor pattern (25) through the side surface of the through hole (27); Prevention of swelling of a polyimide layer in a multilayer wiring board, characterized in that openings (37, 38) are provided in the through hole (27) to expose a part of the first conductor pattern (25). structure.
(2)透孔(43)内に導体(44)が埋設されたバイ
アホールを有する絶縁基板(42)、該絶縁基板(42
)の表面には少なくとも第1の導体パターン(45),
該第1の導体パターン(45)の所要部に連通する透孔
(47)を有する第1のポリイミド層(46),該第1
のポリイミド層(46)の透孔(47)にて該第1の導
体パターン(45)に連通する第2の導体パターン(4
8),該第2の導体パターン(48)の所要部を表呈せ
しめる第2のポリイミド層(49)が設けられ、該絶縁
基板(42)の裏面には少なくとも第3の導体パターン
(50),該第3の導体パターン(50)の所要部に連
通する透孔(52)を有する第3のポリイミド層(51
),該第3のポリイミド層(51)の透孔(52)にて
該第3の導体パターン(50)に連通する第4の導体パ
ターン(53)が設けられ、 該第3のポリイミド層(51)形成後に形成された該第
4の導体パターン(53)が、該第3の導体パターン(
50)と対向しない箇所に透孔(55)のあけられた導
体薄膜(54)から形成されてなることを特徴とする多
層配線基板におけるポリイミド層の膨らみ防止構造。
(2) an insulating substrate (42) having a via hole in which a conductor (44) is embedded in the through hole (43);
) at least a first conductor pattern (45),
a first polyimide layer (46) having a through hole (47) communicating with a required portion of the first conductor pattern (45);
A second conductor pattern (4) communicates with the first conductor pattern (45) through a through hole (47) in the polyimide layer (46).
8) A second polyimide layer (49) is provided that exposes a necessary portion of the second conductor pattern (48), and at least a third conductor pattern (50) is provided on the back surface of the insulating substrate (42). , a third polyimide layer (51) having a through hole (52) communicating with a required portion of the third conductor pattern (50).
), a fourth conductor pattern (53) is provided which communicates with the third conductor pattern (50) through the through hole (52) of the third polyimide layer (51); 51) The fourth conductor pattern (53) formed after the formation is similar to the third conductor pattern (53).
A polyimide layer bulge prevention structure in a multilayer wiring board, characterized in that it is formed from a conductive thin film (54) with a through hole (55) formed at a location not facing the polyimide layer (50).
JP32302689A 1989-12-13 1989-12-13 Swelling prevention structure of polyimide layer in multilayer wiring board Expired - Lifetime JPH0795629B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32302689A JPH0795629B2 (en) 1989-12-13 1989-12-13 Swelling prevention structure of polyimide layer in multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32302689A JPH0795629B2 (en) 1989-12-13 1989-12-13 Swelling prevention structure of polyimide layer in multilayer wiring board

Publications (2)

Publication Number Publication Date
JPH03184396A true JPH03184396A (en) 1991-08-12
JPH0795629B2 JPH0795629B2 (en) 1995-10-11

Family

ID=18150291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32302689A Expired - Lifetime JPH0795629B2 (en) 1989-12-13 1989-12-13 Swelling prevention structure of polyimide layer in multilayer wiring board

Country Status (1)

Country Link
JP (1) JPH0795629B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06164144A (en) * 1992-11-25 1994-06-10 Kyocera Corp Multilayer interconnection board
US6766576B2 (en) 1998-09-18 2004-07-27 International Business Machines Corporation Method for producing a double-sided wiring board
WO2018186131A1 (en) * 2017-04-06 2018-10-11 株式会社デンソー Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06164144A (en) * 1992-11-25 1994-06-10 Kyocera Corp Multilayer interconnection board
US6766576B2 (en) 1998-09-18 2004-07-27 International Business Machines Corporation Method for producing a double-sided wiring board
WO2018186131A1 (en) * 2017-04-06 2018-10-11 株式会社デンソー Semiconductor device
JP2018181962A (en) * 2017-04-06 2018-11-15 株式会社デンソー Semiconductor device

Also Published As

Publication number Publication date
JPH0795629B2 (en) 1995-10-11

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