JPS5832440A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPS5832440A
JPS5832440A JP56130553A JP13055381A JPS5832440A JP S5832440 A JPS5832440 A JP S5832440A JP 56130553 A JP56130553 A JP 56130553A JP 13055381 A JP13055381 A JP 13055381A JP S5832440 A JPS5832440 A JP S5832440A
Authority
JP
Japan
Prior art keywords
wiring
stitch
layers
circuit parts
facing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56130553A
Other languages
Japanese (ja)
Inventor
Naoharu Senba
仙波　直治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56130553A priority Critical patent/JPS5832440A/en
Publication of JPS5832440A publication Critical patent/JPS5832440A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve integration in the formation of a plurality of wiring paths which surround circuit parts placed on an insulative substrate by using a two- layer, upper and lower, construction of the wiring paths in a zigzag arrangement with an insulating glass sandwiched between the layers and facing stitchlands of extreme ends of the wiring paths to the circuit parts. CONSTITUTION:Circuit parts 2 are placed on the central part of an insulative ceramic substrate 1, and a plurality of the first (lower) wiring layers 3 are formed around the circuit parts with stitchlands 3a at the extreme ends of the layers facing the parts. On the wiring layers 3 the second (upper) wiring layers 6 are formed via an insulating glass 5 with stitchlands 6a similarly facing the circuit parts 2. In this constitution the wiring layers 3,6 facing each other via the glass 5 are positioned in a zigzag arrangement, i.e., the first and second wiring paths 3,6 are in close contact with each other when seen from the surface. This increases the density of wire bonding to the parts 2.

Description

【発明の詳細な説明】 本発明は、厚膜基板上に搭載された回路部品をワイヤボ
ンディング法により接続する混成集積回路装置に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hybrid integrated circuit device in which circuit components mounted on a thick film substrate are connected by a wire bonding method.

従来のかかる混成集積回路装置は、第１図（ａ）。Such a conventional hybrid integrated circuit device is shown in FIG. 1(a).

（ｂ）　Ｋ示すように、絶縁基板１の上に搭載された回
路部品２の周囲に配線路３の先端部のステッチランド３
麿を配置し、ワイヤ４のぎンディング法による接続をす
る構造となっている。しかしながら、こＯ様な構造では
、高密度のワイヤボンディング接続が次の理由により不
可能である。厚膜では、配意路の導体幅Ｗが３００μ程
［Ｋなると、第１図（ｃ）　Ｋ示すようＫｓｏｏｓｓｔ
の配意路３で線多少フラット面は残るが、２００ｐ以下
の配意路３′ではフラット面が形成されない。従つて、
フラット面のない配線路のステッチランドへのワイヤボ
ンディング法は非常に不安定であり、ポンディフグ後の
信頼性も低い。更に厚膜印刷の精度も（Ｌ２−程度であ
るために、冥用土の最高ステッチランドピッチ間隔Ｐは
ａ５ｆｉ！度となる。(b) As shown in K, a stitch land 3 is placed at the tip of the wiring path 3 around the circuit component 2 mounted on the insulating substrate 1.
It has a structure in which the wires 4 are connected by the ginning method. However, in this O-like structure, high-density wire bonding connections are impossible for the following reasons. In a thick film, when the conductor width W of the conductor path is about 300μ [K, as shown in Fig. 1(c), Ksoosst
A somewhat flat surface remains in the care path 3 of 200p or less, but no flat surface is formed in the care path 3' of 200p or less. Therefore,
The method of wire bonding to stitch lands for traces without flat surfaces is very unstable and unreliable after pounding. Furthermore, since the accuracy of thick film printing is on the order of L2-, the maximum stitch land pitch interval P of Meiyodo is a5fi! degrees.

本発明の目的は、厚膜基板上に搭載された回路部品のワ
イヤボンディング法を高密度化することを可能にした混
成集積＠略装量を提供するものである。SUMMARY OF THE INVENTION An object of the present invention is to provide a hybrid integration@substantially large amount of wire bonding method for circuit components mounted on a thick film substrate.

本発明を図面に基づき詳細に説明すると、第２図（ａ）
、　（ｂ）線本発明の混成集積回路装置の実施例を示す
図で、（ａ）は平面図、（ｂ）はその断面図でらる。The present invention will be explained in detail based on the drawings as shown in Fig. 2(a).
, (b) are diagrams showing an embodiment of the hybrid integrated circuit device of the present invention, in which (a) is a plan view and (b) is a cross-sectional view thereof.

これらの図において、セラずツク基板ＩＫ回路部品２が
搭載されており、回路部品２の周囲に第１層の配線路３
，３．−・・の先端部のステッチランド３ｍが集るよう
に形成され、第１層のステッチランド３ａｆ露出せしめ
てその他の部分を覆う絶縁ガラス５が配線路３，３．−
・の上に形成され、絶縁ガラス５の上に、第２層の配ｌ
１１Ｎ６．６．−・・が形成されている。第２層の配層
路６，６．・・・は横方向に並んだ第１層の配線路３，
３．−・・の間に絶縁ガラス５ｔ−隔てて入る本うな位
置を占め、かつ、先端部のステッチランド６暑は、第１
層のステッチランド３ｍよ）引込んだ位置にあに、その
結果、＃！１層のステッチ−）／ド３ａと第２層のステ
ッチランド６ａは千鳥足配列となっている。し九がって
、ステッチランド３ａ、６ａの回路部品２に対するワイ
ヤボンディングは、上記の千鳥足配列のために非常にや
〕馬くなりている。In these figures, a ceramic board IK circuit component 2 is mounted, and a first layer wiring path 3 is installed around the circuit component 2.
,3. - is formed so that the stitch lands 3m at the tips of the wiring paths 3, 3, . −
・The second layer is formed on the insulating glass 5.
11N6.6. -... is formed. Second layer layered path 6,6. ... are the wiring paths 3 of the first layer arranged in the horizontal direction,
3. - The insulating glass 5t - occupies a position that separates the main part, and the stitch land 6 at the tip is the first
The stitch land of the layer is 3m) In the retracted position, as a result, #! The stitch lands 6a of the first layer and the stitch lands 6a of the second layer are arranged in a staggered manner. Therefore, the wire bonding of the stitch lands 3a, 6a to the circuit component 2 is very difficult due to the staggered arrangement described above.

すなわち、このような構造によれば、前述したように、
厚膜の導体幅Ｗは最低３００μ溝とした場合、ボンディ
ングワイヤのピッチＰは前述したα５ｍと比較した場合
、０．３露とな、〉１７倍の高密度化が実現できる。更
に、本実施例では、回路部品外周ステッチランドは１周
であるが、これを３周以上にすれば、更にボンディング
ワイヤのピッチは減少でき、高密度のワイヤボンディン
グが可能である。絶縁ガラス上の導体に対するワイヤボ
ンディングの信頼性向上のために、本発明ではステッチ
ランド部分のみ２＠以上の印刷を行い可能にしている。In other words, according to this structure, as mentioned above,
When the thick film conductor width W is at least 300 μm groove, the pitch P of the bonding wire is 0.3 dew compared to the above-mentioned α5m, which is 17 times higher density. Further, in this embodiment, the circuit component outer circumference stitch land is one round, but if this is made three or more rounds, the pitch of the bonding wire can be further reduced, and high-density wire bonding is possible. In order to improve the reliability of wire bonding to conductors on insulating glass, the present invention enables printing of 2@ or more only on the stitch land portion.

本発明は以上説明したように、厚膜基板のワイヤボンデ
ィングのステッチランドを千鳥足配列と絶縁ガラス上に
も設け、更に絶縁ガラス上のステッチランドは２回以上
の印刷を行うことで、高密度のワイヤボンディングを可
能にしている。As explained above, the present invention provides wire bonding stitch lands for thick film substrates in a staggered arrangement and also on insulating glass, and furthermore, the stitch lands on insulating glass are printed two or more times to achieve high density. Enables wire bonding.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（２１）は、従来の混成集積回路装置を示す平面
図、同図（ｂ）、　（Ｃ）は断面図、第２図（ａ）社、
本発明による実−例を示す平面図、同図（ｂ）は断面図
である。 ｌ・・・・・・絶縁セラミック基板、２・・・・・・回
路部品、３・・・・・・第１層の配機略、３ａ−一・ス
テッチランド、４・・・・・・ケンディングワイヤ、５
・・・・・・絶縁ガラス、／ 第　１　刀FIG. 1 (21) is a plan view showing a conventional hybrid integrated circuit device, FIG. 1 (b) and (C) are cross-sectional views, and FIG.
A plan view showing an example according to the present invention, and FIG. 3(b) is a sectional view. l... Insulated ceramic substrate, 2... Circuit components, 3... First layer layout, 3a-1 Stitch land, 4... Kending wire, 5
・・・・・・Insulated glass, / 1st sword

Claims (1)

【特許請求の範囲】[Claims] 絶縁基板の上に搭載された回路部品の周囲にステッチラ
ンドが集るように配置された複数の配線路を有し、これ
らのステッチランドと前記回路部品との間をワイヤボン
ディングによ拳接続して成る混成集積回路装置において
、前記配意路は絶縁層を介して複数層に形成され、これ
ら複数層の配意路のうち下層の配意路のステッチランド
は上層の配意路のステッチランドよ）前記回路部品に近
い位置を占め、かつ、上層の配線路は横方向に並ぶ下層
の配理路同志の間の位置を占めて上層と下層のステッチ
ランド拡千鳥足配列とされていることｔ特徴とする混成
集積回路装置。It has a plurality of wiring paths arranged so that stitch lands are gathered around circuit components mounted on an insulating substrate, and these stitch lands and the circuit components are connected by wire bonding. In the hybrid integrated circuit device comprising: 2) The upper layer wiring path occupies a position close to the circuit component, and the upper layer wiring path occupies a position between the lower layer wiring paths arranged in the horizontal direction, so that the stitch land of the upper layer and the lower layer is in an expanded staggered arrangement. Hybrid integrated circuit device.
JP56130553A 1981-08-20 1981-08-20 Hybrid integrated circuit device Pending JPS5832440A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56130553A JPS5832440A (en) 1981-08-20 1981-08-20 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56130553A JPS5832440A (en) 1981-08-20 1981-08-20 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5832440A true JPS5832440A (en) 1983-02-25

Family

ID=15037019

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56130553A Pending JPS5832440A (en) 1981-08-20 1981-08-20 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5832440A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58178540A (en) * 1982-04-13 1983-10-19 Nec Corp Semiconductor device
FR2557366A1 (en) * 1983-12-27 1985-06-28 Mitsubishi Electric Corp Integrated circuit semiconductor connection pattern

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58178540A (en) * 1982-04-13 1983-10-19 Nec Corp Semiconductor device
FR2557366A1 (en) * 1983-12-27 1985-06-28 Mitsubishi Electric Corp Integrated circuit semiconductor connection pattern

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