JPH0563367A - Low temperature fired ceramic multilayer wiring board - Google Patents
Low temperature fired ceramic multilayer wiring boardInfo
- Publication number
- JPH0563367A JPH0563367A JP12314491A JP12314491A JPH0563367A JP H0563367 A JPH0563367 A JP H0563367A JP 12314491 A JP12314491 A JP 12314491A JP 12314491 A JP12314491 A JP 12314491A JP H0563367 A JPH0563367 A JP H0563367A
- Authority
- JP
- Japan
- Prior art keywords
- gold
- bonding pad
- silver
- ceramic multilayer
- low temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、基板表面に少なくとも
金からなるボンディングパッド部が必要な低温焼成セラ
ミック多層配線基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low temperature fired ceramic multilayer wiring substrate which requires a bonding pad portion made of at least gold on the substrate surface.
【０００２】[0002]
【従来の技術】従来、低温焼成セラミック多層配線基板
において、実装密度の向上を目的としたワイヤボンディ
ングによるベアチップＩＣの搭載をする際、ボンディン
グ性並びに接続信頼性を確保するため、金をボンディン
グパッド部の材料として用いることが知られている。こ
のように、低温焼成セラミック多層配線基板の表面に金
ボンディングパッド部を設ける場合、内部の配線層との
電気的な導通をとるためのビアホール内で使用する材料
として、金等に比べて価格が廉価であるため銀または銀
−パラジウムを使用するのが一般的であった。2. Description of the Related Art Conventionally, when a bare chip IC is mounted on a low temperature fired ceramic multilayer wiring board by wire bonding for the purpose of improving the mounting density, gold is used for the bonding pad portion in order to ensure bonding property and connection reliability. It is known to be used as a material. As described above, when the gold bonding pad portion is provided on the surface of the low-temperature fired ceramic multilayer wiring board, the price is higher than that of gold etc. as the material used in the via hole for establishing electrical conduction with the internal wiring layer. It was common to use silver or silver-palladium because it was cheap.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、金ボン
ディングパッド部に接続する直下のビア導体材料が銀ペ
ーストでは、焼成時の金と銀との相互拡散速度の違いに
より、焼成時に接続界面で空洞が形成される（カーケン
ダル効果）ために、オープン不良が多発する問題があっ
た。そのため、図２にその一例を示すように、銀ビア１
１と金ボンディングパッド部１２との間に、例えば銀−
パラジウム層１３を介在させなければならない問題があ
った。そのため、金ボンディングパッド部と銀−パラジ
ウム層とのオーバーラップ部の印刷ズレを配慮し、設計
基準を緩和する必要があった。However, when the via conductor material immediately below the gold bonding pad portion is a silver paste, a cavity is formed at the connection interface during firing due to the difference in the mutual diffusion rate between gold and silver during firing. Due to the formation (Kirkendal effect), there is a problem that open defects frequently occur. Therefore, as shown in the example in FIG.
1 and the gold bonding pad portion 12, for example, silver-
There was a problem that the palladium layer 13 had to be interposed. Therefore, it is necessary to consider the print deviation of the overlapping portion between the gold bonding pad portion and the silver-palladium layer and relax the design standard.
【０００４】また、金ボンディングパッド部に接続する
直下のビア導体材料が銀−パラジウムでは、例えば図３
にその一例を示すように、金ボンディングパッドを基板
と同時焼成する場合、銀−パラジウムビア１４をなす銀
−パラジウムペーストが焼成時に体積膨張を生じるため
に、銀−パラジウムビア１４が金ボンディングパッド部
１２を突き上げ、金ボンディングパッド部１２の平坦度
が損なわれるという問題があった。そのため、平坦なワ
イヤボンディングエリアを確保するために、金ボンディ
ングパッド部１２の長さを長く形成しなければならない
問題があった。また、金ボンディングパッドを焼成済み
多層基板上に厚膜印刷で形成する場合、銀−パラジウム
ビア１４の突起に金ボンディングパッドを印刷で接続さ
せなければならないため、パターンのにじみを配慮し、
設計基準を緩和する必要があった。If the via conductor material immediately below the gold bonding pad portion is silver-palladium, for example, as shown in FIG.
When the gold bonding pad is co-fired with the substrate, the silver-palladium paste forming the silver-palladium via 14 causes volume expansion during firing. There is a problem that the flatness of the gold bonding pad portion 12 is impaired by pushing up 12. Therefore, in order to secure a flat wire bonding area, there was a problem that the length of the gold bonding pad portion 12 had to be increased. Further, when the gold bonding pad is formed by thick film printing on the baked multilayer substrate, the gold bonding pad must be connected to the protrusion of the silver-palladium via 14 by printing, so that the pattern bleeding is taken into consideration.
It was necessary to relax the design criteria.
【０００５】したがって、上述したようにビア導体とし
て銀または銀−パラジウム等を用いる従来の方法では、
いずれの場合もビアから金ボンディングパッド部先端ま
での距離が長くなっり、ボンディングパッド間のピッチ
が狭くできないために、セラミック多層配線基板の表面
の厚膜パターンの高密度化を達成できない問題があっ
た。Therefore, as described above, according to the conventional method using silver or silver-palladium as the via conductor,
In either case, the distance from the via to the tip of the gold bonding pad becomes long, and the pitch between the bonding pads cannot be narrowed.Therefore, there is a problem that high density of the thick film pattern on the surface of the ceramic multilayer wiring board cannot be achieved. It was
【０００６】本発明の目的は上述した課題を解消して、
金ボンディングパッド部のピッチおよびサイズを最小に
することができ、高密度化を達成することができる低温
焼成セラミック多層配線基板を提供しようとするもので
ある。The object of the present invention is to solve the above problems,
An object of the present invention is to provide a low temperature fired ceramic multilayer wiring board that can minimize the pitch and size of gold bonding pad portions and achieve high density.
【０００７】[0007]
【課題を解決するための手段】本発明の低温焼成セラミ
ック多層配線基板は、基板表面に少なくとも金ボンディ
ングパッド部を有する低温焼成セラミック多層配線基板
において、前記金ボンディングパッド部の直下に金を導
体材料としたビアホールを有することを特徴とするもの
である。The low temperature fired ceramic multilayer wiring board of the present invention is a low temperature fired ceramic multilayer wiring board having at least a gold bonding pad portion on the substrate surface, and gold is used as a conductive material immediately below the gold bonding pad portion. It has a via hole.
【０００８】[0008]
【作用】上述した構成において、金ボンディングパッド
部の直下のビアのみを金からなるビアとしたため、焼成
時のオープン不良や金ボンディングパッド部の平坦度不
良をなくすことができ、さらに設計基準の緩和が不要と
なり、その結果金ボンディングパッド部のピッチおよび
サイズを大きくする必要がなく、高密度化を達成するこ
とができる。また、金の使用を、金ボンディングパッド
部の直下のビアのみとしているため、金ビアを形成する
ことによるコストの上昇を最小限にすることができる。In the above-described structure, only the via immediately below the gold bonding pad is made of gold, so that it is possible to eliminate open defects during firing and flatness of the gold bonding pad, and further relax the design standard. Is unnecessary, and as a result, it is not necessary to increase the pitch and size of the gold bonding pad portion, and high density can be achieved. Further, since the gold is used only in the via directly under the gold bonding pad portion, the increase in cost due to the formation of the gold via can be minimized.
【０００９】[0009]
【実施例】図１は本発明の低温焼成セラミック多層配線
基板の一例の構成を示す断面図である。本実施例では、
表面の１層以外に銀配線層２、銀ビア３、銀−パラジウ
ム配線層４、銀−パラジウムビア５を配し、表面の金ボ
ンディングパッド部６の直下のみを金ビア７で構成して
低温焼成セラミック多層配線基板１を得ている。すなわ
ち、図中最内部の第３内層には銀配線層２を設け、第２
内層にも銀配線層２を設け、これらの銀配線層２の間を
銀ビア３で電気的な導通をとるとともに、第１内層には
銀−パラジウム配線層４を設け、この銀−パラジウム配
線層４と第２内層の銀配線層２との間は銀−パラジウム
ビア５で電気的な導通をとっている。また、図１に示す
ように、表面でも銀−パラジウム配線層４の直下のビア
は銀−パラジウムビア５としている。なお、銀−パラジ
ウムビア５は銀−パラジウシム以外の材料例えば、銀、
銀−白金等を用いても構成可能である。FIG. 1 is a sectional view showing the structure of an example of a low temperature fired ceramic multilayer wiring board of the present invention. In this example,
In addition to one layer on the surface, a silver wiring layer 2, a silver via 3, a silver-palladium wiring layer 4, and a silver-palladium via 5 are arranged, and only under the gold bonding pad portion 6 on the surface is constituted by the gold via 7, and a low temperature is formed. A fired ceramic multilayer wiring board 1 is obtained. That is, the silver wiring layer 2 is provided in the innermost third inner layer in the figure, and the second
The silver wiring layer 2 is also provided in the inner layer, and the silver via 3 electrically connects the silver wiring layers 2 with each other, and the silver-palladium wiring layer 4 is provided in the first inner layer. A silver-palladium via 5 electrically connects between the layer 4 and the second inner silver wiring layer 2. Further, as shown in FIG. 1, the vias on the surface immediately below the silver-palladium wiring layer 4 are silver-palladium vias 5. The silver-palladium via 5 is made of a material other than silver-paradium, for example, silver,
It is also possible to use silver-platinum or the like.
【００１０】上述した構成の低温焼成セラミック多層配
線基板は、低温焼成可能なセラミックグリーンシートに
銀を主成分とするビア導体及び配線導体を印刷し、金ボ
ンディングパッド用の金ペーストの直下のビアには金ペ
ーストを充填した後に積層多層化された未焼成基板を得
た後、同時に低温で焼成することにより得ることができ
る。また、金ボンディングパッド部等の表面導体は焼成
された多層基板に厚膜印刷により形成されるのが一般的
である。In the low-temperature-fired ceramic multilayer wiring board having the above-described structure, a low-temperature-fireable ceramic green sheet is printed with via conductors and wiring conductors containing silver as a main component, and the vias immediately below the gold paste for gold bonding pads are printed. Can be obtained by filling a gold paste, obtaining an unfired substrate having a multilayer structure, and then firing at a low temperature at the same time. Further, surface conductors such as gold bonding pad portions are generally formed by thick film printing on a fired multilayer substrate.
【００１１】本発明は金ボンディングパッド部の直下の
みが金ビアであれば達成でき、その他のビアおよび配線
層は従来から知られているどのようなものでも使用でき
ることはいうまでもない。そのため、上述した実施例に
おける、銀および銀−パラジウム以外の材料例えば銀−
白金等も同様に使用できることはいうまでもない。It goes without saying that the present invention can be achieved if only the gold vias are provided directly under the gold bonding pad portion, and any other known vias and wiring layers can be used. Therefore, in the above-described examples, materials other than silver and silver-palladium, such as silver-
It goes without saying that platinum or the like can be used as well.
【００１２】[0012]
【発明の効果】以上の説明から明らかなように、本発明
によれば、金ボンディングパッド部の直下のビアのみを
金からなるビアとしたため、焼成時のオープン不良や金
ボンディングパッド部の平坦度不良をなくすことがで
き、さらに設計基準の緩和が不必要となり、その結果金
ボンディングパッド部のピッチおよびサイズを大きくす
る必要がなく、高密度化を達成することができる。ま
た、金の使用を、金ボンディングパッド部の直下のビア
のみとしているため、金ビアを形成することによるコス
トの上昇を最小限にすることができる。As is apparent from the above description, according to the present invention, only the via immediately below the gold bonding pad portion is made of gold, and therefore, the open defect during firing and the flatness of the gold bonding pad portion are caused. Defects can be eliminated, and relaxation of design criteria is unnecessary. As a result, there is no need to increase the pitch and size of the gold bonding pad portion, and high density can be achieved. Further, since gold is used only in the vias directly below the gold bonding pad portion, it is possible to minimize an increase in cost due to the formation of the gold vias.
【図１】本発明の低温焼成セラミック多層配線基板の一
例の構成を示す断面図である。FIG. 1 is a cross-sectional view showing a configuration of an example of a low temperature fired ceramic multilayer wiring board of the present invention.
【図２】従来の低温焼成セラミック多層配線基板の一例
の構成を示す断面図である。FIG. 2 is a cross-sectional view showing a configuration of an example of a conventional low temperature firing ceramic multilayer wiring board.
【図３】従来の低温焼成セラミック多層配線基板の他の
例の構成を示す断面図である。FIG. 3 is a cross-sectional view showing the configuration of another example of a conventional low temperature fired ceramic multilayer wiring board.
１ 低温焼成セラミック多層配線基板 ２ 銀配線層 ３ 銀ビア ４ 銀−パラジウム配線層 ５ 銀ーパラジウムビア ６ 金ボンディングパッド部 ７ 金ビア 1 Low-Temperature Ceramic Multilayer Wiring Board 2 Silver Wiring Layer 3 Silver Via 4 Silver-Palladium Wiring Layer 5 Silver-Palladium Via 6 Gold Bonding Pad 7 Gold Via
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０５Ｋ 3/34 Ｂ 9154−4Ｅ 3/46 Ｈ 6921−4Ｅ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI Technical display location H05K 3/34 B 9154-4E 3/46 H 6921-4E
Claims (1)
ッド部を有する低温焼成セラミック多層配線基板におい
て、前記金ボンディングパッド部の直下に金を導体材料
としたビアホールを有することを特徴とする低温焼成セ
ラミック多層配線基板。1. A low temperature fired ceramic multilayer wiring board having at least a gold bonding pad portion on the surface of the substrate, wherein a via hole made of gold as a conductor material is provided directly under the gold bonding pad portion. substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12314491A JPH0563367A (en) | 1991-04-26 | 1991-04-26 | Low temperature fired ceramic multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12314491A JPH0563367A (en) | 1991-04-26 | 1991-04-26 | Low temperature fired ceramic multilayer wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0563367A true JPH0563367A (en) | 1993-03-12 |
Family
ID=14853284
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12314491A Pending JPH0563367A (en) | 1991-04-26 | 1991-04-26 | Low temperature fired ceramic multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0563367A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100673537B1 (en) * | 1999-12-10 | 2007-01-24 | 고등기술연구원연구조합 | A low temperature cofired ceramic on metal and method of producing the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51127112A (en) * | 1975-04-30 | 1976-11-05 | Fujitsu Ltd | Method of producing multiilayered glass substrate |
| JPH01287992A (en) * | 1988-05-13 | 1989-11-20 | Ngk Spark Plug Co Ltd | Low temperature sintered multilayer ceramic board |
-
1991
- 1991-04-26 JP JP12314491A patent/JPH0563367A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51127112A (en) * | 1975-04-30 | 1976-11-05 | Fujitsu Ltd | Method of producing multiilayered glass substrate |
| JPH01287992A (en) * | 1988-05-13 | 1989-11-20 | Ngk Spark Plug Co Ltd | Low temperature sintered multilayer ceramic board |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100673537B1 (en) * | 1999-12-10 | 2007-01-24 | 고등기술연구원연구조합 | A low temperature cofired ceramic on metal and method of producing the same |
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