JPH1197582A - Wiring board and production thereof - Google Patents

Wiring board and production thereof

Info

Publication number
JPH1197582A
JPH1197582A JP27644197A JP27644197A JPH1197582A JP H1197582 A JPH1197582 A JP H1197582A JP 27644197 A JP27644197 A JP 27644197A JP 27644197 A JP27644197 A JP 27644197A JP H1197582 A JPH1197582 A JP H1197582A
Authority
JP
Japan
Prior art keywords
wiring board
insulating
wiring
back surface
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27644197A
Other languages
Japanese (ja)
Inventor
Yasunori Aoi
保典 青井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Niterra Co Ltd
Original Assignee
NGK Spark Plug Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Spark Plug Co Ltd filed Critical NGK Spark Plug Co Ltd
Priority to JP27644197A priority Critical patent/JPH1197582A/en
Publication of JPH1197582A publication Critical patent/JPH1197582A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4061Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates

Abstract

PROBLEM TO BE SOLVED: To reduce the distance of wiring connecting the surface and backside of a board by arranging a plurality of second connecting terminals similarly to a plurality of first connecting terminals and forming a linear wiring connecting the first and second corresponding connecting terminals linearly between insulating stripe members. SOLUTION: First terminals, i.e., a plurality of surface pads 5, are formed on the surface 2a of a wiring board body 2 made of alumina ceramic and second terminals, i.e., a plurality of backside pads 6, are formed on the backside 2b thereof. The surface and backside pads 5, 6 are then connected, respectively, through a plurality of linear inner wiring 7 formed on the side face of insulating strip members 3a-3d by printing or the like. In this regard, the insulating strip members 3a, 3c and 3d have milky white color and the insulating stripe member 3b is added with tungsten, or the like, in order to form a black stripe pattern on white back ground. According to the arrangement, the distance of wiring connecting the surface and backside of the wiring board body 2 can be reduced.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、集積回路チップを
搭載する配線基板およびその製造方法に関し、特に、集
積回路チップと同程度の平面寸法を有するCSP(チッ
プスケールパッケージ)に好ましい配線基板及びその製
造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board on which an integrated circuit chip is mounted and a method of manufacturing the same, and more particularly, to a wiring board suitable for a CSP (chip scale package) having a plane dimension comparable to that of an integrated circuit chip, and a wiring board therefor It relates to a manufacturing method.

【0002】[0002]

【従来の技術】従来、配線基板は、厚みの薄い未焼成の
絶縁層を積層し焼成して形成しており、各絶縁層上に配
線を形成すると共に、絶縁層間の配線の接続には、スル
ーホールやビアを用いていた。このビア等を形成するに
は、まず絶縁層に貫通孔を穿孔する必要があった。
2. Description of the Related Art Conventionally, a wiring board is formed by laminating and firing unsintered insulating layers having a small thickness. Wiring is formed on each of the insulating layers. Through holes and vias were used. In order to form this via or the like, it was necessary to first drill a through hole in the insulating layer.

【0003】ところで、集積回路チップ(以下、ICチ
ップともいう)の高集積化、高速化に伴い、これを搭載
する配線基板についても小型化が求められており、つい
には、ICチップと同程度の平面寸法を持つ配線基板
(いわゆるチップスケールパッケージ、以下CSPとも
いう)が要求されている。例えば、図9に示すCSP1
00においては、2枚の絶縁層101、102を積層し
てなり、その表面101aに形成されたパッド101p
と破線で示すICチップIとをフリップチップ法により
半田S1を介して接続し、その裏面102bに形成され
たパッド102pと破線で示す他の配線基板Pとをフリ
ップチップ法により半田S2を介して接続する。なお、
パッド101pと102pとの間は、CSP内部に形成
されたビア101v、102vにより導通している。
[0003] With the high integration and high speed of integrated circuit chips (hereinafter also referred to as IC chips), miniaturization of a wiring board on which they are mounted is also required. (So-called chip-scale package, hereinafter also referred to as CSP) having a planar dimension of is required. For example, CSP1 shown in FIG.
In FIG. 00, two insulating layers 101 and 102 are laminated, and a pad 101p formed on a surface 101a thereof is formed.
And an IC chip I indicated by a broken line are connected by a solder S1 by a flip chip method, and a pad 102p formed on the back surface 102b and another wiring board P indicated by a broken line are connected by a solder S2 by a flip chip method. Connecting. In addition,
The pads 101p and 102p are electrically connected by vias 101v and 102v formed inside the CSP.

【0004】[0004]

【発明が解決しようとする課題】このCSP100にお
いては、そのビア101v、102v相互の間隔を、I
CチップIの端子(バンプ等)I1の間隔と同じに形成
する必要がある。しかるに、フォトリソグラフィ技術に
よって形成されるICチップIの端子I1の間隔は、例
えば、200μmと非常に小さい。しかもICチップI
には多くの端子I1が形成されている。このため、CS
P100を製造するに当たって、ビア用の貫通穴を小さ
な間隔でしかも多数個(例えば100〜200ヶ)形成
する必要があった。
In the CSP 100, the distance between the vias 101v and 102v is set to I
It is necessary to form the same as the interval between the terminals (bumps and the like) I1 of the C chip I. However, the interval between the terminals I1 of the IC chip I formed by the photolithography technique is very small, for example, 200 μm. Moreover, IC chip I
Are formed with many terminals I1. For this reason, CS
In manufacturing P100, it was necessary to form a large number of through holes for vias at small intervals (for example, 100 to 200).

【0005】このような狭ピッチでしかも多数個のビア
用貫通穴を未焼成の絶縁層に穿孔するのは困難であり、
一度に金型を用いて多数の貫通孔を穿孔しようとする
と、貫通穴径100μm、ピッチ250μm程度が限度
であった。従って、それ以下のピッチや径の貫通孔を形
成する場合には、1ヶまたは数ヶずつ貫通孔を穿孔して
ゆくことになり、時間やコストが掛かっていた。さら
に、CSP100の厚さを稼ぐために、複数の絶縁層
(本例では101、102の2層)を積層してCSP1
00を形成する場合には、複数の絶縁層それぞれに貫通
孔を穿孔する必要があり、面倒であった。
[0005] It is difficult to form such a narrow pitch and a large number of via through holes in an unfired insulating layer.
When attempting to drill a large number of through holes using a mold at a time, the through hole diameter is limited to 100 μm and the pitch is limited to about 250 μm. Therefore, when forming a through hole with a pitch and a diameter smaller than that, it is necessary to drill one or several through holes, which takes time and costs. Further, in order to increase the thickness of the CSP 100, a plurality of insulating layers (two layers 101 and 102 in this example) are stacked to form the CSP 100.
In the case where 00 is formed, it is necessary to form through holes in each of the plurality of insulating layers, which is troublesome.

【0006】さらに、CSPにおいては、ICチップを
搭載するときや、CSPを他の配線基板に搭載(接続)
するときに、その位置決めや方向判別をする必要があ
る。また、CSPの品番等を識別する必要もある。簡易
な構成でCSPに標識を設ける手法も求められていた。
Further, in the CSP, when mounting an IC chip or mounting (connecting) the CSP on another wiring board.
When doing this, it is necessary to determine the positioning and direction. Also, it is necessary to identify the part number of the CSP. There has also been a demand for a method of providing a mark on a CSP with a simple configuration.

【0007】本発明は、かかる問題点に鑑みてなされた
ものであって、第1の目的は、基板の表裏面を結ぶ配線
相互の間隔を狭くでき、しかも製作容易な配線基板及び
その製造方法を提供することにある。また、他の目的
は、位置決めや方向判別、品番判別等を可能とする標識
を簡易な構成で設けた配線基板及びその製造方法を提供
することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and a first object of the present invention is to provide a wiring board which can reduce the distance between wirings connecting the front and back surfaces of the board and which is easy to manufacture, and a method of manufacturing the same. Is to provide. It is another object of the present invention to provide a wiring board provided with a sign having a simple configuration for enabling positioning, direction discrimination, product number discrimination, and the like, and a method of manufacturing the same.

【0008】[0008]

【課題を解決するための手段】しかして、請求項1に記
載の解決手段は、表面と裏面とを有する平板形状を有
し、複数の帯状絶縁部材をその幅方向に相互に密着させ
て列設してなる絶縁部材と、該絶縁部材の表面に形成さ
れた複数の第1接続用端子と、上記絶縁部材の裏面に形
成され、上記第1接続用端子と同配置で配置された複数
の第2接続用端子と、上記帯状絶縁部材間に形成され、
上記第1接続用端子とこれに対応する第2接続用端子と
をそれぞれ直線状に結ぶ内部配線と、を有する配線基板
である。
According to a first aspect of the present invention, there is provided a liquid crystal display having a flat plate shape having a front surface and a back surface, and a plurality of strip-shaped insulating members being closely attached to each other in a width direction thereof. An insulating member, a plurality of first connection terminals formed on the surface of the insulating member, and a plurality of terminals formed on the back surface of the insulating member and arranged in the same arrangement as the first connection terminal. Formed between the second connection terminal and the strip-shaped insulating member;
A wiring board having an internal wiring that linearly connects the first connection terminal and the corresponding second connection terminal.

【0009】かかる配線基板によれば、内部配線が帯状
絶縁部材間に形成されているので、従来の配線基板のよ
うに絶縁層を貫通するビアを形成するために貫通穴を穿
孔する必要がない。このため、印刷等によって内部配線
を形成すればよく、隣接する内部配線間の間隔を小さく
したものとすることができる。なお、内部配線は表面及
び裏面に垂直な直線状にすると配線の長さが短くなって
好ましい。
According to such a wiring board, since the internal wiring is formed between the strip-shaped insulating members, it is not necessary to form a through hole to form a via penetrating the insulating layer unlike a conventional wiring board. . For this reason, the internal wiring may be formed by printing or the like, and the interval between adjacent internal wirings can be reduced. The internal wiring is preferably formed in a straight line perpendicular to the front surface and the back surface, since the length of the wiring is shortened.

【0010】ここで、絶縁部材としては、アルミナ、ガ
ラスセラミック、AlN等のセラミックが挙げられる。
また、第1接続用端子や第2接続用端子、内部配線に
は、絶縁部材の材質との密着性や導電率、半田付け性等
を考慮して選択すればよいが、例えば、W、Mo、A
g、Ag−Pt、Ag−Pd、Au、Cu等が挙げら
れ、さらに、W、Mo等に関しては、耐酸化性や半田付
け性等を改善するためにその露出部にNiメッキやAu
メッキを施してもよい。また、第1、第2接続用端子の
形状は特に限定されず、例えばパッド、バンプ形状のも
のが挙げられる。
Here, examples of the insulating member include ceramics such as alumina, glass ceramic, and AlN.
In addition, the first connection terminal, the second connection terminal, and the internal wiring may be selected in consideration of the adhesion to the material of the insulating member, the conductivity, the solderability, and the like. , A
g, Ag-Pt, Ag-Pd, Au, Cu, and the like. Further, with respect to W, Mo, and the like, in order to improve oxidation resistance, solderability, and the like, Ni plating or Au
Plating may be applied. Further, the shape of the first and second connection terminals is not particularly limited, and examples thereof include pads and bumps.

【0011】さらに、請求項2に記載の解決手段は、前
記表面及び裏面のうち少なくともいずれかは、研磨面で
あることを特徴とする請求項1に記載の配線基板であ
る。
[0011] Further, according to a second aspect of the present invention, there is provided the wiring board according to the first aspect, wherein at least one of the front surface and the rear surface is a polished surface.

【0012】この配線基板によれば、表面及び裏面のう
ち少なくとのいずれかが研磨面である。したがって、研
磨面上に形成された第1または第2接続端子の上面のコ
プラナリティを良好にすることができる。例えば、表面
が研磨面である場合には、この表面に形成された第1接
続端子の上面のコプラナリティが良好となる。従って、
この配線基板の表面にフリップチップ法により集積回路
チップを接続する場合に、第1接続用端子とチップとの
接続性を高くすることができる。同様に、裏面が研磨面
であるばあいには、この裏面に形成される第2接続用端
子の上面のコプラナリティが向上する。従って、この裏
面に他の配線基板をフリップチップ法により接続する場
合、第2接続用端子と他の配線基板との接続性を高くす
ることができる。
According to this wiring board, at least one of the front surface and the back surface is a polished surface. Therefore, the coplanarity of the upper surface of the first or second connection terminal formed on the polished surface can be improved. For example, when the surface is a polished surface, the coplanarity of the upper surface of the first connection terminal formed on this surface is good. Therefore,
When an integrated circuit chip is connected to the surface of the wiring substrate by a flip chip method, the connectivity between the first connection terminal and the chip can be improved. Similarly, when the back surface is a polished surface, the coplanarity of the upper surface of the second connection terminal formed on the back surface is improved. Therefore, when another wiring board is connected to this back surface by the flip-chip method, the connectivity between the second connection terminal and the other wiring board can be improved.

【0013】さらに、請求項3に記載の解決手段は、前
記帯状絶縁部材のうち少なくとも1層以上の帯状絶縁部
材が、他の帯状絶縁部材と異なる色彩を有することを特
徴とする請求項1または2に記載の配線基板である。
Further, according to a third aspect of the present invention, at least one or more layers of the band-shaped insulating members have a color different from that of the other band-shaped insulating members. 2. The wiring board according to item 2.

【0014】本発明によれば、色彩の異なる帯状絶縁部
材により、例えば配線基板の表面には、帯状の模様が形
成される。予めこの帯の数や配置等の模様を読みとるこ
とにより、配線基板の種類(品番)や方向、位置等を認
識することができる。
According to the present invention, a strip-shaped pattern is formed on, for example, the surface of the wiring board by the strip-shaped insulating members having different colors. By reading the pattern such as the number and arrangement of the bands in advance, the type (product number), direction, position, and the like of the wiring board can be recognized.

【0015】さらに、請求項4に記載の解決手段は、未
焼成絶縁層の表面または裏面の少なくともいずれか一方
の上に互いに平行な複数の直線状導体層を形成する工程
と、複数の上記未焼成絶縁層を厚さ方向に積層して積層
体を形成する工程と、該積層体を直線上導体層に直交す
る方向に所定の厚さに切断して未焼成配線基板を形成す
る工程と、該未焼成配線基板を焼成する工程と、を有す
ることを特徴とする配線基板の製造方法である。
Further, a solution according to claim 4 is a step of forming a plurality of linear conductor layers parallel to each other on at least one of the front surface and the back surface of the unfired insulating layer; A step of forming a laminate by laminating the fired insulating layers in the thickness direction, and a step of forming the unfired wiring substrate by cutting the laminate to a predetermined thickness in a direction perpendicular to the conductor layer on a straight line, Baking the unfired wiring board.

【0016】本発明によれば、未焼成絶縁層の表面また
は裏面の少なくともいずれか一方の上に互いに平行な複
数の直線状導体層を形成し、未焼成絶縁層を積層して積
層体とし、直線状導体層に直交する方向に切断して未焼
成配線基板とし、これを焼成して配線基板を形成する。
したがって、絶縁層に貫通孔を穿孔し導体を充填してビ
アとするような面倒な工程は不要である。また、印刷等
によって直線状導体層を形成できるため、導体層相互の
間隔を小さくできる。従って、導体層の間隔の小さい配
線基板とすることができる。また、切断によって未焼成
配線基板をいくつも形成できるため、安価な配線基板を
製造し得る。
According to the present invention, a plurality of linear conductor layers parallel to each other are formed on at least one of the front surface and the back surface of the unsintered insulating layer, and the unsintered insulating layers are stacked to form a laminate. An unsintered wiring board is cut by cutting in a direction orthogonal to the linear conductor layer, and the unsintered wiring board is fired to form a wiring board.
Therefore, a troublesome process of forming a via by forming a through hole in the insulating layer and filling the conductor with the conductor is unnecessary. Further, since the linear conductor layer can be formed by printing or the like, the distance between the conductor layers can be reduced. Therefore, it is possible to provide a wiring board having a small distance between the conductor layers. Further, since a number of unfired wiring boards can be formed by cutting, an inexpensive wiring board can be manufactured.

【0017】なお、前記複数の直線状導体層は、未焼成
絶縁層のいずれか一方の面に形成すれば良いが、両面に
形成した場合は、積層した際に1つの未焼成絶縁層の裏
面に形成された直線状導体層と、他の未焼成絶縁層のう
ちの該裏面と貼り合わされる面(表面)に形成された直
線状導体層とが一体化される。その結果、直線状導体層
の厚みが約2倍になり、その分導通抵抗を下げることが
できるので好ましい。
The plurality of linear conductor layers may be formed on any one surface of the unsintered insulating layer. However, when formed on both surfaces, the back surface of one unsintered insulating layer when laminated is formed. Is integrated with the linear conductor layer formed on the surface (front surface) of the other unsintered insulating layer that is bonded to the back surface. As a result, the thickness of the linear conductor layer is approximately doubled, and the conduction resistance can be reduced accordingly, which is preferable.

【0018】また、未焼成絶縁層とは、焼成後に絶縁層
となるものをいい、具体的には、従来公知のドクターブ
レード法やロールコータ法等によって形成したセラミッ
クグリーンシートが挙げられる。
The unsintered insulating layer is a layer which becomes an insulating layer after firing, and specifically includes a ceramic green sheet formed by a conventionally known doctor blade method, roll coater method or the like.

【0019】さらに、請求項5に記載の解決手段は、未
焼成絶縁層の表面または裏面の少なくともいずれか一方
の上に互いに平行な複数の直線状導体層を形成する工程
と、複数の上記未焼成絶縁層を厚さ方向に積層して積層
体を形成する工程と、該積層体を焼成して焼成体を形成
する工程と、該焼成体を直線上導体層に直交する方向に
所定の厚さに切断する工程と、を有することを特徴とす
る配線基板の製造方法である。
Further, a solution according to a fifth aspect is to form a plurality of linear conductor layers parallel to each other on at least one of the front surface and the back surface of the unsintered insulating layer; A step of forming a laminate by stacking the fired insulating layers in the thickness direction, a step of firing the laminate to form a fired body, and a step of forming the fired body to a predetermined thickness in a direction orthogonal to the conductor layer on a straight line. And a step of cutting the wiring board.

【0020】本発明によれば、未焼成絶縁層の表面また
は裏面のいずれか一方の上に互いに平行な複数の直線状
導体層を形成し、未焼成絶縁層を積層して積層体とし、
これを焼成して焼成体とした後、直線状導体層に直交す
る方向に切断して配線基板を形成するので、絶縁層に貫
通孔を穿孔し導体を充填してビアとするような面倒な工
程は不要である。また、印刷等によって直線状導体層を
形成できるため、導体層相互の間隔を小さくできる。従
って、導体層の間隔の小さい配線基板とすることができ
る。また、切断によって配線基板をいくつも形成できる
ため、安価な配線基板を製造し得る。
According to the present invention, a plurality of linear conductor layers parallel to each other are formed on one of the front surface and the back surface of the unsintered insulating layer, and the unsintered insulating layers are stacked to form a laminate.
After baking this into a fired body, it is cut in the direction orthogonal to the linear conductor layer to form a wiring board, so that it is troublesome to drill a through hole in the insulating layer and fill the conductor with a via to form a via. No steps are required. Further, since the linear conductor layer can be formed by printing or the like, the distance between the conductor layers can be reduced. Therefore, it is possible to provide a wiring board having a small distance between the conductor layers. Further, since a number of wiring boards can be formed by cutting, an inexpensive wiring board can be manufactured.

【0021】さらに、請求項6に記載の解決手段によれ
ば、前記積層された未焼成絶縁層のうち、少なくとも1
つ以上の未焼成絶縁層が焼成後の発色が他とは異なる異
色未焼成絶縁層であり、前記積層体形成工程において、
上記異色未焼成絶縁層を所定位置に積層することを特徴
とする請求項4または5に記載の配線基板の製造方法で
ある。
According to a sixth aspect of the present invention, at least one of the stacked unsintered insulating layers is provided.
The one or more unsintered insulating layers are different-color unsintered insulating layers whose coloring after firing is different from the others, and in the laminate forming step,
6. The method for manufacturing a wiring board according to claim 4, wherein said unsintered insulating layers having different colors are laminated at predetermined positions.

【0022】本発明によれば、焼成後の発色が異なる異
色未焼成絶縁層を所定位置に積層しているので、標識を
形成するのに標識形成工程は不要である。また、絶縁層
自身の発色が異なるものを用いるので、研磨等の工程を
経た後も、標識が削り取られてしまうことはない。
According to the present invention, since the uncolored unsintered insulating layers having different colors after firing are laminated at predetermined positions, the sign forming step is not required for forming the sign. In addition, since the insulating layer itself has a different coloring, the sign is not scraped off even after a process such as polishing.

【0023】[0023]

【発明の実施の形態】本発明の実施の形態を、図を参照
しつつ説明する。 (実施例1)図1に本発明の実施例1にかかる配線基板
の斜視図を、また、図2に断面図を示す。ここで、図1
(a)は本実施例にかかる配線基板1の斜視図であり、図
1(b)は、この配線基板1の分解斜視図である。また、
図2(a)は、A−A’断面図を、図2(b)はB−B’断面
図である。図1(a)に示すように、配線基板1は、アル
ミナセラミック製の配線基板本体2を有する。この配線
基板本体2は、矩形平板状であり、図中左右方向に帯状
絶縁部材3a〜3dがその幅方向に密着することにより
形成されている。また、この配線基板本体2の表面2a
には、第1接続端子である表面側パッド5、5が、裏面
2bには、第2接続端子である裏面側パッド6、6が形
成されている。この表面側パッド5と裏面側パッド6と
は、帯状絶縁部材3a〜3dの側面に印刷等により形成
された直線状の内部配線7、7によってそれぞれ接続さ
れている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to the drawings. (Embodiment 1) FIG. 1 is a perspective view of a wiring board according to Embodiment 1 of the present invention, and FIG. 2 is a sectional view. Here, FIG.
FIG. 1A is a perspective view of a wiring board 1 according to the present embodiment, and FIG. 1B is an exploded perspective view of the wiring board 1. Also,
FIG. 2A is a sectional view taken along the line AA ′, and FIG. 2B is a sectional view taken along the line BB ′. As shown in FIG. 1A, the wiring board 1 has a wiring board body 2 made of alumina ceramic. The wiring board main body 2 has a rectangular flat plate shape, and is formed by closely attaching band-shaped insulating members 3a to 3d in the width direction thereof in the left-right direction in the drawing. The surface 2a of the wiring board body 2
, Front side pads 5, 5 which are first connection terminals, and back side pads 6, 6, which are second connection terminals, are formed on the back surface 2 b. The front side pad 5 and the back side pad 6 are connected by linear internal wirings 7 formed on the side surfaces of the band-shaped insulating members 3a to 3d by printing or the like.

【0024】この帯状絶縁部材3a〜3dは、アルミナ
約90%のアルミナセラミック製で、このうち、部材3
a、3c、3dは、乳白色を呈している。一方、部材3
bは、W、Mo、Cr23等が添加されているため、黒
色を呈している。従って、配線基板本体2は、部材3b
によって白地に黒い帯状のストライプ模様が形成されて
いる。また、表面側および裏面側パッド5、6および内
部配線7は、タングステンを主成分としている。また、
表面側および裏面側パッド5、6の表面上には、無電解
ニッケルメッキおよび金メッキが施されており、半田付
け性等の改善が図られている。
The band-shaped insulating members 3a to 3d are made of alumina ceramic of about 90% alumina.
a, 3c and 3d are milky white. On the other hand, member 3
b has a black color because W, Mo, Cr 2 O 3 and the like are added. Therefore, the wiring board main body 2 is
As a result, a black striped stripe pattern is formed on a white background. The front and rear pads 5, 6 and the internal wiring 7 are mainly composed of tungsten. Also,
Electroless nickel plating and gold plating are applied to the surfaces of the front side and back side pads 5 and 6 to improve the solderability and the like.

【0025】ついで、本配線基板1の製造方法について
説明する。まず、図3(a)に示すように、周知のスリッ
プキャスト法によりセラミック成分としてアルミナを主
成分とするグリーンシートGを形成し、その表面にタン
グステンペーストを用い、スクリーン印刷法により互い
に平行な直線状の導体層Lを複数形成する。本例では、
このようなグリーンシートGを3枚(Gb、Gc、G
d)形成し、さらに、導体層Lを形成しないグリーンシ
ートGaを形成しておく。なお、グリーンシートGbに
ついては、他のグリーンシートと異なり、W、Mo、C
23等の着色剤を添加している。
Next, a method of manufacturing the wiring board 1 will be described. First, as shown in FIG. 3A, a green sheet G mainly containing alumina as a ceramic component is formed by a well-known slip casting method, and a tungsten paste is used on the surface thereof, and straight lines parallel to each other are formed by a screen printing method. A plurality of conductor layers L are formed. In this example,
Three such green sheets G (Gb, Gc, G
d) The green sheet Ga on which the conductor layer L is not formed is formed. The green sheet Gb is different from other green sheets in that W, Mo, C
A coloring agent such as r 2 O 3 is added.

【0026】ついで、これらを図3(b)に示すように各
グリーンシートをGd、Gc、Gb、Gaの順に積層、
圧着して図4(a)に示すように積層体Mを形成する。こ
の積層体Mを図4(a)に一点鎖線で示す切断線Xに従っ
て一定間隔(一定厚さ)に切断する。この切断方向は、
内部に形成された導体層Lの長手方向に対して直角な方
向(導体層に対して直交する方向)である。これによ
り、切断された切断体(未焼成配線基板)Cの両側の切
断面C1、C2には、図4(b)に示すように、切断され
た導体層Lの断面Lcが露出した状態となる。また、こ
のように形成すると、いわゆる金太郎飴と同様に切断に
より同形状の切断体Cを容易に形成することができる。
この切断体Cは、各グリーンシートGa等が切断された
帯状部材Ca、Cb、Cc、Cdが相互に積層されたも
のである。なお、この図4(b)からも判るように、グリ
ーンシートGbに相当する帯状部材Cbには、他の部材
と異なり着色剤が添加されている。
Next, as shown in FIG. 3B, these green sheets are laminated in the order of Gd, Gc, Gb, and Ga.
The laminate M is formed by pressure bonding as shown in FIG. The laminate M is cut at a constant interval (constant thickness) according to a cutting line X indicated by a dashed line in FIG. This cutting direction is
This is a direction perpendicular to the longitudinal direction of the conductor layer L formed therein (direction perpendicular to the conductor layer). As a result, as shown in FIG. 4 (b), the cross section Lc of the cut conductor layer L is exposed on the cut surfaces C1 and C2 on both sides of the cut cut body (unfired wiring board) C. Become. Further, when formed in this manner, a cut body C having the same shape can be easily formed by cutting in the same manner as the so-called Kintaro candy.
The cut body C is formed by laminating strip members Ca, Cb, Cc, and Cd obtained by cutting the green sheets Ga and the like. As can be seen from FIG. 4B, a colorant is added to the belt-shaped member Cb corresponding to the green sheet Gb, unlike other members.

【0027】さらに、図5に示すように、この切断体C
の切断面C1、C2に露出する導体層断面Lcを覆うよ
うに、スクリーン印刷によりタングステンペーストを塗
布して、未焼成パッドCpを形成する。なお、図5にお
いては、切断面C2側の未焼成パッドCpは図示しな
い。このパッドCpは、IC基板等との接続時に導体層
断面Lcの形状では、面積が小さすぎるため、接続面積
を増やすために形成される。
Further, as shown in FIG.
A tungsten paste is applied by screen printing so as to cover the conductor layer cross section Lc exposed on the cut surfaces C1 and C2 of FIG. In FIG. 5, the unfired pad Cp on the cut surface C2 side is not shown. The pad Cp is formed in order to increase the connection area because the area of the pad Cp is too small in the shape of the conductor layer cross section Lc when connected to an IC substrate or the like.

【0028】ついで、還元雰囲気中で約1550℃に加
熱して、一体焼結により図1、2に示す配線基板1を形
成する。これにより、帯状部材Ca、Cb、Cc、Cd
はそれぞれ帯状絶縁部材3a〜3dに、導体層Lは内部
配線7に、パッドCpは、表面側パッド5及び裏面側パ
ッド6になる。また、帯状部材Cbは、この焼成により
着色剤が黒く発色して黒色の帯状絶縁部材3bとなり、
着色剤の添加されていない他の帯状絶縁部材3a、3
c、3dは乳白色となる。なお、表面側パッド5および
裏面側パッド6の表面にはさらに、無電解メッキにより
ニッケルメッキ及び金メッキを施す。
Then, the wiring substrate 1 is heated to about 1550 ° C. in a reducing atmosphere and integrally sintered to form the wiring board 1 shown in FIGS. Thereby, the band members Ca, Cb, Cc, Cd
Are the band-shaped insulating members 3a to 3d, the conductor layer L is the internal wiring 7, and the pad Cp is the front surface pad 5 and the rear surface pad 6. In addition, the band-shaped member Cb becomes black in the colorant by the firing, and becomes a black band-shaped insulating member 3b.
Other belt-shaped insulating members 3a, 3 to which no coloring agent is added
c and 3d are milky white. The surfaces of the front side pad 5 and the back side pad 6 are further subjected to nickel plating and gold plating by electroless plating.

【0029】本配線基板においては、表面側パッド5と
裏面側パッド6とを接続する内部配線7は、印刷により
形成した導体層Lを焼成して得た。即ち、従来の配線基
板ようにビアを用いてパッド間を導通しないので、貫通
穴を穿孔しその中に導体を充填する必要が無い。このた
め、内部配線を形成するのが容易であり、内部配線間の
間隔を小さくすることも容易にできる。
In the present wiring board, the internal wiring 7 connecting the front surface side pad 5 and the back surface side pad 6 was obtained by firing a conductive layer L formed by printing. That is, since conduction between pads is not performed using vias as in a conventional wiring board, there is no need to drill through holes and fill them with conductors. Therefore, it is easy to form the internal wiring, and the interval between the internal wirings can be easily reduced.

【0030】本配線基板1においては、図2(a)、(b)に
示す断面図から明らかなように、各内部配線7の間隔d
のうち、帯状絶縁部材3a等の幅方向の間隔d1は、こ
の部材3a等の幅になり、一方、これに直角な帯状絶縁
部材3a等の長手方向の間隔d2は、内部配線7の印刷
等の間隔(ピッチ)によって決まる。間隔d1は、容易
に理解できるように、各グリーンシートGa等の厚さに
よって決まる。さらに詳しく言えば、間隔d1は、概略
グリーンシートGa等の厚さに焼成時の収縮率(焼成収
縮率;通常0.8程度)をかけた値となる。従って、間
隔d1を小さくするには、シートの厚さを薄くすればよ
い。また、間隔d2は、グリーンシートG上に印刷等に
よって形成した導体層Lの間隔と焼成収縮率をかけた値
となる。即ち、スクリーン印刷等の手法により導体層L
を密に形成すればよく、100μmライン&スペース及
びそれ以下の配線を形成することもさほど困難ではな
い。従って、間隔d2の小さい配線基板1を容易に形成
することができる。
In the present wiring board 1, as is apparent from the cross-sectional views shown in FIGS.
Among them, the interval d1 in the width direction of the band-shaped insulating member 3a or the like becomes the width of the member 3a or the like, while the interval d2 in the longitudinal direction of the band-shaped insulating member 3a or the like is perpendicular to the width of the internal wiring 7 or the like. Is determined by the interval (pitch). The interval d1 is determined by the thickness of each green sheet Ga or the like so that it can be easily understood. More specifically, the interval d1 is a value obtained by multiplying the thickness of the green sheet Ga or the like by a shrinkage rate during firing (a firing shrinkage rate: usually about 0.8). Therefore, in order to reduce the distance d1, the thickness of the sheet may be reduced. The interval d2 is a value obtained by multiplying the interval between the conductor layers L formed on the green sheet G by printing or the like by the firing shrinkage. That is, the conductor layer L is formed by a method such as screen printing.
It is not difficult to form a 100 μm line & space and a wiring of less than 100 μm. Therefore, the wiring board 1 with a small distance d2 can be easily formed.

【0031】このようにして形成した配線基板1を、図
6に示すように、その表面2a側に形成された表面側パ
ッド5とICチップIとをフリップチップ法により半田
S1を介して接続し、その裏面側2bに形成された裏面
側パッド6と他の配線基板Pとをフリップチップ法によ
り半田S2を介して接続する。パッド5と6との間は、
それぞれ内部配線7により導通している。また、本実施
例の配線基板は、内部配線7が直線状に形成され、配線
基板本体2の表裏面間を最短距離で接続しているので、
ICチップIと他の配線基板Pの信号のやりとりを高速
で行わせることができる。
As shown in FIG. 6, the wiring board 1 formed as described above is connected to the front-side pad 5 formed on the front surface 2a side of the wiring board 1 and the IC chip I via the solder S1 by the flip-chip method. Then, the back surface side pad 6 formed on the back surface side 2b and another wiring board P are connected via the solder S2 by the flip chip method. Between the pads 5 and 6,
Each is electrically connected by the internal wiring 7. Further, in the wiring board of the present embodiment, since the internal wiring 7 is formed in a straight line and connects the front and back surfaces of the wiring board body 2 with the shortest distance,
It is possible to exchange signals between the IC chip I and the other wiring board P at high speed.

【0032】さらに、本実施例においては、帯状絶縁部
材3bのみ黒色としてストライプ模様を形成したので、
配線基板1の品番や基板の向き(方向)、各パッドの位
置をこの模様から検出することができる。即ち、予め、
グリーンシート中に他とは焼成後の発色を異ならせる添
加剤を添加しておくことにより、容易に模様を付けるこ
とができ、この模様によって配線基板の品番や配線基板
の向きやパッドの位置等を検出させることができる。例
えば、本例においては、4つの帯状絶縁部材のうち1つ
(3b)を黒色化した。同様にして部材3aを黒色化し
てもよく、このように黒色化させる部材の位置により品
番等を判別することができる。また、複数本のストライ
プの組み合わせでも良い。なお、本例においては、W、
Mo、Cr23を添加して黒色化した例を示したが、他
の添加物を添加して他の色に発色させてもよく、添加物
の添加量を調節することで色調(濃淡)を変化させても
良い。また、全体を黒色化し、1部の部材のみ添加剤を
加えない白色セラミックとしても良い。
Further, in the present embodiment, since only the strip-shaped insulating member 3b is formed in a black stripe pattern,
The product number of the wiring board 1, the direction (direction) of the board, and the position of each pad can be detected from this pattern. That is,
By adding an additive that makes the color development after firing different from the others in the green sheet, it is possible to easily add a pattern, and by this pattern, the product number of the wiring board, the orientation of the wiring board, the position of the pad, etc. Can be detected. For example, in this example, one (3b) of the four strip-shaped insulating members was blackened. Similarly, the member 3a may be blackened, and the product number or the like can be determined based on the position of the member to be blackened. Further, a combination of a plurality of stripes may be used. In this example, W,
Although an example in which Mo and Cr 2 O 3 are added to make a black color is shown, other additives may be added to form a different color, and the color tone (shading) is adjusted by adjusting the amount of the additive. ) May be changed. Further, the whole may be blackened and a white ceramic may be used in which only one part is added with no additive.

【0033】(実施例2)上記実施例1においては、積
層体Mを切断して切断体Cを形成し、さらに、未焼成パ
ッドCpを形成した後に、同時焼成により配線基板1を
形成した例を示したが、本例においては、切断体Cを焼
成した後にパッドを形成する。即ち、実施例1と同様に
して切断体Cを形成する。切断体Cの切断面C1、C2
には、導体層Lの断面Lcが露出しており、本例におい
ては、このまま還元雰囲気中で焼成する。これにより配
線基板本体2’が焼結される。この配線基板本体2’
は、図7(a)に示すように、表面2a’および裏面2
b’を有し、両面から内部配線7の端面7s’が露出
し、帯状絶縁部材3a’〜3d’がその幅方向に密着し
て形成され、部材3b’により黒色ストライプ模様が形
成されている。
(Example 2) In Example 1 described above, the laminated body M was cut to form a cut body C, an unfired pad Cp was formed, and then the wiring substrate 1 was formed by simultaneous firing. However, in this example, the pad is formed after firing the cut body C. That is, the cut body C is formed in the same manner as in the first embodiment. Cut surface C1, C2 of cut body C
, The cross section Lc of the conductor layer L is exposed, and in this example, it is fired as it is in a reducing atmosphere. Thereby, the wiring board main body 2 'is sintered. This wiring board body 2 '
As shown in FIG. 7 (a), the front surface 2a 'and the back surface 2a'
b ', the end surfaces 7s' of the internal wiring 7 are exposed from both sides, and the strip-shaped insulating members 3a' to 3d 'are formed in close contact in the width direction thereof, and a black stripe pattern is formed by the members 3b'. .

【0034】ついで、この配線基板本体2’の表面2
a’および裏面2b’をラップ研磨等により研磨する。
これにより、焼成後の配線基板本体2’の反りやうねり
等をなくし、その表面2a’及び裏面2b’を平坦にす
ることができる。なお、この研磨によっても、配線基板
本体2’の帯状絶縁部材3b’の黒色模様は消えること
はない。部材3b’自身が黒色とされているからであ
る。
Next, the surface 2 of the wiring board body 2 '
The a ′ and the back surface 2b ′ are polished by lap polishing or the like.
This makes it possible to eliminate the warpage, undulation, etc. of the wiring board body 2 ′ after firing, and to flatten the front surface 2a ′ and the back surface 2b ′. The black pattern of the band-shaped insulating member 3b 'of the wiring board main body 2' does not disappear even by this polishing. This is because the member 3b 'itself is black.

【0035】ついで、配線基板2’の表面2a’および
裏面2b’にパッド(表面側パッド、裏面側パッド)を
形成する。具体的には、フォトリソグラフィ技術によ
り、両面から露出している内部配線の端面7s’を覆う
ようにして、パッドを形成する。例えば、表面2a’全
面に接続層としてTi−Mo−Cuスパッタ層(厚さ3
00Å−2000Å−2000Å)を形成する。さら
に、フォトレジストを塗布し露光現像して、端面7s上
部を所定形状(例えば100μmφ)に開口させ、スパ
ッタ層を通じて電流を流しCu−Ni−Auメッキ(厚
さ3−2−0.5μm)を施し、レジストおよび不要な
スパッタ層を除去して、表面2a’に表面側パッド5’
を形成する。裏面2b’側にも同様にして裏面側パッド
6’(図示しない)を形成して配線基板1’を完成させ
る(図7(b)参照)。
Next, pads (front side pads, rear side pads) are formed on the front surface 2a 'and the back surface 2b' of the wiring board 2 '. Specifically, a pad is formed by photolithography so as to cover the end face 7s' of the internal wiring exposed from both sides. For example, a Ti-Mo-Cu sputtered layer (thickness 3) is formed on the entire surface 2a 'as a connection layer.
00-2000} -2000}). Further, a photoresist is applied and exposed and developed to open an upper portion of the end face 7s in a predetermined shape (for example, 100 μmφ), and a current is passed through a sputter layer to perform Cu-Ni-Au plating (thickness 3-2-0.5 μm). To remove the resist and the unnecessary sputtered layer, and attach the surface side pad 5 'to the surface 2a'.
To form Similarly, a back surface side pad 6 '(not shown) is formed on the back surface 2b' side to complete the wiring board 1 '(see FIG. 7B).

【0036】このようにすると、配線基板本体2’の表
裏面を一旦研磨してからパッド5’、6’を形成するの
で、パッド5’、6’の上面のコプラナリティが良好と
なり、ICチップや他の配線基板との接続性を向上させ
ることができる。
In this way, the pads 5 'and 6' are formed after the front and back surfaces of the wiring board main body 2 'are polished once, so that the coplanarity of the upper surfaces of the pads 5' and 6 'is improved, and the IC chip and The connectivity with other wiring boards can be improved.

【0037】なお、上記例においては、Ti−Mo−C
uスパッタ層上にCu−Ni−Auメッキ層を積層した
構成のパッドを形成した例を示したが、他の構成によっ
ても良い。また、上記のようにフォトリソグラフィ技術
によってパッドを形成するほか、マスクを用いてパッド
を蒸着等により形成しても良い。さらに、研磨後に、ス
クリーン印刷法により、Ag、Ag−Pd、Ag−P
t,Cu等のペーストを印刷し、800〜1000℃程
度の温度でパッドを焼き付け形成しても良い。この場合
にも、パッド焼き付け温度による本体2’の変形は少な
いので、配線基板本体2’の表裏面2a’、2b’は平
坦にすることができる。また、ICチップの接続はフリ
ップチップ法に限定されず、ワイヤボンディング方式の
構造を採用することもできる。
In the above example, Ti-Mo-C
Although an example is shown in which a pad having a configuration in which a Cu-Ni-Au plating layer is laminated on a u-sputtering layer is shown, another configuration may be used. Further, in addition to forming the pad by the photolithography technique as described above, the pad may be formed by vapor deposition using a mask. Further, after polishing, Ag, Ag-Pd, Ag-P
A pad such as t, Cu or the like may be printed, and the pad may be formed by baking at a temperature of about 800 to 1000 ° C. Also in this case, since the deformation of the main body 2 ′ due to the pad baking temperature is small, the front and back surfaces 2a ′ and 2b ′ of the wiring board main body 2 ′ can be made flat. Further, the connection of the IC chip is not limited to the flip chip method, and a structure of a wire bonding method can be adopted.

【0038】(実施例3)上記実施例1,2において
は、積層体Mを切断して切断体Cを形成した後に焼成し
た例を示した。本実施例3においては、積層体Mを焼成
しその後切断する例を示す。即ち、本例は、積層体Mの
製造までは上記実施例1と同じである(図4(a)参
照)。この積層体Mを還元雰囲気中で焼成し、図8(a)
に示すように、焼結積層体SMを形成する。この焼結積
層体SMにおいては、焼結層Sa、Sb、Sc、Sdの
4層が積層され、このうち焼結層Sbが黒く発色してい
る。
(Embodiment 3) In the above embodiments 1 and 2, the laminated body M was cut to form a cut body C and fired. In the third embodiment, an example will be described in which the multilayer body M is fired and then cut. That is, this example is the same as Example 1 up to the production of the laminate M (see FIG. 4A). This laminate M was fired in a reducing atmosphere, and FIG.
As shown in (1), a sintered laminate SM is formed. In the sintered laminate SM, four sintered layers Sa, Sb, Sc, and Sd are laminated, and the sintered layer Sb is colored black.

【0039】この焼結積層体SMを一点鎖線で示す切断
線Yに沿って所定厚さに切断する。切断方向は、積層体
Mの内部の導体層Lに直交する方向である。これによ
り、図8(b)に示すように、表面2a’および裏面2
b’を有し、両面から内部配線7の端面7s’が露出し
ている配線基板本体2”が形成できた。この手法によれ
ば、焼結積層体SMを形成してから切断するので、切断
体Cを焼結するのとは異なり、焼結に伴う反りやうねり
を生ずることがない。従って、表面及び裏面2a”、2
b”の表面粗さやキズ等が十分小さいならば、そのまま
でパッドを形成することができる。なお、この配線基板
本体2”の表面2a”および裏面2b”をラップ研磨等
により研磨してもよい。この場合においても、本体2”
に反り等がないので、研磨はごくわずかで足り、容易に
研磨できる。その後は、上記実施例2と同様にして、表
面側パッド及び裏面側パッドを形成すればよい。
The sintered laminate SM is cut to a predetermined thickness along a cutting line Y indicated by a dashed line. The cutting direction is a direction orthogonal to the conductor layer L inside the multilayer body M. As a result, as shown in FIG.
The wiring board main body 2 ″ having b ′ and exposing the end surface 7s ′ of the internal wiring 7 from both surfaces was formed. According to this method, the sintered laminate SM was formed and then cut, Unlike the sintering of the cut body C, there is no warping or undulation caused by the sintering.
If the surface roughness and scratches of b ″ are sufficiently small, the pad can be formed as it is. The front surface 2a ″ and back surface 2b ″ of the wiring board body 2 ″ may be polished by lap polishing or the like. . Also in this case, the main body 2 ″
Since there is no warp or the like, the polishing is extremely small and can be easily performed. After that, the front side pad and the back side pad may be formed in the same manner as in the second embodiment.

【図面の簡単な説明】[Brief description of the drawings]

【図1】実施例1にかかる配線基板の斜視図である。FIG. 1 is a perspective view of a wiring board according to a first embodiment;

【図2】実施例1にかかる配線基板の断面図である。FIG. 2 is a cross-sectional view of the wiring board according to the first embodiment.

【図3】実施例1にかかる配線基板の製造方法のうち、
グリーンシートの積層までを説明する説明図である。
FIG. 3 shows a method of manufacturing a wiring board according to the first embodiment;
FIG. 4 is an explanatory diagram illustrating up to lamination of green sheets.

【図4】実施例1にかかる配線基板の製造方法のうち、
切断体の製作までを説明する説明図である。
FIG. 4 is a diagram illustrating a method for manufacturing a wiring board according to the first embodiment;
It is explanatory drawing explaining manufacture of a cut body.

【図5】実施例1にかかる配線基板の製造方法のうち、
未焼成パッドの形成までを説明する説明図である。
FIG. 5 is a diagram illustrating a method for manufacturing a wiring board according to the first embodiment;
FIG. 4 is an explanatory diagram illustrating the steps up to the formation of an unfired pad.

【図6】本発明の配線基板をICチップ及び他の配線基
板と接続した状態を示す断面図である。
FIG. 6 is a cross-sectional view showing a state in which the wiring board of the present invention is connected to an IC chip and another wiring board.

【図7】実施例2にかかる配線基板の製造方法を説明す
る説明図である。
FIG. 7 is an explanatory diagram for explaining the method for manufacturing the wiring board according to the second embodiment;

【図8】実施例3にかかる配線基板の製造方法を説明す
る説明図である。
FIG. 8 is an explanatory diagram for explaining the method of manufacturing the wiring board according to the third embodiment;

【図9】従来の配線基板をICチップ及び他の配線基板
に接続した状態を示す断面図である。
FIG. 9 is a cross-sectional view showing a state in which a conventional wiring board is connected to an IC chip and another wiring board.

【符号の説明】[Explanation of symbols]

1:配線基板 2、2’、2”:配線基板本体 2a:表面 2b:裏面 3a、3b、3c、3d:帯状絶縁部材 5:表面側パッド(第1接続端子) 6:裏面側パッド(第2接続端子) 7:内部配線 1: Wiring board 2, 2 ′, 2 ″: Wiring board main body 2a: Front surface 2b: Back surface 3a, 3b, 3c, 3d: Band-shaped insulating member 5: Front surface side pad (first connection terminal) 6: Back surface side pad (first 2 connection terminals) 7: Internal wiring

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】表面と裏面とを有する平板形状を有し、複
数の帯状絶縁部材をその幅方向に相互に密着させて列設
してなる絶縁部材と、 該絶縁部材の表面に形成された複数の第1接続用端子
と、 上記絶縁部材の裏面に形成され、上記第1接続用端子と
同配置で配置された複数の第2接続用端子と、 上記帯状絶縁部材間に形成され、上記第1接続用端子と
これに対応する第2接続用端子とをそれぞれ表面及び裏
面に垂直な直線状に結ぶ内部配線と、を有する配線基
板。
An insulating member having a flat plate shape having a front surface and a back surface, a plurality of band-shaped insulating members being arranged in close contact with each other in a width direction thereof, and formed on a surface of the insulating member. A plurality of first connection terminals, a plurality of second connection terminals formed on the back surface of the insulating member and arranged in the same arrangement as the first connection terminals, and a plurality of second connection terminals formed between the band-shaped insulating members; A wiring board having an internal wiring that connects a first connection terminal and a corresponding second connection terminal in a straight line perpendicular to the front surface and the back surface, respectively.
【請求項2】前記表面及び裏面のうち少なくともいずれ
かは、研磨面であることを特徴とする請求項1に記載の
配線基板。
2. The wiring board according to claim 1, wherein at least one of the front surface and the rear surface is a polished surface.
【請求項3】前記帯状絶縁部材のうち少なくとも1層以
上の帯状絶縁部材が、他の帯状絶縁部材と異なる色彩を
有することを特徴とする請求項1または2に記載の配線
基板。
3. The wiring board according to claim 1, wherein at least one layer of the band-shaped insulating members has a color different from that of the other band-shaped insulating members.
【請求項4】未焼成絶縁層の表面または裏面の少なくと
もいずれか一方の上に互いに平行な複数の直線状導体層
を形成する工程と、 複数の上記未焼成絶縁層を厚さ方向に積層して積層体を
形成する工程と、 該積層体を直線状導体層に直交する方向に所定の厚さに
切断して未焼成配線基板を形成する工程と、 該未焼成配線基板を焼成する工程と、を有することを特
徴とする配線基板の製造方法。
4. A step of forming a plurality of linear conductor layers parallel to each other on at least one of the front surface and the back surface of the unsintered insulating layer, and laminating the plurality of unsintered insulating layers in a thickness direction. Forming a laminate by cutting the laminate to a predetermined thickness in a direction orthogonal to the linear conductor layer to form a green wiring board; and firing the green wiring board. A method for manufacturing a wiring board, comprising:
【請求項5】未焼成絶縁層の表面または裏面の少なくと
もいずれか一方の上に互いに平行な複数の直線状導体層
を形成する工程と、 複数の上記未焼成絶縁層を厚さ方向に積層して積層体を
形成する工程と、 該積層体を焼成して焼成体を形成する工程と、 該焼成体を直線上導体層に直交する方向に所定の厚さに
切断する工程と、を有することを特徴とする配線基板の
製造方法。
5. A step of forming a plurality of linear conductor layers parallel to each other on at least one of a front surface and a back surface of the unsintered insulating layer, and laminating the plurality of unsintered insulating layers in a thickness direction. Forming a fired body by firing the stacked body, and cutting the fired body to a predetermined thickness in a direction perpendicular to the conductor layer on a straight line. A method for manufacturing a wiring board, comprising:
【請求項6】前記積層された未焼成絶縁層のうち、少な
くとも1つ以上の未焼成絶縁層が焼成後の発色が他とは
異なる異色未焼成絶縁層であり、 前記積層体形成工程において、上記異色未焼成絶縁層を
所定位置に積層することを特徴とする請求項4または5
に記載の配線基板の製造方法。
6. The laminated green insulating layer, wherein at least one or more of the laminated green insulating layers is a non-colored green insulating layer having a different color development after firing from the others. The said different color unsintered insulating layer is laminated | stacked on a predetermined position, The Claim 4 or 5 characterized by the above-mentioned.
3. The method for manufacturing a wiring board according to claim 1.
JP27644197A 1997-09-23 1997-09-23 Wiring board and production thereof Pending JPH1197582A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27644197A JPH1197582A (en) 1997-09-23 1997-09-23 Wiring board and production thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27644197A JPH1197582A (en) 1997-09-23 1997-09-23 Wiring board and production thereof

Publications (1)

Publication Number Publication Date
JPH1197582A true JPH1197582A (en) 1999-04-09

Family

ID=17569476

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27644197A Pending JPH1197582A (en) 1997-09-23 1997-09-23 Wiring board and production thereof

Country Status (1)

Country Link
JP (1) JPH1197582A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8344490B2 (en) 2005-02-18 2013-01-01 Fujitsu Semiconductor Limited Semiconductor device having a high frequency electrode positioned with a via hole

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8344490B2 (en) 2005-02-18 2013-01-01 Fujitsu Semiconductor Limited Semiconductor device having a high frequency electrode positioned with a via hole
US9076789B2 (en) 2005-02-18 2015-07-07 Socionext Inc. Semiconductor device having a high frequency external connection electrode positioned within a via hole

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