JPH10173083A - Wiring board for mounting electronic component and its manufacturing method - Google Patents

Wiring board for mounting electronic component and its manufacturing method

Info

Publication number
JPH10173083A
JPH10173083A JP8325414A JP32541496A JPH10173083A JP H10173083 A JPH10173083 A JP H10173083A JP 8325414 A JP8325414 A JP 8325414A JP 32541496 A JP32541496 A JP 32541496A JP H10173083 A JPH10173083 A JP H10173083A
Authority
JP
Japan
Prior art keywords
insulating
insulating layer
wiring board
electronic component
metallized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8325414A
Other languages
Japanese (ja)
Other versions
JP3725949B2 (en
Inventor
Kazue Akita
和重 秋田
Masahito Morita
雅仁 森田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Niterra Co Ltd
Original Assignee
NGK Spark Plug Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Spark Plug Co Ltd filed Critical NGK Spark Plug Co Ltd
Priority to JP32541496A priority Critical patent/JP3725949B2/en
Publication of JPH10173083A publication Critical patent/JPH10173083A/en
Application granted granted Critical
Publication of JP3725949B2 publication Critical patent/JP3725949B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board wherein an electronic component mounting part on the board surface is flattened and an electronic component can be rigidly fixed, and its manufacturing method, regarding a wiring board on the surface of which an electronic component like an IC chip is mounted. SOLUTION: A wring board 1 for mounting an electronic component has a surface 4a on which an IC chip 2 is mounted, a plurality of insulating layers 4-8 composed of ceramic, and metallized wirings 12 arranged between the insulating layers 4-8. Insulating parts 20 are buried in the following; at least the vicinity of the metallized wirings, 12 which are arranged between the first insulating layer 4 and the second insulating layer 5 adjacent to the layer 4 and positioned just under the mounting part of the IC chip 2, or a part between the wirings 12, or the part between the wirings 12 and the vicinity of the wirings 12. The same kind of ceramic as the insulating layers 4-8 can be used for the insulating parts 20.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、表面上に集積回路
チップ(以下、ICチップともいう)、トランジスタ、コ
ンデンサ等の電子部品を搭載する配線基板とその製造方
法に関し、特にICチップ等を搭載する表面を平坦にし
た配線基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board on which electronic components such as an integrated circuit chip (hereinafter, also referred to as an IC chip), a transistor, and a capacitor are mounted on a surface and a method of manufacturing the same. The present invention relates to a wiring substrate having a flat surface.

【0002】[0002]

【従来の技術】一般に、ICチップを表面上に搭載する
セラミック製の配線基板は、アルミナ等からなるグリー
ンシート上にタングステン、モリブデン等の高融点金属
の導体ペーストをスクリーン印刷等して、所望の回路パ
ターンを有する導体ペースト層を設け、この導体ペース
ト層を有する複数のグリーンシートを積層し圧着した
後、焼成することにより製造されている。一方、近年に
おける小型化、薄肉化の要求に連れて、ICチップ搭載
用配線基板も小型化、薄肉化に対応するため、配線の高
密度化と併せて、ICチップ搭載部の下方の位置にもメ
タライズ配線による導体配線層を設ける構造とすること
がある。
2. Description of the Related Art In general, a ceramic wiring board on which an IC chip is mounted on its surface is formed by printing a conductor paste of a refractory metal such as tungsten or molybdenum on a green sheet made of alumina or the like by screen printing or the like. It is manufactured by providing a conductive paste layer having a circuit pattern, laminating a plurality of green sheets having the conductive paste layer, pressing and bonding, and then firing. On the other hand, in response to the recent demand for miniaturization and thinning, the wiring board for mounting the IC chip has also been required to be smaller and thinner. In some cases, a conductor wiring layer formed of metallized wiring is provided.

【0003】例えば、図4(A)に縦断面図を示すICチ
ップ搭載用配線基板50は、複数のセラミックからなる
絶縁層52〜56を積層してなり、第1の絶縁層52と
第2の絶縁層53との間には、メタライズ配線51が埋
設されている。上記第1の絶縁層52上の周囲には、枠
状の絶縁層55,56が断面で階段状になるよう積層さ
れ、これらに囲まれた第1の絶縁層52の表面52aの
図示しないメタライズ層(所謂ダイアタッチ)上には、I
Cチップを搭載するためのキャビティー58が形成され
る。また、上記枠状の絶縁層55の上面の内周寄りに
は、ICチップとメタライズ配線51等からなる導体配
線層を接続するための接続用パッド59が所要数設けら
れている。
For example, a wiring board 50 for mounting an IC chip, whose longitudinal section is shown in FIG. 4 (A), is formed by laminating a plurality of insulating layers 52 to 56 made of ceramics. A metallized wiring 51 is buried between the insulating layer 53 of FIG. Around the first insulating layer 52, frame-shaped insulating layers 55 and 56 are laminated so as to have a stepped cross section, and a metallized surface (not shown) of the surface 52a of the first insulating layer 52 surrounded by these layers. On the layer (so-called die attach), I
A cavity 58 for mounting the C chip is formed. A required number of connection pads 59 are provided near the inner periphery of the upper surface of the frame-shaped insulating layer 55 to connect the IC chip to the conductor wiring layer including the metallized wiring 51 and the like.

【0004】ところで、このような配線基板50を製造
した場合には、第1の絶縁層52の表面52a上には、
メタライズ配線51が埋された位置の上方にその厚みに
起因する突起57が生じることがある。この突起57
は、第1の絶縁層52が薄い程顕著に生じる傾向があ
る。そして、図4(B)に示すように、第1の絶縁層52
の表面52a上におけるICチップ搭載部分に、例えば
Au−Siのプリフォームされたロウ材62を載置し、その
上面にICチップ60を載置した後、約400℃に加熱
してICチップ60を固着する。ところが、第1の絶縁
層52の表面52a上に前記突起57が存在すると、上
記ICチップ60の固着時に上記突起57間でロウ材6
2中に隙間Sが生じ、ICチップ60の接着が不十分と
なることがある。また、係る隙間Sの発生を防止するた
め、ロウ材62等の使用量を増やす方法もあるが、コス
ト高になるという問題点があった。同様な問題は、ロウ
材のペーストや樹脂系接着剤によってICチップ60を
固着する場合にも生ずる。
By the way, when such a wiring board 50 is manufactured, the surface 52a of the first insulating layer 52 is
A projection 57 due to the thickness of the metallized wiring 51 may be formed above a position where the metallized wiring 51 is buried. This projection 57
Tends to occur more noticeably as the first insulating layer 52 is thinner. Then, as shown in FIG. 4B, the first insulating layer 52 is formed.
For example, on the IC chip mounting portion on the surface 52a of
The brazing material 62 preformed from Au-Si is placed, and the IC chip 60 is placed on the upper surface thereof, and then heated to about 400 ° C. to fix the IC chip 60. However, if the protrusions 57 exist on the surface 52a of the first insulating layer 52, the brazing material 6 between the protrusions 57 when the IC chip 60 is fixed.
In some cases, a gap S is generated in 2 and the adhesion of the IC chip 60 may be insufficient. Further, in order to prevent the generation of the gap S, there is a method of increasing the use amount of the brazing material 62 or the like, but there is a problem that the cost is increased. A similar problem occurs when the IC chip 60 is fixed by a brazing paste or a resin-based adhesive.

【0005】[0005]

【発明が解決すべき課題】本発明は、以上の従来技術に
おける問題点を解決し、上記ICチップやその他の電子
部品の搭載部分における突起を無くすか又は低減して、
ロウ材等の使用量を増やすことなく、その内部に隙間を
生じさせないようにした電子部品搭載用配線基板とその
製造方法を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems in the prior art, and eliminates or reduces projections on the mounting portion of the IC chip and other electronic components.
An object of the present invention is to provide a wiring board for mounting electronic components and a method of manufacturing the same, in which a gap is not generated inside the brazing material without increasing the amount of brazing material used.

【0006】[0006]

【課題を解決するための手段】本発明は、上記課題を解
決するため、電子部品の搭載部分の直下に位置するメタ
ライズ配線の近傍やその配線相互間に別の絶縁体を埋設
することにより、上記搭載部分の表面に突起が生じるこ
とを防ぐことに着想して成されたものである。即ち、本
発明の電子部品搭載用配線基板は、電子部品を搭載する
ための表面を有し、且つ複数のセラミックからなる絶縁
層と、この絶縁層の間に配設されたメタライズ配線とを
有する配線基板であって、上記表面を有する第1の絶縁
層とこれに隣接する第2の絶縁層との間に配設され、且
つ前記電子部品搭載部分の直下に位置するメタライズ配
線の少なくとも近傍、メタライズ配線相互間、又は、メ
タライズ配線相互間及びにメタライズ配線の近傍の何れ
かに、絶縁部を埋設したことを特徴とする。係る構成に
よれば、メタライズ配線の近傍や配線相互間には絶縁部
が埋設されているので、電子部品搭載部分の表面に突起
を生じず、又は極く小さくでき、電子部品を固着するた
めのロウ材等中に隙間が生じることを防止できる。
The present invention solves the above-mentioned problems by embedding another insulator near metallized wiring located immediately below a mounting portion of an electronic component and between the wirings. The present invention has been conceived to prevent a projection from being formed on the surface of the mounting portion. That is, the electronic component mounting wiring board of the present invention has a surface for mounting electronic components, and has an insulating layer made of a plurality of ceramics and a metallized wiring disposed between the insulating layers. A wiring board, disposed between a first insulating layer having the surface and a second insulating layer adjacent thereto and at least near a metallized wiring located immediately below the electronic component mounting portion; An insulating portion is buried between the metallized wirings, or between the metallized wirings and in the vicinity of the metallized wirings. According to such a configuration, since the insulating portion is buried in the vicinity of the metallized wiring and between the wirings, no projection is formed on the surface of the electronic component mounting portion, or it can be made extremely small, so that the electronic component can be fixed. A gap can be prevented from being formed in the brazing material or the like.

【0007】また、前記絶縁部が、前記メタライズ配線
の第1の絶縁層側又は第2の絶縁層側の何れかを覆って
なる電子部品搭載用配線基板も含まれる。係る構成によ
れば、絶縁部とメタライズ配線との間に隙間が無くなる
ので、電子部品搭載部分の表面がより平坦になり、突起
が生じにくくなる。前記絶縁部が、前記表面上の電子部
品搭載部分の直下よりも広く埋設されてなる電子部品搭
載用配線基板も含まれる。この構成によれば、電子部品
搭載部分の表面に突起が確実に生じにくくなり、搭載部
分を含む広い表面が平坦となり、電子部品の搭載がより
容易となる。更に、前記絶縁部が前記絶縁層と同種のセ
ラミックからなる電子部品搭載用配線基板も含まれる。
係る構成によれば、第1、第2の絶縁層と同様な特性
(熱膨張率、熱伝導率)の絶縁部が得られ、基板内が同
種のセラミックにて一体的且つ強固に構成でき、製造も
容易に行うことができる。また、前記第1の絶縁層の厚
さが0.01〜0.65mmの範囲内である配線基板も含ま
れる。この厚さを0.01mm以上としたのは、セラミック
の絶縁層として実質的な最小の厚さであるためであり、
0.65mm以下としたのはこれよりも厚くなると突起が
生じにくくなる傾向が現れるためである。
[0007] The present invention also includes a wiring board for mounting an electronic component, wherein the insulating portion covers either the first insulating layer side or the second insulating layer side of the metallized wiring. According to such a configuration, since there is no gap between the insulating portion and the metallized wiring, the surface of the electronic component mounting portion becomes flatter, and projections are less likely to occur. An electronic component mounting wiring board in which the insulating portion is buried wider than immediately below the electronic component mounting portion on the surface is also included. According to this configuration, it is difficult for projections to be reliably formed on the surface of the electronic component mounting portion, and a wide surface including the mounting portion is flattened, thereby making it easier to mount the electronic component. Further, a wiring board for mounting an electronic component in which the insulating portion is made of the same type of ceramic as the insulating layer is also included.
According to such a configuration, an insulating portion having the same characteristics (coefficient of thermal expansion and thermal conductivity) as the first and second insulating layers can be obtained, and the inside of the substrate can be integrally and firmly formed of the same type of ceramic. Manufacturing can also be easily performed. Also, a wiring board in which the thickness of the first insulating layer is in the range of 0.01 to 0.65 mm is included. The reason why the thickness is set to 0.01 mm or more is that the thickness is substantially the minimum as a ceramic insulating layer.
The reason why the thickness is 0.65 mm or less is that if the thickness is larger than this, there is a tendency that projections are less likely to occur.

【0008】また、本発明は、以上の各配線基板を製造
する方法、即ち、焼成後に前記第1の絶縁層となるグリ
ーンシートの下面又は第2の絶縁層となるグリーンシー
トの上面に、焼成後に前記メタライズ配線となる導体ペ
ースト層を形成した後に、この導体ペースト層のうち少
なくとも前記電子部品搭載部分の直下に位置する部位を
略覆うように絶縁性ペーストを塗布し、この上方に前記
第2の絶縁層又は第1の絶縁層となるグリーンシートを
積層して焼成することを特徴とする電子部品搭載用配線
基板の製造方法も含む。この方法によれば、前記突起の
ない表面、又は極く小さくした表面を有する基板を、僅
かな工程を付加するのみで効率良く生産することができ
る。更に、上記絶縁性ペーストに含有されるセラミック
素材が、第1及び第2の絶縁層となるグリーンシートと
同種のセラミック素材である配線基板の製造方法も含ま
れる。この方法によれば、安価に製造することができ
る。また、絶縁層となるグリーンシートと同様な焼成収
縮率や熱膨張率を持たせることができるので、焼成時に
クラック等の不具合が生じることがなく、更に絶縁層と
絶縁部が一体的且つ強固に接合した配線基板とすること
ができる。
Further, the present invention provides a method of manufacturing each of the above-mentioned wiring boards, that is, a method in which the lower surface of the green sheet which becomes the first insulating layer after firing or the upper surface of the green sheet which becomes the second insulating layer is fired. After forming a conductive paste layer to be the metallized wiring later, an insulating paste is applied so as to substantially cover at least a portion of the conductive paste layer located immediately below the electronic component mounting portion, and the second conductive paste layer is formed thereon. A green sheet to be an insulating layer or a first insulating layer is laminated and fired, and a method for manufacturing a wiring board for mounting electronic components is also included. According to this method, it is possible to efficiently produce a substrate having a surface without the projections or a very small surface by adding only a few steps. Furthermore, the present invention also includes a method of manufacturing a wiring board in which the ceramic material contained in the insulating paste is the same type of ceramic material as the green sheets serving as the first and second insulating layers. According to this method, it can be manufactured at low cost. In addition, since the same firing shrinkage and thermal expansion coefficient as those of the green sheet serving as the insulating layer can be provided, problems such as cracks do not occur during firing, and the insulating layer and the insulating portion are integrally and firmly integrated. A bonded wiring board can be obtained.

【0009】[0009]

【発明の実施の形態】以下に本発明の実施に好適な形態
を図面と共に説明する。図1(A)は、本発明の配線基板
1の表面上にICチップ2を搭載した状態を示す斜視図
である。配線基板1は、全体が略平らな矩形状を呈し、
図1(B)に示すように、セラミックからなる複数の絶縁
層4,5,6と、絶縁層4の表面4aの周囲に階段状に設
けられたセラミックからなる四角枠形状の絶縁層7,8
を一体に積層した本体10を有する。各絶縁層4〜8の
間には、メタライズ配線12等が設けられ、且つこれら
のメタライズ配線の相互間を導通するビア(図示せず)が
各絶縁層4〜8を貫通して形成されている。また、階段
状の絶縁層7の内周面上には、上記導体配線層をICチ
ップ2に金属細線(図示せず)を介して導通するための接
続用パッド9が、各辺に沿って所要数設けられている。
更に、上記絶縁層7,8に囲まれてキャビティ11が形
成される。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1A is a perspective view showing a state in which an IC chip 2 is mounted on the surface of a wiring board 1 of the present invention. The wiring substrate 1 has a substantially flat rectangular shape as a whole,
As shown in FIG. 1B, a plurality of insulating layers 4, 5, 6 made of ceramic and a rectangular frame-shaped insulating layer 7 made of ceramic provided around the surface 4 a of the insulating layer 4 in a stepwise manner. 8
Are integrally laminated. Metallized wirings 12 and the like are provided between the insulating layers 4 to 8, and vias (not shown) that conduct between these metallized wirings are formed through the insulating layers 4 to 8. I have. On the inner peripheral surface of the step-like insulating layer 7, connection pads 9 for conducting the conductor wiring layer to the IC chip 2 via thin metal wires (not shown) are provided along each side. The required number is provided.
Further, a cavity 11 is formed surrounded by the insulating layers 7 and 8.

【0010】例えば、ICチップ2を搭載するための表
面4aを有する第1の絶縁層4と、この下方に隣接する
第2の絶縁層5との間には、予め絶縁層5の図中上面に
設けられたメタライズ配線12における配線12相互間
とその近傍、及び配線12の第1の絶縁層4側を覆って
絶縁部20が埋設されている。尚、表面4aのうち、キ
ャビティ11側に露出している部分には、図示しないメ
タライズ層が形成されている。この絶縁部20は、各絶
縁層4〜8と同種のセラミックからなり、配線12の厚
さと略同様の厚みを有し、且つ、平面視においても、I
Cチップ2の搭載部分の直下よりも広く形成されてい
る。このような絶縁部20を設けることにより、メタラ
イズ配線12によって従来表面4aに発生していた突起
は解消され、表面4aは平坦なICチップ搭載部分を有
するものとなる。従って、表面4a上にNiメッキ及びAu
メッキを施した後、例えばAu−Si系の薄板状にプリフォ
ームされたロウ材22を載せ、その上方からICチップ
2を載置して約400℃に加熱し固着しても、その後の
ロウ材22の内部には隙間が殆ど見られず、ICチップ
2は表面4a上の所定の位置に所定の姿勢にて強固に固
着される。尚、絶縁部20は、表面4aの平坦性に影響
する第1の絶縁層4とこれに隣接する第2の絶縁層5間
の上記メタライズ配線12付近にのみ設けられる。
For example, between the first insulating layer 4 having the surface 4a on which the IC chip 2 is mounted and the second insulating layer 5 adjacent below the first insulating layer 4, the upper surface of the insulating layer 5 in FIG. An insulating portion 20 is buried between the wirings 12 in the metallized wiring 12 provided in the vicinity and in the vicinity thereof, and covers the wiring 12 on the first insulating layer 4 side. It should be noted that a metallized layer (not shown) is formed on a portion of the surface 4a exposed to the cavity 11 side. The insulating portion 20 is made of the same type of ceramic as the insulating layers 4 to 8, has a thickness substantially similar to the thickness of the wiring 12, and has a thickness of I in plan view.
It is formed wider than immediately below the mounting portion of the C chip 2. By providing such an insulating portion 20, the protrusions which have conventionally occurred on the surface 4a due to the metallized wiring 12 are eliminated, and the surface 4a has a flat IC chip mounting portion. Therefore, Ni plating and Au plating on the surface 4a
After plating, for example, a brazing material 22 preformed in the form of a thin plate of Au-Si is placed thereon, and the IC chip 2 is placed from above and heated to about 400 ° C. to fix the soldering material. There is hardly any gap in the inside of the member 22, and the IC chip 2 is firmly fixed at a predetermined position on the surface 4a in a predetermined posture. The insulating portion 20 is provided only in the vicinity of the metallized wiring 12 between the first insulating layer 4 which affects the flatness of the surface 4a and the second insulating layer 5 adjacent thereto.

【0011】次に、配線基板1の製造方法について説明
する。前記各絶縁層4〜8を形成するため、アルミナ等
からなるグリーンシートを用意し、各絶縁層4〜8に応
じて抜き打ち加工等により所定の形状に成形する。次い
で、各グリーンシートの表面にタングステンやモリブデ
ン等の高融点金属又はそれらの合金の粉末を含む導体ペ
ーストをスクリーン印刷によって、所望の導体ペースト
層を形成する。そして、第2の絶縁層5となるグリーン
シートの上面に形成された前記導体ペースト層のうち、
ICチップ搭載部分の直下の導体ペースト層上、導体ペ
ースト層相互間およびその近傍に、グリーンシートと同
様なセラミック素材を用いたアルミナ系の絶縁性ペース
トをスクリーン印刷する。すると、絶縁性ペーストが若
干流動して導体ペースト層上では薄くなり、全体に略同
じ高さを有する絶縁性ペースト層となる。
Next, a method of manufacturing the wiring board 1 will be described. In order to form each of the insulating layers 4 to 8, a green sheet made of alumina or the like is prepared, and is formed into a predetermined shape by punching or the like according to each of the insulating layers 4 to 8. Next, a desired conductive paste layer is formed on the surface of each green sheet by screen printing a conductive paste containing a powder of a high melting point metal such as tungsten or molybdenum or an alloy thereof. Then, of the conductive paste layers formed on the upper surface of the green sheet to be the second insulating layer 5,
Alumina-based insulating paste using a ceramic material similar to the green sheet is screen-printed on the conductor paste layer immediately below the IC chip mounting portion, between the conductor paste layers, and in the vicinity thereof. Then, the insulating paste slightly flows and becomes thin on the conductive paste layer, and becomes an insulating paste layer having substantially the same height as a whole.

【0012】係る各グリーンシートを所定の順序に積層
し圧着すると、上記アルミナ系絶縁性ペースト層は、第
1の絶縁層4となるグリーンシートと第2の絶縁層5と
なるグリーンシートとの間に位置する。その後、焼成す
ると各グリーンシートはセラミックの各絶縁層4〜8に
なり、上記アルミナ系絶縁性ペースト層は絶縁部20に
なると共に、第1の絶縁層4の表面4aが平坦となっ
た、一体のセラミックからなる配線基板1を得ることが
できる。
When the green sheets are laminated and pressed in a predetermined order, the alumina-based insulating paste layer is formed between the green sheet serving as the first insulating layer 4 and the green sheet serving as the second insulating layer 5. Located in. Thereafter, when fired, each green sheet becomes each of the insulating layers 4 to 8 of ceramic, the alumina-based insulating paste layer becomes the insulating portion 20, and the surface 4a of the first insulating layer 4 becomes flat. Can be obtained.

【0013】ここで、本発明の配線基板の効果を従来構
造の配線基板と比較する。前記図1(B)と図4(A)それ
ぞれと同様な断面構造を有する同じアルミナ質からなる
基板1,50を用意し、第1の絶縁層4,52の厚さを
0.25mm、第2の絶縁層5,53を含む他の絶縁層の
厚さを0.5mmとすると共に、第2の絶縁層5,53上
に形成したメタライズ配線12,51の厚さを15μm
とした。また、基板1にはメタライズ配線12を覆うよ
うアルミナからなる絶縁部20を15〜20μmの厚さ
で埋設した。このような基板1,50のICチップ搭載
部分となる表面4a,52aにおける突起の平均高さ
は、各々2μmと12μmであった。また、表面4a,
52aを有する第1の絶縁層4,52の厚さを変化させ
て、各々の表面4a,52aにおける突起の高さを測定
した。その結果を表1に示す。尚、各データは20個ず
つの基板1,50を接触型表面粗さ計で測定した平均値
を示す。
Here, the effects of the wiring board of the present invention will be compared with those of a conventional wiring board. A substrate 1 and 50 made of the same alumina and having the same cross-sectional structure as those of FIGS. 1B and 4A are prepared, and the thickness of the first insulating layers 4 and 52 is 0.25 mm. The thickness of the other insulating layers including the second insulating layers 5 and 53 is 0.5 mm, and the thickness of the metallized wirings 12 and 51 formed on the second insulating layers 5 and 53 is 15 μm.
And An insulating portion 20 made of alumina was embedded in the substrate 1 so as to cover the metallized wiring 12 with a thickness of 15 to 20 μm. The average heights of the protrusions on the surfaces 4a and 52a serving as the IC chip mounting portions of the substrates 1 and 50 were 2 μm and 12 μm, respectively. Also, the surface 4a,
By changing the thickness of the first insulating layers 4 and 52 having 52a, the heights of the protrusions on the respective surfaces 4a and 52a were measured. Table 1 shows the results. Each data shows an average value of 20 substrates 1 and 50 measured by a contact type surface roughness meter.

【0014】[0014]

【表1】 [Table 1]

【0015】表1の結果から、本発明の基板1における
突起の高さは、2〜3μmの極く微小な範囲となったの
に対し、比較例の基板50における突起の高さは、2〜
15μmの範囲となり、且つ、その第1の絶縁層52の
厚さが薄くなる程高くなる傾向を示した。これは、両者
共に第1の絶縁層4,52が薄い程、前記メタライズ配
線12,51の影響を受けやすいことによる。しかし、
本発明の基板1では第1の絶縁層4が薄くても突起の高
さは微小となるのに対し、比較例の基板50では第1の
絶縁層52が薄くなると急激に突起が高くなっている。
このことからも、基板1中に前記絶縁部20を埋設する
ことによって、表面4aが平坦化されたことが明らかで
ある。尚、第1の絶縁層4,52が0.80mmと厚い場合、
両者共に突起の高さは2μmと低い値なった。これは、
第1の絶縁層4,52が前記メタライズ配線12,51
による影響を吸収したものと思われる。このことから、
本発明の絶縁部20を設けてその効果が得られるのは、
第1の絶縁層4の厚さが0.65mm以下であることも理
解される。
From the results shown in Table 1, the height of the projections on the substrate 1 of the present invention was in a very small range of 2 to 3 μm, whereas the height of the projections on the substrate 50 of the comparative example was 2 μm. ~
The thickness of the first insulating layer 52 tended to be higher as the thickness of the first insulating layer 52 became thinner. This is because both are more susceptible to the influence of the metallized wirings 12 and 51 as the first insulating layers 4 and 52 are thinner. But,
In the substrate 1 of the present invention, the height of the projections becomes very small even if the first insulating layer 4 is thin, whereas in the substrate 50 of the comparative example, when the first insulating layer 52 becomes thin, the projections increase rapidly. I have.
From this, it is apparent that the surface 4a was flattened by burying the insulating portion 20 in the substrate 1. When the first insulating layers 4 and 52 are as thick as 0.80 mm,
In both cases, the height of the protrusion was as low as 2 μm. this is,
The first insulating layers 4, 52 are formed by the metallized wirings 12, 51.
It seems that the effects of the absorption were absorbed. From this,
The effect of providing the insulating portion 20 of the present invention is as follows.
It is also understood that the thickness of the first insulating layer 4 is 0.65 mm or less.

【0016】尚、配線基板1の前記接続用パッド9やキ
ャビティ11内の表面4aの図示しないメタライズ層上
にはNiメッキを施した後、更にAuメッキを施す。係る
メッキが施された配線基板1のキァビティ11内の表面
4a上におけるICチップ2の搭載部分には、所定厚さ
のAu−Si系の薄板状のロウ材22が載置され、その上に
ICチップ2を載置した後、約400℃に加熱してIC
チップ2を固着する。その後、前記接続パッド9とIC
チップ2とを金属細線を介して接続し、最後にICチッ
プ2を封止するため、本体10最上段の絶縁層8の上面
全体を覆うように金属又はセラミック製の蓋(図示せず)
が半田付け等により接着され、所謂半導体装置となる。
The metallization layer (not shown) on the connection pads 9 of the wiring board 1 and the surface 4a in the cavity 11 is plated with Ni and then with Au plating. On the mounting portion of the IC chip 2 on the surface 4a in the cavity 11 of the plated wiring board 1 on which the plating is applied, an Au-Si-based thin brazing material 22 having a predetermined thickness is placed. After placing the IC chip 2, it is heated to about 400 ° C.
The chip 2 is fixed. Then, the connection pad 9 and the IC
In order to connect the chip 2 via a thin metal wire and finally seal the IC chip 2, a metal or ceramic lid (not shown) is provided so as to cover the entire upper surface of the insulating layer 8 at the uppermost stage of the main body 10.
Are bonded by soldering or the like to form a so-called semiconductor device.

【0017】ここで、本発明と従来構造の配線基板1,
50のロウ材22,62中の隙間を比較する。同じ高さ
の突起を有する基板1,50を各々について3個ずつ用
意し、前記と同じ条件で各表面4a,52a上に一辺1
0mm角のICチップ2を、厚さ25μmで一辺7mm角の
Au−Si系のロウ材プリフォームを用いて固着した。次い
で、これらの各ロウ材22,62中に存在する隙間Sを
超音波探査映像装置を用いて、各ロウ材22,62中に
全隙間Sが存在する面積比を空孔率として測定し、平均
値を算出した。その結果を表2に示す。
Here, the wiring board 1 of the present invention and the conventional structure,
The gaps in the 50 brazing materials 22, 62 are compared. Three substrates 1 and 50 each having projections having the same height are prepared, and one side is formed on each of the surfaces 4a and 52a under the same conditions as described above.
A 0 mm square IC chip 2 having a thickness of 25 μm and a side of 7 mm square
It was fixed using an Au-Si brazing material preform. Next, the gap S existing in each of the brazing materials 22 and 62 was measured using an ultrasonic exploration imaging apparatus, and the area ratio where the entire gap S was present in each of the brazing materials 22 and 62 was measured as a porosity. The average was calculated. Table 2 shows the results.

【0018】[0018]

【表2】 [Table 2]

【0019】表2の結果から、本発明の基板1を用いた
場合の空孔率は5〜10%であったのに対し、比較例の
基板50を用いた場合の空孔率は35〜50%と、前者
の方が約3分の一乃至7分の一と少ない。この結果から
本発明の基板1を用いた場合、ICチップ2を強固に固
着できることが容易に理解することができる。また、表
2は、基板1,50の各表面4a,52aにおける突起
が低い程、空孔率が低いことも示しており、これからも
本発明の意義と効果が理解されよう。尚、絶縁性ペース
トの粘度やスクリーンマスク(或いはメタルマスク)の厚
さ等を調整することにより、絶縁性ペースト層による絶
縁部20の厚みを調整することができる。
From the results shown in Table 2, the porosity was 5 to 10% when the substrate 1 of the present invention was used, whereas the porosity was 35 to 10% when the substrate 50 of the comparative example was used. The former is 50%, about one third to one seventh smaller. From this result, it can be easily understood that when the substrate 1 of the present invention is used, the IC chip 2 can be firmly fixed. Table 2 also shows that the lower the protrusions on the surfaces 4a and 52a of the substrates 1 and 50, the lower the porosity, and the significance and effects of the present invention will be understood from now on. The thickness of the insulating portion 20 made of the insulating paste layer can be adjusted by adjusting the viscosity of the insulating paste, the thickness of the screen mask (or metal mask), and the like.

【0020】図2(A)は、図1(B)中の部分拡大図を示
し、第2の絶縁層5上面のメタライズ配線12と絶縁部
20のうちメタライズ配線12の間に位置する部分の厚
さとが略同じ厚さとされており、従ってメタライズ配線
12の頂部付近の絶縁部20の厚さは極く薄くされて埋
設されている。一方、図2(B)に示すように、メタライ
ズ配線12の頂部付近も比較的厚く覆うように絶縁部2
0全体をより厚くして埋設すると、第1の絶縁層4の表
面4aを確実に平坦化することができる。但し、逆に絶
縁部20のうちメタライズ配線12の間に位置する部分
の厚さを、メタライズ配線12の厚さよりもやや薄くし
ても、表面4a上に生じる突起を低くすることができ
る。
FIG. 2A is a partially enlarged view of FIG. 1B, and shows the metallized wiring 12 on the upper surface of the second insulating layer 5 and the portion of the insulating portion 20 located between the metallized wiring 12. The thickness of the insulating portion 20 near the top of the metallized wiring 12 is extremely small and is buried. On the other hand, as shown in FIG. 2B, the insulating portion 2 is formed so as to cover the vicinity of the top of the metallized wiring 12 relatively thickly.
By burying the entirety 0, the surface 4a of the first insulating layer 4 can be reliably flattened. However, on the contrary, even if the thickness of the portion of the insulating portion 20 located between the metallized wirings 12 is slightly smaller than the thickness of the metallized wirings 12, the protrusions generated on the surface 4a can be reduced.

【0021】また、図2(C)に示すように、メタライズ
配線12の相互間や配線12の近傍(図中、左端や右端
部分)にのみ絶縁性ペーストを塗布して絶縁部20を形
成しても、同様に突起を低くし、或いは無くすことがで
きる。但し、絶縁性ペーストの印刷パターンが複雑にな
り、位置合わせが煩雑になる点で不利であるが、ペース
トの使用量を節約できる利点がある。更に、外側のメタ
ライズ配線12がICチップ搭載部分の輪郭と略一致す
る場合には、図2(D)に示すように、メタライズ配線1
2の相互間にのみ絶縁部20を設けても良い。
As shown in FIG. 2C, an insulating paste is applied only between the metallized wirings 12 and in the vicinity of the wirings 12 (left and right ends in the drawing) to form an insulating part 20. However, similarly, the protrusion can be lowered or eliminated. However, this is disadvantageous in that the printing pattern of the insulating paste becomes complicated and the alignment becomes complicated, but there is an advantage that the amount of the paste used can be saved. Further, when the outer metallized wiring 12 substantially matches the contour of the IC chip mounting portion, as shown in FIG.
The insulating portion 20 may be provided only between the two.

【0022】図3は、異なる形態の配線基板30の縦断
面図を示し、前記同様の第1の絶縁層32の下面にメタ
ライズ配線36を形成し、これを覆うように絶縁部40
を第1の絶縁層32と第2の絶縁層34との間に埋設し
たものである。即ち、第1の絶縁層32となるグリーン
シートの下面に印刷にてメタライズ配線36となる導体
ペースト層を形成し、これを覆うように同種のセラミッ
クの絶縁性ペーストを印刷した後、第2の絶縁層34と
なる他のグリーンシートと積層して圧着し焼成すると、
メタライズ配線36と絶縁部40は、図示のように第1
の絶縁層32と第2の絶縁層34との間に位置した状態
となり、各絶縁層32,34は絶縁部40と共に一体化
されたセラミックの配線基板30となる。この配線基板
30における第1の絶縁層32の表面33aは、絶縁部
40がメタライズ配線36を覆うため平坦化される。従
って、表面33a上の図示しないメタライズ層にNiメッ
キ及びAuメッキを施した後、ロウ材22を用いてICチ
ップ2を接着すると、係るロウ材22中に隙間が少ない
強固な固着状態を得ることができる。
FIG. 3 is a longitudinal sectional view of a wiring board 30 having a different form. A metallized wiring 36 is formed on the lower surface of the same first insulating layer 32 as described above, and an insulating section 40 is formed so as to cover the metallized wiring 36.
Is buried between the first insulating layer 32 and the second insulating layer 34. That is, a conductive paste layer serving as the metallized wiring 36 is formed on the lower surface of the green sheet serving as the first insulating layer 32 by printing, and an insulating paste of the same type of ceramic is printed so as to cover the same. When laminated with another green sheet to be the insulating layer 34, pressed and fired,
The metallized wiring 36 and the insulating portion 40 are connected to the first
Is located between the insulating layer 32 and the second insulating layer 34, and the insulating layers 32 and 34 become the ceramic wiring board 30 integrated with the insulating portion 40. The surface 33a of the first insulating layer 32 in the wiring board 30 is flattened because the insulating portion 40 covers the metallized wiring. Accordingly, when the IC chip 2 is adhered to the metallized layer (not shown) on the surface 33a using the brazing material 22 after the Ni plating and the Au plating are performed, a strong fixed state with few gaps in the brazing material 22 is obtained. Can be.

【0023】尚、以上の実施の各形態においては、1つ
のICチップを基板の表面に搭載するタイプの所謂シン
グルチップタイプの配線基板を例として説明したが、本
発明はこれに限定されるものではない。即ち、複数個の
ICチップを固着して用いるマルチチップモジュールに
も適用することができるし、更には、トランジスタ、F
ET等の半導体素子やコンデンサ、抵抗、インダクタ、
SAWフィルタ、その他の電子部品を表面に搭載する場
合であっても良いことは明らかである。
In each of the above embodiments, a so-called single-chip type wiring board in which one IC chip is mounted on the surface of the board has been described as an example. However, the present invention is not limited to this. is not. That is, the present invention can be applied to a multi-chip module in which a plurality of IC chips are fixedly used.
Semiconductor elements such as ET, capacitors, resistors, inductors,
It is clear that a SAW filter and other electronic components may be mounted on the surface.

【0024】更に、配線基板を構成するセラミックとし
て、アルミナを主成分とするものを用いた例を示した
が、これに限定されず、例えば窒化アルミニウム(Al
N)やガラスセラミック、ムライト等、配線基板を構成
できるものであれば、特に限定されない。また、メタラ
イズ配線についても、使用するセラミックの材質に適合
したものを使用すれば良いし、例示したMoやW等の
他、Mo-Mn,Ag,Cu,Ag-Pd,Ag-Ptその他の
材質を用いても良い。
Further, an example was shown in which a ceramic comprising alumina as a main component was used as the ceramic constituting the wiring board. However, the present invention is not limited to this.
There is no particular limitation as long as it can constitute a wiring board, such as N), glass ceramic, mullite, and the like. Also, the metallized wiring may be made of a material suitable for the ceramic material to be used. In addition to the exemplified Mo and W, Mo-Mn, Ag, Cu, Ag-Pd, Ag-Pt and other materials May be used.

【0025】絶縁性ペーストとして絶縁層となるグリー
ンシートと同様なアルミナ系ペーストを用い、従って絶
縁部としてもアルミナを主成分とするものとなる例を示
したが、使用する絶縁層の材質によって適宜選択すれば
良い。即ち、例えば絶縁層がAlNを主体とするセラミ
ックで構成される場合には、絶縁性ペーストもAlNを
主成分とするペーストを用いるのが良いが、これに限定
されず、焼成収縮、熱膨張率その他を考慮して、絶縁層
と異なる材質の絶縁性ペーストを用いることも可能であ
る。
An example in which an alumina paste similar to a green sheet to be an insulating layer is used as the insulating paste, and thus the insulating portion is mainly composed of alumina, but the insulating paste may be appropriately changed depending on the material of the insulating layer to be used. Just choose. That is, for example, when the insulating layer is made of a ceramic mainly composed of AlN, it is preferable to use a paste mainly composed of AlN as the insulating paste. In consideration of others, it is also possible to use an insulating paste of a material different from that of the insulating layer.

【0026】更に、前述した形態においては、ICチッ
プをAu−Si系のロウ材で固着した場合を示したが、
これに限定されるものではなく、Au−Sn,Au−G
e,Pd−Sn系等のロウ材(半田材)や、エポキシ樹脂
等の樹脂系接着剤でICチップやその他の電子部品を固
着する場合においても適用できる。また、Au−Si系
のロウ材として、プリフォームされた薄板材を用いた例
を示したが、ペースト状のロウ材(半田材)や樹脂系接着
剤を用いても良い。
Further, in the above-described embodiment, the case where the IC chip is fixed with the Au-Si brazing material has been described.
The present invention is not limited to this, and Au-Sn, Au-G
e, Pd-Sn-based brazing material (solder material), or a resin-based adhesive such as epoxy resin can be used to fix IC chips and other electronic components. Further, although an example in which a preformed thin plate material is used as the Au-Si brazing material has been described, a paste brazing material (solder material) or a resin-based adhesive may be used.

【0027】[0027]

【発明の効果】以上において説明した本発明の電子部品
搭載用配線基板によれば、第1の絶縁層の表面上におけ
る電子部品搭載部分に、突起がないか、極く低い突起の
みしかない平坦な表面を得ることができるので、ロウ材
等を用いて電子部品を固着してもこのロウ材等中の隙間
を大幅に低減でき、電子部品を強固で且つ適正な姿勢に
て搭載することができる。また、請求項4及び7の発明
によれば、絶縁部と絶縁層とが同じ種類のセラミックに
て形成でき、基板の本体自体も強固に構成することがで
きる。更に、請求項6の製造方法によれば、上記配線基
板を僅かの工程を付すのみで、確実且つ大量に生産する
ことができる。
According to the electronic component mounting wiring board of the present invention described above, the electronic component mounting portion on the surface of the first insulating layer has no projections or has only very low projections. Since a special surface can be obtained, even if an electronic component is fixed using a brazing material, the gap in the brazing material can be significantly reduced, and the electronic component can be mounted in a strong and appropriate posture. it can. According to the fourth and seventh aspects of the present invention, the insulating portion and the insulating layer can be formed of the same type of ceramic, and the main body of the substrate itself can be firmly configured. Further, according to the manufacturing method of the sixth aspect, the wiring substrate can be reliably and mass-produced with only a few steps.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(A)はICチップを搭載した本発明の配線基板
の斜視図、(B)は(A)中のB−B断面図である。
FIG. 1A is a perspective view of a wiring board of the present invention on which an IC chip is mounted, and FIG. 1B is a sectional view taken along line BB in FIG.

【図2】(A)は図1(B)中の部分拡大図、(B)乃至(D)
は異なる形態の部分拡大図である。
2A is a partially enlarged view of FIG. 1B, and FIGS.
FIG. 3 is a partially enlarged view of a different form.

【図3】本発明の配線基板の異なる形態を示す縦断面図
である。
FIG. 3 is a longitudinal sectional view showing a different form of the wiring board of the present invention.

【図4】(A)は従来の配線基板を示す縦断面図、(B)は
(A)中の部分拡大図である。
4A is a longitudinal sectional view showing a conventional wiring board, and FIG.
It is the elements on larger scale in (A).

【符号の説明】[Explanation of symbols]

1,30……………………配線基板 2……………………………ICチップ 4,32……………………第1の絶縁層 4a,33a………………表面 5,34……………………第2の絶縁層 6,7,8……………………絶縁層 12,36…………………メタライズ配線 20,40…………………絶縁部 1, 30 Wiring board 2 IC chip 4, 32 IC chip 4, 32 First insulating layer 4a, 33a ...... Surface 5, 34 ...... Second insulating layer 6, 7, 8 ... Insulating layer 12, 36 ... Metallized wiring 20, 40 ... ............ Insulation part

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】電子部品を搭載するための表面を有し、且
つ複数のセラミックからなる絶縁層と、この絶縁層の間
に配設されたメタライズ配線とを有する配線基板であっ
て、 上記表面を有する第1の絶縁層とこれに隣接する第2の
絶縁層との間に配設され、且つ前記電子部品搭載部分の
直下に位置するメタライズ配線の少なくとも近傍、メタ
ライズ配線相互間、又は、メタライズ配線相互間及びメ
タライズ配線の近傍の何れかに、絶縁部を埋設したこと
を特徴とする電子部品搭載用配線基板。
1. A wiring board having a surface for mounting electronic components and having an insulating layer made of a plurality of ceramics and metallized wiring disposed between the insulating layers. Disposed between the first insulating layer and the second insulating layer adjacent thereto and at least near the metallized wirings located immediately below the electronic component mounting portion, between the metallized wirings, or between the metallized wirings A wiring board for mounting electronic components, wherein an insulating portion is buried between wirings or in the vicinity of metallized wirings.
【請求項2】前記絶縁部が、前記メタライズ配線の第1
の絶縁層側又は第2の絶縁層側の何れかを覆って設けら
れてなることを特徴とする請求項1に記載の電子部品搭
載用配線基板。
2. The method according to claim 1, wherein the insulating portion is a first metallized wiring.
2. The electronic component mounting wiring board according to claim 1, wherein the wiring board is provided so as to cover either the insulating layer side or the second insulating layer side.
【請求項3】前記絶縁部が、前記表面上の電子部品搭載
部分の直下よりも広く埋設されてなることを特徴とする
請求項1又は2に記載の電子部品搭載用配線基板。
3. The electronic component mounting wiring board according to claim 1, wherein the insulating portion is buried wider than immediately below the electronic component mounting portion on the surface.
【請求項4】前記絶縁部が前記絶縁層と同種のセラミッ
クからなることを特徴とする請求項1乃至3の何れかに
記載の電子部品搭載用配線基板。
4. The wiring board for mounting electronic components according to claim 1, wherein said insulating portion is made of the same type of ceramic as said insulating layer.
【請求項5】前記第1の絶縁層の厚さが0.01〜0.6
5mmの範囲内であることを特徴とする請求項1乃至4の
何れかに記載の電子部品搭載用配線基板。
5. The method according to claim 1, wherein said first insulating layer has a thickness of 0.01 to 0.6.
The wiring board for mounting electronic components according to any one of claims 1 to 4, wherein the distance is within a range of 5 mm.
【請求項6】請求項1乃至5に記載の配線基板の製造方
法であって、 焼成後に前記第1の絶縁層となるグリーンシートの下面
又は第2の絶縁層となるグリーンシートの上面に、焼成
後に前記メタライズ配線となる導体ペースト層を形成し
た後に、この導体ペースト層のうち少なくとも前記電子
部品搭載部分の直下に位置する部位を略覆うように絶縁
性ペーストを塗布し、この上方に前記第2の絶縁層又は
第1の絶縁層となるグリーンシートを積層して焼成する
ことを特徴とする電子部品搭載用配線基板の製造方法。
6. The method for manufacturing a wiring board according to claim 1, wherein a lower surface of the green sheet serving as the first insulating layer or an upper surface of the green sheet serving as the second insulating layer after firing is provided. After forming a conductive paste layer to be the metallized wiring after firing, an insulating paste is applied so as to substantially cover at least a portion of the conductive paste layer located immediately below the electronic component mounting portion, and the insulating paste is applied thereon. 2. A method for manufacturing a wiring board for mounting electronic components, comprising laminating and firing a second insulating layer or a green sheet to be a first insulating layer.
【請求項7】前記絶縁性ペーストに含有されるセラミッ
ク素材が、前記第1及び第2の絶縁層となるグリーンシ
ートと同種のセラミック素材であることを特徴とする請
求項6に記載の電子部品搭載用配線基板の製造方法。
7. The electronic component according to claim 6, wherein the ceramic material contained in the insulating paste is the same type of ceramic material as the green sheets serving as the first and second insulating layers. Manufacturing method of mounting wiring board.
JP32541496A 1996-12-05 1996-12-05 Semiconductor element housing base and method of manufacturing the same Expired - Fee Related JP3725949B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32541496A JP3725949B2 (en) 1996-12-05 1996-12-05 Semiconductor element housing base and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32541496A JP3725949B2 (en) 1996-12-05 1996-12-05 Semiconductor element housing base and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH10173083A true JPH10173083A (en) 1998-06-26
JP3725949B2 JP3725949B2 (en) 2005-12-14

Family

ID=18176587

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32541496A Expired - Fee Related JP3725949B2 (en) 1996-12-05 1996-12-05 Semiconductor element housing base and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP3725949B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002299102A (en) * 2001-03-29 2002-10-11 Koa Corp Chip resistor
JP2006086225A (en) * 2004-09-14 2006-03-30 Murata Mfg Co Ltd Ceramic multilayer board
US7745734B2 (en) 2005-05-12 2010-06-29 Murata Manufacturing Co., Ltd. Ceramic multilayer substrate
CN108461453A (en) * 2017-02-22 2018-08-28 京瓷株式会社 Electronic component mounting substrate, electronic device and electronic module
JP2018200976A (en) * 2017-05-29 2018-12-20 京セラ株式会社 Electronic element mounting substrate, electronic device, and electronic module

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002299102A (en) * 2001-03-29 2002-10-11 Koa Corp Chip resistor
JP2006086225A (en) * 2004-09-14 2006-03-30 Murata Mfg Co Ltd Ceramic multilayer board
JP4599951B2 (en) * 2004-09-14 2010-12-15 株式会社村田製作所 Ceramic multilayer substrate
US7745734B2 (en) 2005-05-12 2010-06-29 Murata Manufacturing Co., Ltd. Ceramic multilayer substrate
CN108461453A (en) * 2017-02-22 2018-08-28 京瓷株式会社 Electronic component mounting substrate, electronic device and electronic module
JP2018200976A (en) * 2017-05-29 2018-12-20 京セラ株式会社 Electronic element mounting substrate, electronic device, and electronic module

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Publication number Publication date
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