JP4599951B2 - Ceramic multilayer substrate - Google Patents

Ceramic multilayer substrate Download PDF

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JP4599951B2
JP4599951B2 JP2004267367A JP2004267367A JP4599951B2 JP 4599951 B2 JP4599951 B2 JP 4599951B2 JP 2004267367 A JP2004267367 A JP 2004267367A JP 2004267367 A JP2004267367 A JP 2004267367A JP 4599951 B2 JP4599951 B2 JP 4599951B2
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cavity
electrode
multilayer substrate
ceramic multilayer
die bond
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浩二 田中
博之 川端
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Murata Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Description

本発明は、セラミック多層基板に関し、詳しくは、多層基板本体の少なくとも一方の主面に、チップ部品が収容されるキャビティが形成された構造を有するセラミック多層基板に関する。   The present invention relates to a ceramic multilayer substrate, and more particularly to a ceramic multilayer substrate having a structure in which a cavity for accommodating a chip component is formed on at least one main surface of a multilayer substrate body.

近年、電子機器の小型化に伴い、高密度配線や回路要素の高密度実装などに対応することが可能なセラミック多層基板が広く用いられるようになっている。   In recent years, with the miniaturization of electronic equipment, ceramic multilayer substrates that can cope with high-density wiring and high-density mounting of circuit elements have been widely used.

そして、このようなセラミック多層基板の一つに、図６に示すように、多層基板本体５１の一方主面にキャビティ５２を形成し、その中にＩＣチップや弾性表面波フィルタなどのチップ部品５３を配設するようにしたセラミック多層基板がある（特許文献１参照）。   Then, as shown in FIG. 6, a cavity 52 is formed in one main surface of the multilayer substrate body 51 in one of such ceramic multilayer substrates, and a chip component 53 such as an IC chip or a surface acoustic wave filter is formed therein. There is a ceramic multilayer substrate in which is disposed (see Patent Document 1).

なお、チップ部品５３は、例えば、図７に模式的に示すように（図７では図６とは上下を逆にして示している）、ダイボンディングによりキャビティ５２の底面５７に配設されたダイボンド電極５４に接合固定されるとともに、ワイヤボンディングによりワイヤ５６を介して、キャビティ５２内のワイヤボンディング面５８に配設されたランド５５に電気的に接続される。   The chip component 53 is, for example, a die bond disposed on the bottom surface 57 of the cavity 52 by die bonding, as schematically shown in FIG. 7 (shown in FIG. 7 upside down from FIG. 6). It is bonded and fixed to the electrode 54 and is electrically connected to a land 55 disposed on a wire bonding surface 58 in the cavity 52 through a wire 56 by wire bonding.

このように、キャビティ５２内にチップ部品５３を収容するように構成されたセラミック多層基板においては、チップ部品５３をキャビティ５２内に収容することにより、搭載部品（チップ部品）の実装密度や実装信頼性を向上させることが可能になるとともに、突出部が少なくて外部との干渉によるチップ部品の脱落や破損などが生じにくく、かつ、取扱性や実装性に優れたセラミック多層基板を得ることが可能になる。   As described above, in the ceramic multilayer substrate configured to accommodate the chip component 53 in the cavity 52, by mounting the chip component 53 in the cavity 52, the mounting density and the mounting reliability of the mounted component (chip component) are reduced. It is possible to obtain a ceramic multilayer substrate that has few protrusions and is unlikely to cause chipping or damage due to interference with the outside, and that is excellent in handling and mounting. become.

しかしながら、上述のようなキャビティ５２を備えたセラミック多層基板においては、製造工程で、セラミックグリーンシートと導体ペーストから形成されたグリーン積層体を焼成する際に、セラミック部分と導体部分との収縮率が異なることに起因して、キャビティ５２の底面５７に反りやうねりが発生し、チップ部品５３の搭載信頼性を損なうという問題点があり、また、セラミック多層基板全体の反りや歪みを引き起こす原因になるという問題点がある。   However, in the ceramic multilayer substrate provided with the cavity 52 as described above, when the green laminate formed from the ceramic green sheet and the conductor paste is fired in the manufacturing process, the shrinkage ratio between the ceramic portion and the conductor portion is low. Due to the difference, the bottom surface 57 of the cavity 52 is warped and undulated, and there is a problem that the mounting reliability of the chip component 53 is impaired, and the entire ceramic multilayer substrate is warped and distorted. There is a problem.

すなわち、図７に示すように、多層基板本体５１に形成されたキャビティ５２の底面（ダイボンディング面）５７に反りやうねりが生じ、平坦性（平滑性）が損なわれていると、チップ部品５３の搭載時（ダイボンディング時）に、チップ部品５３が傾いて実装され、場合によっては、チップ部品５３が損傷するというような問題点があり、さらに、チップ部品５３が傾いた状態で搭載されると、ワイヤボンディング時に、ワイヤ５６の切断、チップ部品５３の倒れ、ワイヤ５６のキャビティ５２からの露出などの不具合を生じるというような問題点がある。
特開２００４−１０３６０８号公報 That is, as shown in FIG. 7, when the bottom surface (die bonding surface) 57 of the cavity 52 formed in the multilayer substrate body 51 is warped or undulated, and the flatness (smoothness) is impaired, the chip component 53 In mounting (die bonding), the chip component 53 is tilted and mounted, and in some cases, the chip component 53 is damaged, and the chip component 53 is mounted in a tilted state. At the time of wire bonding, there are problems such as cutting of the wire 56, tipping of the chip part 53, and exposure of the wire 56 from the cavity 52.
JP 2004-103608 A

本発明は、上記課題を解決するものであり、多層基板本体の少なくとも一方主面にチップ部品が収容されるキャビティを備えたセラミック多層基板において、キャビティの底面に反りやうねりがなく、チップ部品の搭載安定性などが良好で、信頼性の高いセラミック多層基板を提供することを課題とする。   The present invention solves the above-described problems, and in a ceramic multilayer substrate having a cavity in which a chip component is accommodated in at least one main surface of the multilayer substrate body, the bottom surface of the cavity is free from warping and undulation, and It is an object of the present invention to provide a ceramic multilayer substrate with favorable mounting stability and high reliability.

上記課題を解決するために、本発明（請求項１）のセラミック多層基板は、
少なくとも一方の主面に、チップ部品を収容するキャビティが形成された多層基板本体と、
キャビティの底面に配設されたダイボンド電極と、
キャビティ内に配設され、前記ダイボンド電極に接合固定されるとともに、多層基板本体が備える配線導体と電気的に接続されたチップ部品と
を具備するセラミック多層基板であって、
前記ダイボンド電極が複数に分割された構造を有するとともに、前記キャビティの底面の中央領域には前記ダイボンド電極を構成する電極が配設されていない無電極領域が形成されていること
前記ダイボンド電極が複数に分割された構造を有していること
を特徴としている。 In order to solve the above problems, the ceramic multilayer substrate of the present invention (Claim 1)
A multilayer substrate body in which a cavity for accommodating chip components is formed on at least one main surface;
A die bond electrode disposed on the bottom surface of the cavity;
A ceramic multilayer substrate that is disposed in a cavity and is bonded and fixed to the die bond electrode, and includes a chip component that is electrically connected to a wiring conductor included in the multilayer substrate body,
As well as have the said die bonding electrode is divided into a plurality structure, the die bonding electrodeless region where the electrode is not disposed to the electrodes constituting the has been formed Rukoto the die bonding electrode in the central region of the bottom surface of the cavity It is characterized by having a structure divided into multiple parts.

また、請求項２のセラミック多層基板は、前記ダイボンド電極を構成する、複数に分割された電極のそれぞれが略同一の面積を有していることを特徴としている。   The ceramic multilayer substrate according to claim 2 is characterized in that each of the plurality of divided electrodes constituting the die bond electrode has substantially the same area.

また、請求項３のセラミック多層基板は、キャビティの底面の形状が矩形であり、前記底面を縦３列、横３列となるように９分割した領域のうち、中央領域を除いた８領域に、前記ダイボンド電極が分割して配設されていることを特徴としている。 The ceramic multilayer substrate according to claim 3 has a shape of a bottom surface of the cavity that is rectangular, and is divided into nine regions excluding the central region among the nine regions divided so that the bottom surface has three rows and three rows. The die bond electrodes are divided and arranged .

本発明（請求項１）のセラミック多層基板は、キャビティの底面に配設されたダイボンド電極を、複数に分割しているので、焼成工程でセラミック部分と電極部分（導体部分）との収縮率が異なることにより発生する応力を小さくして、キャビティの底面に応力が加わることを抑制することが可能になり、キャビティの底面に反りやうねりがなく、チップ部品の搭載信頼性に優れ、しかも、キャビティの底面の反りやうねりに起因する多層基板本体の反りや歪みのない、信頼性の高いセラミック多層基板を得ることが可能になる。   In the ceramic multilayer substrate of the present invention (Claim 1), since the die bond electrode disposed on the bottom surface of the cavity is divided into a plurality of parts, the shrinkage ratio between the ceramic part and the electrode part (conductor part) is reduced in the firing process. It is possible to reduce the stress generated due to the difference, and to suppress the stress from being applied to the bottom surface of the cavity, there is no warpage or undulation on the bottom surface of the cavity, and excellent chip component mounting reliability is achieved. It is possible to obtain a highly reliable ceramic multilayer substrate free from warping or distortion of the multilayer substrate body caused by warping or undulation of the bottom surface of the substrate.

また、キャビティの底面の中央領域は、キャビティ面の略全面にダイボンド電極を備えた構成とした場合に、通常、最も隆起の発生しやすい部分となるが、キャビティの底面の中央領域にダイボンド電極を構成する電極を配設しないようにしている（すなわち、キャビティの底面の中央領域を無電極領域としている）ので、キャビティの底面の中央領域に隆起が生じることを抑制、防止して、キャビティ底面の全体的なうねり量を低減することが可能になり、結果として、反りや歪みのない、信頼性の高いセラミック多層基板を得ることが可能になる。  In addition, the center region of the bottom surface of the cavity is usually the most prominent part when the die bond electrode is provided on the substantially entire surface of the cavity surface, but the die bond electrode is provided in the center region of the bottom surface of the cavity. Since the electrodes constituting it are not arranged (that is, the central region of the bottom surface of the cavity is an electrodeless region), it is possible to suppress and prevent the bulging from occurring in the central region of the bottom surface of the cavity. As a result, it is possible to reduce the overall amount of waviness, and as a result, it is possible to obtain a highly reliable ceramic multilayer substrate free from warping and distortion.

本発明において、ダイボンド電極を分割する場合の分割数に特に制約はなく、印刷精度に影響されないレベルであれば、できるだけ多くの数に分割する方が望ましい。
なお、通常は、例えば４以上の数に分割することが望ましい。なお、ダイボンド電極の分割数を増やすことがチップ部品搭載時のセンシングに利用できるのであればさらに好都合である。
また、分割の態様についても特に制約はなく、分割された個々の電極が縦横に行列状に並ぶようになるような態様で分割してもよく、また、放射状に分割することも可能である。 In the present invention, there are no particular restrictions on the number of divisions in the case of dividing the die bond electrode, and it is desirable to divide into as many as possible as long as the level is not affected by the printing accuracy.
Normally, it is desirable to divide the number into, for example, 4 or more. Note that it is more convenient if the number of divisions of the die bond electrode can be utilized for sensing when chip components are mounted.
There are no particular restrictions on the manner of division, and the divided electrodes may be divided in such a manner that the individual electrodes are arranged in rows and columns in the vertical and horizontal directions, or can be divided radially.

また、請求項２のセラミック多層基板のように、ダイボンド電極を構成する、複数に分割された各電極の面積を互いに略同一とすることにより、キャビティ底面の局所的な反りやうねりを低減することが可能になり、本発明をさらに実効あらしめることが可能になる。   Further, as in the ceramic multilayer substrate according to claim 2, the area of each of the plurality of divided electrodes constituting the die bond electrode is made substantially the same to reduce local warping and undulation of the cavity bottom surface. It becomes possible to make the present invention more effective.

また、分割された各電極の形状は、同一形状であればさらに望ましい。各電極を同一形状にすることにより、焼成工程でセラミック部分と電極部分（導体部分）との収縮率が異なることにより発生する応力（本発明のようにダイボンド電極を分割してもある程度の応力は発生する）の偏りを抑制して、キャビティ底面の反りやうねりをさらに確実に抑制することが可能になる。   Further, it is more desirable that the divided electrodes have the same shape. By making each electrode the same shape, the stress generated by different shrinkage rates between the ceramic part and the electrode part (conductor part) in the firing process (even if the die bond electrode is divided as in the present invention, some stress is Can be suppressed, and the warping and undulation of the bottom surface of the cavity can be more reliably suppressed.

また、請求項３のセラミック多層基板のように、キャビティの底面の平面形状が矩形である場合において、キャビティの底面を縦３列、横３列となるように９分割した領域のうち、中央領域を除いた８領域に、ダイボンド電極が分割して配設された構造とした場合、キャビティの底面の局所的な反りやうねりの発生を確実に低減することが可能になり、本発明をさらに実効あらしめることが可能になる。 Moreover, when the planar shape of the bottom surface of the cavity is a rectangle as in the ceramic multilayer substrate according to claim 3 , the center region of the regions obtained by dividing the bottom surface of the cavity into 9 columns so as to form 3 rows and 3 rows When the die bond electrode is divided and arranged in 8 regions excluding, it is possible to reliably reduce the occurrence of local warping and undulation on the bottom surface of the cavity, and the present invention is further effective. It becomes possible to storm.

以下に本発明の実施例を示して、本発明の特徴とするところをさらに詳しく説明する。   Examples of the present invention will be described below to describe the features of the present invention in more detail.

図１は、本発明が関連する発明の一実施例（実施例１）にかかるセラミック多層基板の構成を模式的に示す断面図、図２は、セラミック多層基板のキャビティの底面に形成されたダイボンド電極の形状を示す平面図である。 FIG. 1 is a sectional view schematically showing a configuration of a ceramic multilayer substrate according to one embodiment (Example 1) of the invention to which the present invention relates, and FIG. 2 is a die bond formed on the bottom surface of the cavity of the ceramic multilayer substrate. It is a top view which shows the shape of an electrode.

このセラミック多層基板は、図１に示すように、一方の主面にキャビティ２が形成された多層基板本体１、キャビティ２の底面７に配設されたダイボンド電極４、キャビティ２内に配設され、その底面７に配設されたダイボンド電極４に接合固定されたチップ部品（この実施例１ではＩＣチップ）３を備えている。   As shown in FIG. 1, the ceramic multilayer substrate is disposed in a multilayer substrate body 1 having a cavity 2 formed on one main surface, a die bond electrode 4 disposed on a bottom surface 7 of the cavity 2, and the cavity 2. A chip component (IC chip in the first embodiment) 3 that is bonded and fixed to the die bond electrode 4 disposed on the bottom surface 7 is provided.

また、チップ部品３は、ワイヤボンディングにより、ワイヤ６を介してキャビティ２内のワイヤボンディング面８に配設されたランド５に電気的に接続されている。   The chip component 3 is electrically connected to the land 5 disposed on the wire bonding surface 8 in the cavity 2 through the wire 6 by wire bonding.

そして、この実施例１のセラミック多層基板において、キャビティ２の底面７に配設されたダイボンド電極４は、図２に示すように、無電極部１１により仕切られ、縦３列、横３列に９分割されている。個々の電極（個別電極）１４はいずれも、横長方形の形状を有しており、各電極１４から構成されたダイボンド電極４も横長方形の形状を有している。また、ダイボンド電極４を構成する、複数に分割された電極１４はそれぞれ、略同一の形状および面積を有している。   In the ceramic multilayer substrate of Example 1, the die bond electrode 4 disposed on the bottom surface 7 of the cavity 2 is partitioned by the electrodeless portion 11 as shown in FIG. There are 9 divisions. Each of the individual electrodes (individual electrodes) 14 has a horizontal rectangular shape, and the die-bonding electrode 4 composed of each electrode 14 also has a horizontal rectangular shape. The plurality of divided electrodes 14 constituting the die bond electrode 4 have substantially the same shape and area.

このように、ダイボンド電極４を複数に分割して形成することにより、従来のように、ダイボンド電極４が一体構造で、大面積である場合には、セラミック部分と電極部分の焼結時の収縮率の差によりキャビティ２の底面７に生じるような反りやうねりの発生を防止することが可能になる。その結果、キャビティ２の底面７が平坦で、チップ部品の搭載信頼性が高く、かつ、キャビティ２の底面７に発生する反りやうねりに起因する多層基板本体の反りや歪みのない、信頼性の高いセラミック多層基板を得ることが可能になる。   As described above, when the die bond electrode 4 is divided into a plurality of parts and the die bond electrode 4 has a single structure and has a large area as in the prior art, the ceramic portion and the electrode portion are shrunk during sintering. It is possible to prevent the occurrence of warpage and undulation that occurs on the bottom surface 7 of the cavity 2 due to the difference in rate. As a result, the bottom surface 7 of the cavity 2 is flat, the chip component mounting reliability is high, and there is no warping or distortion of the multilayer substrate body caused by warping or waviness occurring on the bottom surface 7 of the cavity 2. It becomes possible to obtain a high ceramic multilayer substrate.

なお、比較のため、平面寸法が６．５mm×５mmのキャビティ２の底面７の略全面に、図２に示すように、縦３列、横３列に９分割されたダイボンド電極４を形成した場合（実施例１の試料）と、図３に示すように、一体のダイボンド電極４を形成した場合（比較例の試料）について、キャビティ２の底面７の反りの大きさ（底面７の隆起量）（図４のＡで示した距離）を調べた。   For comparison, as shown in FIG. 2, the die bond electrode 4 divided into nine rows and three rows is formed on substantially the entire bottom surface 7 of the cavity 2 having a plane dimension of 6.5 mm × 5 mm. In the case (sample of Example 1) and the case where the integral die-bonding electrode 4 is formed as shown in FIG. 3 (sample of the comparative example), the amount of warpage of the bottom surface 7 of the cavity 2 (the amount of protrusion of the bottom surface 7) ) (Distance indicated by A in FIG. 4).

その結果、上記比較例の場合には、キャビティの底面の反りの大きさ（底面の隆起量）が５５．０μmであったのに対して、ダイボンド電極４を分割して形成した実施例１の場合には、キャビティ２の底面７の反りの大きさ（底面７の隆起量）が４７．３μmと小さくなることが確認された。   As a result, in the case of the comparative example, the magnitude of the warp of the bottom surface of the cavity (the amount of protrusion on the bottom surface) was 55.0 μm, whereas the die bond electrode 4 was divided and formed. In this case, it was confirmed that the warpage of the bottom surface 7 of the cavity 2 (the amount of protrusion of the bottom surface 7) was as small as 47.3 μm.

図５は本発明の実施例（実施例２）にかかるダイボンド電極の構成を示す図である。
すなわち、この実施例２では、図５に示すように、ダイボンド電極４を、無電極部１１により縦横に分割され、かつ、中央領域１０には電極の形成されていない無電極領域１０ａが配設された構造（すなわち、図２のダイボンド電極４を構成する個々の電極１４のうち、中央の電極１４（１４ａ）を取り除いた構造）とした。そして、この図５に示すような構造を有するダイボンド電極４を備えた実施例２のセラミック多層基板を製造し、キャビティの底面の反りの大きさ（底面の隆起量）を調べた。 FIG. 5 is a diagram showing a configuration of a die bond electrode according to an example (Example 2) of the present invention.
That is, in Example 2, as shown in FIG. 5, the die bond electrode 4 is divided vertically and horizontally by the electrodeless portion 11, and the electrodeless region 10 a in which no electrode is formed is disposed in the central region 10. 2 (ie, the structure in which the central electrode 14 (14a) is removed from the individual electrodes 14 constituting the die bond electrode 4 of FIG. 2). And the ceramic multilayer substrate of Example 2 provided with the die bond electrode 4 which has a structure as shown in this FIG. 5 was manufactured, and the magnitude | size of the curvature of the bottom face of a cavity (the amount of protrusions of a bottom face) was investigated.

その結果、図５に示すように、ダイボンド電極４を、無電極部１１により縦横に分割され、かつ、中央領域１０には電極の形成されていない無電極領域１０ａが配設された構造とした場合、キャビティの底面の反りの大きさ（底面の隆起量）が２９．９μmと、上記実施例１の場合よりもさらに小さくなることが確認された。   As a result, as shown in FIG. 5, the die bond electrode 4 is divided vertically and horizontally by the electrodeless portion 11, and the electrodeless region 10 a where no electrode is formed is disposed in the central region 10. In this case, it was confirmed that the warpage of the bottom surface of the cavity (the amount of protrusion on the bottom surface) was 29.9 μm, which was even smaller than in the case of Example 1.

なお、上記実施例１では、ダイボンド電極４を、縦３列、横３列に均等に９分割した場合（図２）について説明したが、ダイボンド電極４を分割する場合の分割数はこれに限定されるものではなく、９分割よりも多くの数に分割することも可能であり、９分割未満の数に分割することも可能である。また、縦の列数と横の列数を異ならせることも可能である。
ただし、焼成工程でセラミック部分と電極部分の収縮率が異なることにより発生する応力を小さくする見地からは、ダイボンド電極を分割する場合の分割数は、ある程度の数以上（通常は４以上の数）とすることが望ましい。 In the first embodiment, the case where the die bond electrode 4 is equally divided into nine rows in three vertical rows and three horizontal rows (FIG. 2) has been described. However, the number of divisions when the die bond electrode 4 is divided is limited to this. However, it is possible to divide into more than 9 divisions, and it is also possible to divide into less than 9 divisions. In addition, the number of vertical columns and the number of horizontal columns can be different.
However, from the viewpoint of reducing the stress generated due to the difference in shrinkage between the ceramic part and the electrode part in the firing step, the number of divisions when dividing the die bond electrode is a certain number (usually a number of 4 or more). Is desirable.

また、ダイボンド電極を分割する場合の分割の態様についても特に制約はなく、上記実施例１のように、縦３列、横３列に分割する態様（個々の電極が行列状に並ぶような態様）に限らず、例えば、放射状に分割することも可能である。   In addition, there is no particular limitation on the manner of division when the die bond electrode is divided, and an embodiment in which the die bond electrode is divided into three columns in the vertical direction and three rows in the horizontal direction (a mode in which the individual electrodes are arranged in a matrix form). For example, it is also possible to divide radially.

また、上記実施例２の場合のように、ダイボンド電極を構成する個々の電極のうち、中央領域の電極を取り除いた構成とする場合においても、ダイボンド電極を放射状に分割し、かつ、中央領域が無電極領域となるように構成することも可能である。   In addition, as in the case of Example 2 above, even in the case of the configuration in which the central region electrode is removed from the individual electrodes constituting the die bond electrode, the die bond electrode is divided radially, and the central region is It can also be configured to be an electrodeless region.

また、上記実施例では、多層基板本体の一方の主面側にのみキャビティが形成されている場合を例にとって説明したが、両方の主面側にキャビティが形成された構成とすることも可能である。   In the above embodiment, the case where the cavity is formed only on one main surface side of the multilayer substrate main body has been described as an example. However, a configuration in which the cavity is formed on both main surface sides is also possible. is there.

また、上記実施例ではチップ部品がＩＣチップである場合を例にとって説明したが、チップ部品の種類はこれに限られるものではなく、弾性表面波フィルタその他の種々のチップ部品をキャビティに収容する場合に広く本発明を適用することが可能である。   In the above embodiment, the case where the chip component is an IC chip has been described as an example. However, the type of the chip component is not limited to this, and the surface acoustic wave filter and other various chip components are accommodated in the cavity. The present invention can be widely applied to.

本発明は、さらにその他の点においても上記実施例の構成に制約されるものではなく、キャビティの形状、配設数などに関し、発明の範囲内において、種々の応用、変形を加えることが可能である。   The present invention is not limited to the configuration of the above embodiment in other respects, and various applications and modifications can be made within the scope of the invention with respect to the shape and number of the cavities. is there.

上述のように、本発明によれば、キャビティの底面に配設されたダイボンド電極を、複数に分割するとともに、中央領域にはダイボンド電極を構成する電極が配設されていない無電極領域を形成するようにしているので、焼成工程でセラミック部分と電極部分の収縮率が異なることにより発生する応力を小さくして、キャビティの底面に反りやうねりが生じることを抑制することが可能になり、チップ部品の搭載安定性に優れた、信頼性の高いセラミック多層基板を得ることが可能になる。
したがって、本発明は、チップ部品を収容するキャビティを備えたセラミック多層基板に広く適用することが可能である。 As described above, according to the present invention, the die bond electrode disposed on the bottom surface of the cavity is divided into a plurality, and an electrodeless region in which the electrode constituting the die bond electrode is not disposed is formed in the central region. since the way, to reduce the stress shrinkage of the ceramic part and the electrode portion in the firing process caused by different, it is possible to suppress the warpage and undulation occurs in the bottom of the cavity, the chip A highly reliable ceramic multilayer substrate having excellent component mounting stability can be obtained.
Therefore, the present invention can be widely applied to ceramic multilayer substrates having cavities for accommodating chip components.

本発明が関連する発明の一実施例（実施例１）にかかるセラミック多層基板の構成を模式的に示す断面図である。It is sectional drawing which shows typically the structure of the ceramic multilayer substrate concerning one Example (Example 1) with which this invention relates. 実施例１のセラミック多層基板のキャビティの底面に形成されたダイボンド電極の形状を示す平面図である。 4 is a plan view showing the shape of a die bond electrode formed on the bottom surface of the cavity of the ceramic multilayer substrate of Example 1. FIG. 比較例のダイボンド電極（分割されていない一体構造のダイボンド電極）を示す図である。It is a figure which shows the die-bonding electrode (die-bonding electrode of the integral structure which is not divided | segmented) of a comparative example. キャビティの底面の反りの大きさ（底面の隆起量）を説明するための図である。It is a figure for demonstrating the magnitude | size (the amount of protrusions of a bottom face) of the curvature of the bottom face of a cavity. 本発明の実施例（実施例２）にかかるセラミック多層基板のキャビティの底面に形成されたダイボンド電極の形状を示す平面図である。It is a top view which shows the shape of the die-bonding electrode formed in the bottom face of the cavity of the ceramic multilayer substrate concerning the Example (Example 2) of this invention . 多層基板本体の一方主面にキャビティを備えた従来のセラミック多層基板を示す図である。It is a figure which shows the conventional ceramic multilayer substrate provided with the cavity in one main surface of a multilayer substrate main body. 従来のセラミック多層基板の構成および問題点を説明するための図である。It is a figure for demonstrating the structure and problem of the conventional ceramic multilayer substrate.

１ 多層基板本体
２ キャビティ
３ チップ部品
４ ダイボンド電極
５ ランド
６ ワイヤ
７ 底面
８ ワイヤボンディング面
１０ 中央領域
１０ａ 無電極領域
１１ 無電極部
１４ 個々の電極（個別電極）
１４（１４ａ） 中央の電極 DESCRIPTION OF SYMBOLS 1 Multilayer substrate body 2 Cavity 3 Chip component 4 Die bond electrode 5 Land 6 Wire 7 Bottom surface 8 Wire bonding surface 10 Central area | region 10a Electrodeless area | region 11 Electrodeless part 14 Individual electrode (individual electrode)
14 (14a) Center electrode

Claims (3)

少なくとも一方の主面に、チップ部品を収容するキャビティが形成された多層基板本体と、
キャビティの底面に配設されたダイボンド電極と、
キャビティ内に配設され、前記ダイボンド電極に接合固定されるとともに、多層基板本体が備える配線導体と電気的に接続されたチップ部品と
を具備するセラミック多層基板であって、
前記ダイボンド電極が複数に分割された構造を有するとともに、前記キャビティの底面の中央領域には前記ダイボンド電極を構成する電極が配設されていない無電極領域が形成されていること
を特徴とするセラミック多層基板。 A multilayer substrate body in which a cavity for accommodating chip components is formed on at least one main surface;
A die bond electrode disposed on the bottom surface of the cavity;
A ceramic multilayer substrate that is disposed in a cavity and is bonded and fixed to the die bond electrode, and includes a chip component that is electrically connected to a wiring conductor included in the multilayer substrate body,
Together with the die bonding electrode is divided into a plurality structure, the ceramic in the central region of the bottom surface of the cavity, characterized that you have formed no-electrode region in which the electrode constituting the die bonding electrode is not disposed is Multilayer board. 前記ダイボンド電極を構成する、複数に分割された電極のそれぞれが略同一の面積を有していることを特徴とする請求項１記載のセラミック多層基板。   2. The ceramic multilayer substrate according to claim 1, wherein each of the plurality of divided electrodes constituting the die bond electrode has substantially the same area. キャビティの底面の形状が矩形であり、前記底面を縦３列、横３列となるように９分割した領域のうち、中央領域を除いた８領域に、前記ダイボンド電極が、分割して配設されていることを特徴とする請求項１または２記載のセラミック多層基板。 The die-bonding electrode is divided and arranged in 8 areas excluding the central area among the 9 areas divided so that the bottom surface of the cavity is rectangular and the bottom surface is arranged in 3 rows and 3 rows. 3. The ceramic multilayer substrate according to claim 1, wherein the ceramic multilayer substrate is formed.
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JPH03284858A (en) * 1990-03-30 1991-12-16 Matsushita Electron Corp Semiconductor device
JPH10173083A (en) * 1996-12-05 1998-06-26 Ngk Spark Plug Co Ltd Wiring board for mounting electronic component and its manufacturing method
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