JPH08241935A - Multilayer circuit board - Google Patents

Abstract

PURPOSE: To provide a multilayer circuit board in which a wiring operation can be performed even directly below a position in which a die pad is arranged. CONSTITUTION: In a multilayer circuit board 1, a die pad 21 on which an LSI bare chip (a semiconductor element) 20 is to be mounted is formed. The multilayer circuit board comprises a plurality of conductor layers, including a power supply/ground plane 3b, a signal line 4b, a power supply/ground plane 5b and signal lines 6b, 6d; and a plurality of dielectric layers, including a first dielectric layer 3a, a second dielectric layer 4a, a third dielectric layer 5a and a fourth dielectric layer 6a. Then, the conductor layers and the dielectric layers are laminated alternately, and a partial dielectric layer 7 for the die pad 21, having a prescribed size, is formed on the signal line 6d arranged at the outermost part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer circuit board, and more particularly to a thick film multilayer circuit board.

[0002]

2. Description of the Related Art Conventionally, a multilayer circuit board has a plurality of conductor layers and a plurality of dielectric layers, and the conductor layers and the dielectric layers are alternately laminated. For example, in FIG.
A thick film multilayer circuit board (hereinafter, simply referred to as “multilayer circuit board”) 31 shown in (b) has a middle layer signal on a first layer 32 as a power or ground plane (hereinafter, referred to as “power / ground plane”) layer. A second layer 33 as a line layer, a third layer 34 as a power / ground plane layer, and a fourth layer 35 as an upper signal line layer are laminated in this order.

The first layer 32 is a power supply / ground plane 3 which is a conductor layer formed on the first dielectric layer 32a.
2b and the second layer 33 is the first layer 32.
It is composed of a second dielectric layer 33a formed above and a signal line 33b which is a conductor layer formed above this. Also the third
The layer 34 is a third dielectric layer 34 formed on the second layer 33.
a and a power / ground plane 34b which is a conductor layer formed on the multilayer circuit board 30.
The outermost fourth layer 35 is a fourth dielectric layer 35a formed on the third layer 33, a signal line 35b which is a conductor layer formed on the fourth dielectric layer 35a, and the fourth dielectric layer 35a. Pads for mounting and connecting components (hereinafter, referred to as
(Collectively referred to as a pad) 35c.

In the multi-layer circuit board 31, the signal line 35b connected to the pad 35c and the signal line 33b of the second layer 33 among the signal lines 35b of the fourth layer 35 are connected to the signal line vias 37. Connected through.

Usually, on such a multilayer circuit board 31, that is, on the fourth dielectric layer 35a of the fourth layer 35,
The LSI bare chip 50, which is a semiconductor element, is mounted via the die pad 51 in a face-up state, for example.
In this case, the LSI bare chip 50 has the die paste 52
It is fixed to the die pad 51 via the and is connected to the pad 35c via the bonding wire 53. When the back surface of the LSI bare chip 50 mounted on the die pad 51 must be used as a ground, the die paste agent 52
A material made of a conductive material is used as
The die pad 51 is connected to the power / ground plane 34b through the via 36 for connecting between the grounds formed in the fourth layer 35.
Connected to.

[0006]

However, in the multilayer circuit board 31 shown in FIG. 2, since the die pad 51 is directly provided on the fourth dielectric layer 35a of the fourth layer 35, the fourth dielectric layer immediately below the die pad 51 is formed. When the signal line 35b is arranged on the body layer 35a, the signal line 35b may be short-circuited with the die pad 51. Therefore, the signal line 35b may be arranged on the fourth dielectric layer 35a directly below the die pad 51. Can not. Therefore, the arrangement position of the signal line 35b is restricted, which prevents the wiring density from being increased. Therefore, it is desired to develop a multi-layer circuit board that can be wired immediately below the die pad arrangement position.

[0007]

A multilayer circuit board of the present invention is provided with a die pad for mounting a semiconductor element, has a plurality of conductor layers and a plurality of dielectric layers, and has a plurality of conductor layers. It is formed by alternately laminating dielectric layers. Then, a partial dielectric layer of a predetermined size for a die pad is provided on the outermost conductor layer.

[0008]

According to the multilayer circuit board of the present invention, the partial dielectric layer for the die pad is provided on the outermost conductor layer. Therefore, the partial dielectric layer for providing the semiconductor element is provided on the multilayer circuit board. Even if the die pad is provided on the body layer, the conductor layer is in a state of being insulated from the die pad. Therefore, even if the die pad is provided on the partial dielectric layer, the outermost conductor layer can be arranged without any restriction on the arrangement position of the die pad.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the multilayer circuit board of the present invention will be described below with reference to FIG. 1 shows a case where the present invention is applied to a thick film multilayer circuit board. In FIG. 1, (a) is a plan view and (b) is a sectional view taken along the line AA in (a). is there.

As shown in FIG. 1, the thick film multilayer circuit board (hereinafter, simply referred to as a multilayer circuit board) 1 is a first layer as a power source or a ground plane layer (hereinafter, referred to as a power source / ground plane layer). On the third layer, the second layer 4 as the middle signal line layer and the third layer as the power / ground plane layer.
The layer 5, the fourth layer 6 as an upper signal line layer, and the partial dielectric layer 7 which is a feature of the present invention are laminated in this order. The first layer 3 is composed of a first dielectric layer 3a and a power / ground plane 3b which is a conductor layer formed on the first dielectric layer 3a, and the second layer 4 is formed on the first layer 3. Second
It is composed of a dielectric layer 4a and a middle-layer signal line 4b which is a conductor layer formed on the dielectric layer 4a.

The third layer 5 is composed of a third dielectric layer 5a formed on the second layer 4 and a power / ground plane 5b which is a conductor layer formed on the third dielectric layer 5a.
The layer 6 is a fourth dielectric layer 6a formed on the third layer 5, an upper signal line 6b which is a conductor layer formed on the fourth dielectric layer 6a,
6d, a plurality of pads for component mounting and connection (hereinafter,
Collectively referred to as a pad) 6c. The signal line 6b is provided at a position other than the formation position of the partial dielectric layer 7 formed in the upper layer, and the signal line 6d is provided at the formation position of the partial dielectric layer 7. The pad 6c is
It is formed around the formation position of the partial dielectric layer 7.

On the outermost conductor layer of the conductor layers, that is, on the conductor layer of the fourth layer 6 which is a conductor layer at least a part of which is exposed without being covered with the dielectric layer. Is provided with a partial dielectric layer 7 for the die pad 21. Here, the partial dielectric layer 7 for the die pad 21 is provided on the signal line 6d of the signal lines 6b and 6d which is the conductor layer of the fourth layer 6. The partial dielectric layer 7 is formed to have a predetermined size, that is, a size and shape that are substantially equal to or slightly larger than the bottom surface of the die pad 21 to be provided on the multilayer circuit board 1. Further, as the material of the partial dielectric layer 7, for example, glass ceramics is used, but it is not limited to this as long as it is well adhered to the lower layer of the partial dielectric layer 7 when the multilayer circuit board 1 is manufactured.

As described above, the multilayer circuit board 1 includes the four conductor layers of the power / ground planes 3b and 5b, the middle-layer signal line 4b, the upper-layer signal lines 6b and 6d, and the first dielectric layer 3a to the fourth dielectric layer. The body layer 6a and the five dielectric layers of the partial dielectric layer 7 are provided, and the conductor layers and the dielectric layers are alternately laminated. The partial dielectric layer 7 and the fourth dielectric layer 6a are provided with vias 8 for connecting the grounds to the power / ground plane 5b of the third layer 5, and are formed on the upper surface of the partial dielectric layer 7. At least a part is in a state of being electrically connected to the power / ground plane 5b via the via 8.

Further, among the signal lines 6b and 6d of the fourth layer 6, the signal lines 6b connected to the pads 6c are alternately arranged for each pad 6c, and the pads 6c to the partial dielectric layer 7 are alternately arranged.
Side, the pad 6c is formed so as to extend to the side opposite to the partial dielectric layer 7. The tip of the signal line 6b formed so as to extend to the partial dielectric layer 7 side is for connecting the signal line formed on the fourth layer 6 and the third layer 5 immediately below the partial dielectric layer 7. It is connected to the signal line 4b of the second layer 4 via the via 9a. Further, the tips of the signal lines 6b formed so as to extend to the side opposite to the partial dielectric layer 7 are formed on the fourth layer 6 and the third layer 5 at positions other than directly below the partial dielectric layer 7. The signal line 4b of the second layer 4 is connected via the signal line connecting via 9b.

When the LSI bare chip 20 is provided as a semiconductor element on the multilayer circuit board 1 configured as described above, the die pad 21 is provided on the partial dielectric layer 7.
The LSI bare chip 20 is provided on the die pad 21 in a face-up state, for example. FIG. 1 shows a state where the LSI bare chip 20 is mounted on the die pad 21, and here, the LSI bare chip 20 is fixed to the die pad 21 via a die paste agent 22 made of a conductive material. Further, the LSI bare chip 20 is connected to the plurality of pads 6c ... Through bonding wires 23.

Next, a method of manufacturing the multilayer circuit board 1 will be described. First, the sheet-shaped first dielectric layer 3a and the second dielectric layer 4
a, the third dielectric layer 5a, the fourth dielectric layer 6a and the partial dielectric layer 7 are prepared, and the third dielectric layer 5a and the fourth dielectric layer 6 are prepared.
Holes for the vias 9a and 10b are formed at predetermined positions with a. Further, holes for the vias 8 are formed at predetermined positions in the fourth dielectric layer 6a and the partial dielectric layer 7. Then, the conductor paste is filled in the respective holes by the thick film printing method.

Next, the first dielectric layer 3 is formed by a thick film printing method.
a to the power / ground plane 3b and the second dielectric layer 4a
To the signal line 4b, the third dielectric layer 5a to the power / ground plane 5b, and the fourth dielectric layer 6a to the signal line 6b.
b, 6d are respectively printed, and pads 6c are provided at predetermined positions on the fourth dielectric layer 6a to form the first layer 3, the second layer 4, the third layer 5 and the fourth layer 6.

The first layer 3, the second layer 4, and the third layer
The layer 5, the fourth layer 6 and the partial dielectric layer 7 are superposed in this order while being aligned with each other, fixed by thermocompression bonding and finally fired. As a result, the multilayer circuit board 1
Is manufactured. In addition, at the time of fixing, a solvent that burns during the subsequent firing and does not remain as residual carbon on the substrate, for example, the binder contained in the sheet-shaped first dielectric layer 3a to fourth dielectric layer 6a. The partial dielectric layer 7 is fixed with the same type of solvent as.

According to the multilayer circuit board 1 manufactured as described above, since the partial dielectric layer 7 for the die pad 21 is provided on the signal line 6d, the LSI bare chip 20 is provided on the multilayer circuit board 1. Partial dielectric layer 7 for providing
Even if the die pad 21 is provided on the upper portion, the signal line 6d is insulated from the die pad 21. Therefore, even if the die pad 21 is provided on the partial dielectric layer 7, the upper signal lines 6b and 6d can be arranged on the fourth dielectric layer 6a without any restriction on the arrangement position of the die pad 21. That is, the partial dielectric layer 7 for the die pad 21
The signal line 6d can be freely formed immediately below, as in this embodiment.

In the conventional example shown in FIG. 2, the pad 35 is used.
Although the signal line 35b from c could be drawn out only in one direction on the side opposite to the position where the die pad 51 was arranged, in the present embodiment, the fourth dielectric layer 6a immediately below the position where the die pad 21 is arranged.
Since the signal line 6d can be formed on the upper side, the signal line 6b from the pad 6c can be drawn out in two directions, that is, the die pad 21 arrangement position side and the side opposite to the die pad 21 arrangement position.

In particular, when the signal line 6b is drawn from the pad 6c used for wire bonding and connected to the signal line 4b in the middle layer with the vias 9a and 9b as in this embodiment, the pitch of the pad 6c is the pitch of the vias 9a and 9b. Very effective when smaller than. Therefore, in the multilayer circuit board 1 of the present embodiment, the wiring density can be improved as compared with the conventional one, so that the wiring density can be increased.

Further, in this embodiment, at least a part of the upper surface of the partial dielectric layer 7 is electrically connected to the power / ground plane 5b through the via 8, so that the die pad is formed on the partial dielectric layer 7. 21 is provided, the die pad 2
1 is connected to the power / ground plane 5b. As a result, the signal line 6b between the partial dielectric layer 7 and the fourth dielectric layer 6a is sandwiched between the power / ground plane 5b and the die pad 21 (ground) connected thereto. , Can be configured as a stripline. Moreover, since the upper-layer signal line 6b is constituted by the macro strip line and the middle-layer signal line 4b is constituted by the strip line, the multilayer circuit board 1 of the present embodiment can cope with high-speed signals.

[0023]

As described above, according to the multilayer circuit board of the present invention, the partial dielectric layer for the die pad is provided on the outermost conductor layer, and the die pad is formed on the partial dielectric layer. , The conductor layer immediately below the die pad is insulated from the die pad, so that the outermost conductor layer can be arranged at the arrangement position of the die pad without any restriction. Therefore, in the multilayer circuit board of the present invention, even if the die pad is provided, the wiring can be freely provided directly below the die pad via the partial dielectric layer, and the wiring density can be improved, so that high-density wiring is possible.

[Brief description of drawings]

FIG. 1 is a diagram illustrating an embodiment of the present invention, (a)
Is a plan view and (b) is a sectional view taken along the line AA in (a).

FIG. 2 is a diagram illustrating a conventional example, (a) is a plan view,
(B) is a BB line sectional view taken on the line in (a).

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Multilayer circuit board 3a 1st dielectric layer 3b Power / ground plane (conductor layer) 4a 2nd dielectric layer 4b Signal line (conductor layer) 5a 3rd dielectric layer 5b Power / ground plane (conductor layer) 6a 4th Dielectric layer 6b, 6d Signal line (conductor layer) 7 Partial dielectric layer 20 LSI bare chip (semiconductor element) 21 Die pad

Claims (2)

[Claims] 1. A multi-layer circuit board provided with a die pad for mounting a semiconductor element, comprising a plurality of conductor layers and a plurality of dielectric layers, wherein the conductor layers and the dielectric layers are alternately laminated. And a partial dielectric layer of a predetermined size for the die pad, which is provided on the outermost conductor layer. 2. At least one of the conductor layers other than the outermost conductor layer among the plurality of conductor layers is a power supply layer or a ground layer, and at least a part of an upper surface of the partial dielectric layer. The multi-layer circuit board according to claim 1, wherein is electrically connected to the power supply or the ground layer.