JP2508831B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device having a multilayer wiring structure, and more particularly to a semiconductor device which enables fine multilayer wiring.

〔Overview〕

According to the present invention, in a semiconductor device having multilayer wiring, an interlayer connection in which a conductor film for connection between a lower layer wiring and an upper layer wiring is formed by exposing the upper surface of the lower layer wiring and a part of a side surface continuous with the upper surface. By filling the holes with the connecting conductor and filling the gaps with the second insulating film, the inter-wiring connections are formed, eliminating the need to increase the width of the lower-layer wiring in the inter-wiring connections, thus achieving high integration. Is intended.

[Conventional technology]

Conventionally, this type of semiconductor device has a wiring structure as shown in FIGS. 4 (a) and 4 (b). In the figure, 1 is a silicon substrate, 2 is a silicon oxide film, 3 is a first aluminum wiring, 4 is a bias ECR (Electron Cyclotron Resonator).
a silicon oxide film formed by a plasma CVD method or the like, 7 is a second aluminum wiring, and 8 is an interlayer connection hole.

In this conventional example, the width of the first aluminum wiring 3 is large at the inter-wiring connection portion between the first aluminum wiring 3 and the second aluminum wiring 7. Therefore, for example, the first aluminum wiring width is 1.0 μm, the wiring interval is 1.0 μm, and the interlayer connection hole 8 is
1.0 μm, allowance between the interlayer connection hole 8 and the first aluminum wiring 3
If it is 0.5 μm, the first aluminum wiring pitch is 2.5 μm.

[Problems to be solved by the invention]

In the conventional semiconductor device described above, the wiring width is increased in consideration of the alignment margin in the lower layer wiring portion where the interlayer connection hole is opened so that the interlayer connection hole is not displaced with respect to the lower layer wiring and is not removed. Was there. This means that the wiring pitch in the portion where the interlayer connection hole is installed becomes larger than that in the portion where the interlayer connection hole is not installed, and in particular, there is a drawback that it becomes a main impediment factor to high integration of the semiconductor integrated circuit. .

The object of the present invention is to eliminate the above-mentioned drawbacks,
An object of the present invention is to provide a semiconductor device that can achieve interlayer connection without increasing the wiring pitch of the lower layer wiring and can achieve high integration.

[Means for solving problems]

The present invention relates to a semiconductor device having a plurality of layers of wiring formed on one main surface of a semiconductor substrate with an insulating film sandwiched therebetween, in which the upper surface of a lower layer wiring and a part of a side surface continuous with the upper surface are exposed to expose the insulating film. In a partly formed interlayer connection hole, a connection conductor film formed covering the exposed portion of the lower layer wiring and connected to the upper layer wiring is embedded to form a gap between the interlayer connection hole and the connection conductor film. It is characterized by having an inter-wiring connection portion filled with a second insulating film.

[Action]

The connection conductor film, for example, a tungsten film fills the interlayer connection hole formed by exposing the upper surface of the lower layer wiring and a part of the side surface continuous with the upper surface, and further the gap between the interlayer connection hole and the connection conductor film is formed. The inter-wiring connection portion filled with the second insulating film is formed, and the interlayer insulating film is interposed between the side surface portion and the upper surface of the lower layer wiring.

Therefore, the inter-layer connection hole is larger than the width of the lower layer wiring, that is, it is formed outside, and can be set to a sufficient size in consideration of misalignment. Moreover, the width of the lower layer wiring can be left unchanged, and as a result, the wiring pitch can be reduced and high integration can be achieved. Further, there is an advantage that the distance from the adjacent wiring becomes large, the capacity coupling can be made small, and the gap is further filled to improve the flatness.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 (a) is a plan view showing an embodiment of the present invention, and FIG. 1 (b) is a sectional view taken along the line AA '.

In this embodiment, a first aluminum wiring 3 and a second aluminum wiring 7 are formed as a two-layer wiring formed on one main surface of a silicon substrate 1 with silicon oxide films 2 and 4 as insulating films sandwiched therebetween. In a semiconductor device having, the upper surface of the first aluminum wiring 3 and a part of a side surface connected to the first aluminum wiring 3 are exposed to form an interlayer connection hole 8 formed in the silicon oxide film 4 so as to cover the exposed portion of the first aluminum wiring 3. It has an inter-wiring connection portion in which a tungsten film 5 as a connecting conductor film connected to the second aluminum wiring 7 is embedded.

In FIGS. 1 (a) and 1 (b), 6 is a silica-coated oxide film formed by filling the gap between the tungsten film 5 and the interlayer connection hole 8, which is a gap caused by misalignment during formation of the interlayer connection hole. The purpose of this is to fill in the concave portions caused by the above and to planarize the surface on which the second aluminum wiring 7 is formed. The material is not limited to silica, and any material can be used as long as it can fill the gap and form an insulator.

1A and 1B, the size of the interlayer connection hole 8 is set to be larger than the width of the first aluminum wiring 3 in the lower layer, and it is embedded in the connection conductor. This is because the tungsten film 5 as a film is provided and the gap between the interlayer connection holes 8 is filled with the silica coating oxide film 6.

Next, with respect to the manufacturing method of the present embodiment, referring to plan views in the main steps shown in FIGS. 2 (a) and (b) and FIGS. Explain.

First, as shown in FIGS. 2A and 2B, an aluminum film having a thickness of about 0.5 μm is deposited on the silicon oxide film 2 on the silicon substrate 1 to form a pattern, and the first aluminum wiring 3 is formed.
To form.

Next, as shown in FIGS. 3A and 3B, after the silicon oxide film 4 having a thickness of about 0.9 μm is formed on the first aluminum wiring 3 by the bias ECR plasma CVD method, the first aluminum wiring 3 is formed. The upper surface and a part of the side surface are selectively exposed, and a tungsten film 5 having a film thickness of about 0.4 μm is formed by a tungsten selective CVD method. Then, the gap between the tungsten film 5 and the silicon oxide film 5 is coated with silica by an etch-back method and heat-treated to be filled with the silica-coated oxide film 6.

Finally, as shown in FIGS. 1 (a) and 1 (b), aluminum having a film thickness of about 1.0 μm is deposited and patterned to form a second aluminum wiring 7 electrically connected to the tungsten film 5.

In this embodiment, if the first aluminum wiring width is 1.0 μm, the wiring interval is 1.0 μm, and the interlayer connection holes 8 are 1.0 μm × 2.0 μm, the first aluminum wiring pitch is 2.0 μm. Although aluminum is used as the wiring material of the first wiring and the second wiring in this embodiment, a refractory metal such as tungsten may be used instead of aluminum. In this case, there is an advantage that the migration resistance of the wiring is greatly improved. The same applies when another conductor material such as highly conductive polycrystalline silicon is used as the wiring material.

〔The invention's effect〕

As described above, according to the present invention, the size of the interlayer connection hole can be made larger than the width of the lower layer wiring, that is, can be removed, so that a fine multilayer wiring can be realized and high integration can be achieved. There is. Further, the gap between the connection holes is filled with an insulating film, so that the flatness is increased and the productivity can be improved. Further, since the distance to the adjacent wiring can be increased, there is an advantage that the capacitance coupling can be reduced.

[Brief description of drawings]

1 (a) and 1 (b) are a plan view and an AA 'sectional view showing an embodiment of the present invention. 2 (a) and 2 (b) are a plan view and a sectional view taken along the line AA 'in the main manufacturing steps thereof. 3 (a) and 3 (b) are a plan view and a sectional view taken along the line AA 'in the main manufacturing steps thereof. 4 (a) and 4 (b) are a plan view showing a conventional example and its BB 'sectional view. 1 ... Silicon substrate, 2, 4 ... Silicon oxide film, 3 ... First aluminum wiring, 5 ... Tungsten film, 6 ... Silica-coated oxide film, 7 ... Second aluminum wiring, 8 ... Interlayer connection hole.

Claims (1)

(57) [Claims] 1. A semiconductor device having a plurality of layers of wiring formed on one main surface of a semiconductor substrate with an insulating film sandwiched therebetween, wherein the upper surface of a lower layer wiring and a part of a side surface continuous with it are exposed. A connecting conductor film formed so as to cover the exposed portion of the lower layer wiring and connected to the upper layer wiring is embedded in an interlayer connecting hole formed in a part of the gap between the interlayer connecting hole and the connecting conductor film. A semiconductor device comprising: an inter-wiring connecting portion in which the second insulating film is filled with