JP3107005B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device comprising:
The present invention relates to a semiconductor integrated circuit device having at least two or more wiring layers stacked with an insulating film interposed therebetween, and more particularly to a structure of a wiring and a via hole.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device having a multi-layer wiring structure, which has been miniaturized in recent years, upper and lower wiring layers are connected by fine plugs having a diameter of 0.5 μm or less.

FIG. 4 shows an example of a conventional semiconductor integrated circuit device having a multilayer wiring structure. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line EE.

In FIG. 4, on a semiconductor substrate 101,
Lower wirings 102a and 102b and upper wiring 104 are formed with an insulating film 103 interposed therebetween. The upper wiring 104 and the lower wirings 102a and 102b are connected by a plug 105. Such a plug 105 is formed by depositing an insulating film 103 on the semiconductor substrate 101 on which the lower wirings 102a and 102b are formed, and then forming a via hole in a portion of the insulating film 103 where the lower wiring 102b and the upper wiring 104 are connected. In general, the method is performed by forming the via holes 103a and filling the via holes 103a with the conductive material 106. The upper wiring 104 and the lower wiring 102b
The width of the contact portion with the plug 105 is formed to be wider than the width of the other portion in consideration of the positional deviation when forming the via hole 103a.

However, in recent miniaturized semiconductor integrated circuit devices, it is required to eliminate a portion having a large wiring width in order to form wiring at a higher density.
As shown in FIG. 5, the upper wiring 114 and the lower wiring 11
The width of 2b is the same at the portion connected to the plug 115. That is, the wiring width is constant.

[0006]

However, in a semiconductor integrated circuit device in which miniaturization is progressing, the distance between adjacent wirings in the same wiring layer becomes narrow, and when an insulating film is deposited on this wiring, the distance between the wirings is reduced. In a narrow portion, the burying property of the insulating film is poor, and as shown in FIG.
Cavity 117 may occur between a and 112b. Also, Japanese Patent Application Laid-Open No. 7-326670 and Japanese Patent Publication No.
As disclosed in Japanese Patent No. 4236, there is a method of intentionally providing a cavity so as to reduce the parasitic capacitance between adjacent wirings in order to speed up the operation of the semiconductor integrated circuit device.

As described above, when a cavity is formed between adjacent wirings, as shown in FIG.
If the via hole 113a does not completely lie on the lower wiring 112b due to a displacement during the formation of 3a and is also opened on the side surface thereof, the cavity 117 and the via hole 113a may be connected. In this state, via hole 11
When the conductive material 116 is embedded in 3a, the conductive material 1
16 penetrates into the cavity 117 and the via hole 113
a may not be completely embedded.

This causes a connection failure between the upper wiring and the lower wiring. In particular, when the cavity is intentionally provided, such a connection failure tends to occur, and the yield is greatly reduced.

Accordingly, the present invention provides a semiconductor integrated circuit device which prevents a poor connection between an upper wiring and a lower wiring due to incomplete filling of a via hole even if the distance between adjacent wirings in the same wiring layer is small. The purpose is to provide.

[0010]

The semiconductor integrated circuit device of the present invention for achieving the above object, according to an aspect of the on a semiconductor substrate, a semiconductor integrated circuit device formed through the wiring of at least two layers to one another insulating film, A plurality of lower layer wirings are arranged at a predetermined pitch, and at least one of the lower layer wirings includes:
The upper layer wiring is electrically connected by a conductive material embedded in a via hole provided in the insulating film, and a part of the lower layer wiring has a narrow portion.
The conductive material embedded in the via hole; and
It is characterized in that it is in contact with the lower wiring .

In the semiconductor integrated circuit device of the present invention configured as described above, a part of the lower wiring is a narrow portion.
Since that, in this portion, the interval between adjacent wires is wider. As a result, even if wirings in the lower layer are wired at a narrow pitch, no cavity of the insulating film is generated between the wirings. On the other hand,
The buried conductive material is embedded in the narrow part of the underlying wiring.
Is in contact with the wiring. Therefore, even if the position of the via hole is shifted, the via hole does not connect to the cavity, and the via hole is completely filled with the conductive material.

Further, in order to reduce the parasitic capacitance between the adjacent wirings, a cavity may be intentionally provided between the wirings in the insulating film, the wirings of which the lower wirings are designed to be the narrowest. Even in this case, since the space between the lower layer wiring and the adjacent wiring is large at the contact portion with the conductive material, no cavity is formed in this portion.

The “upper layer” and “lower layer” in the present invention are defined as
It does not mean absolute upper and lower layers, but means relative upper and lower layers in two wiring layers that are vertically overlapped. Therefore, in the case of a three-layer structure, the middle wiring layer becomes a lower wiring for the uppermost wiring layer and becomes an upper wiring for the lowermost wiring layer.

[0014]

Next, embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a diagram showing a first embodiment of a semiconductor integrated circuit device according to the present invention.
(A) is a main part plan view, (b) is a cross-sectional view taken along line AA of (a), and (c) is a cross-sectional view taken along line BB of (a).

As shown in FIG. 1, in the semiconductor integrated circuit device of the present embodiment, a plurality of lower wirings 1 are formed on a semiconductor substrate 11.
2a and 12b are formed at a predetermined pitch, and an upper layer wiring 14 is formed thereon with an insulating film 13 interposed therebetween.

The upper wiring 14 and the lower wiring 12b are electrically connected by a plug 15. The plug 15 is formed by depositing an insulating film 13 on the semiconductor substrate 11 on which the lower wirings 12a and 12b are formed, and then forming a via hole 13a in a portion of the insulating film 13 where the lower wiring 12b and the upper wiring 14 are connected. Then, the via hole 13a is filled with the conductive material 16. As the conductive material 16, a metal such as tungsten is used. The via hole 13a is buried by a chemical vapor deposition (CV) method.
D).

In the lower wiring 12b connected to the upper wiring 14 of the lower wirings 12a and 12b, the width of the contact portion with the plug 15 is smaller than the width of the other parts.
In the present embodiment, the width of the lower wirings 12a and 12b is set to 0.3.
μm, height 0.6 μm, spacing between adjacent lower-layer wirings 0.3 μm, and opening diameter of via hole 13 a 0.3 μm.
m. The width of a contact portion of the lower wiring 12b connected to the upper wiring 14 with the plug 15 is 0.24 μm.
And Thus, the plug 15 of the lower wiring 12b is
At the contact portion with the lower wiring 12a is 0.33 μm.

When the insulating film 13 is formed, the insulating film 13 is formed under film forming conditions such that the insulating film 13 can be completely buried between the lower wirings 12a and 12b. However, even in this case, it is not sufficiently buried due to manufacturing variations, and a cavity 17 may be formed between the lower wirings 12a and 12b as shown in FIG.
Such film formation conditions include, for example, a method in which the source gas is Si
There is a method of depositing an SiO ₂ film as the insulating film 13 by plasma CVD using H ₄ and O ₂ at a substrate bias of 1500 W. In the limit region of the embedding performance, even if the wiring interval is the same in design, there are some cases where complete embedding can be performed as described above due to manufacturing variations, but if the wiring interval is widened even a little, the lower wiring 1
The space between 2a and 12b can be reliably embedded.

In the present invention, the space between the lower wiring 12a connected to the upper wiring 14 and the adjacent lower wiring 12a is wide at the contact portion of the lower wiring 12b with the plug 15, so that no cavity 17 is formed in this portion. As a result, even if the via hole 13a formed in the insulating film 13 is displaced, the via hole 13a and the cavity 17 are not connected, and the filling of the conductive material 16 into the via hole 13a becomes incomplete. Therefore, contact failure between the upper wiring 14 and the lower wiring 12a does not occur.

Here, the structure in which the wiring width of the contact portion with the plug is widened as shown in FIG. 4 under the condition that the interval of the lower wiring is the same, and the wiring width is constant as shown in FIG. The yield was compared between the structure of Example 1 and the structure of the present embodiment. Here, the cavity is not intentionally provided.
As a result, it was about 80% in the structure having a fixed wiring width, whereas it was 100% in the structure in which the wiring width at the contact portion with the plug was widened and the structure of the present embodiment.

By the way, in the structure in which the contact portion with the plug is widened, the interval between adjacent wires is narrow at that portion, so that it is difficult to make the wiring pitch fine. On the other hand, in the structure of the present embodiment, since the wiring width is not widened, the cavity 17 is not formed between the adjacent lower wirings at the contact portion with the plug 15, and the plug 15 and the lower wiring 12 are not formed.
The wiring pitch can be further miniaturized within a range that does not affect the electrical connection with the wiring b.

(Second Embodiment) FIG. 2 is a view showing a semiconductor integrated circuit device according to a second embodiment of the present invention.
(A) is a main part plan view, (b) is a cross-sectional view taken along line CC of (a), and (c) is a cross-sectional view taken along line DD of (a).

In the present embodiment, the insulating film 23 is formed such that a cavity 27 is always formed in a portion having a design minimum wiring interval between adjacent lower wirings 22a and 22b. Other structures are the same as those of the first embodiment, and in particular, the lower wiring 22b connected to the upper wiring 24
The width of the lower wiring 22b is narrow at the contact portion with the plug 25. As described above, the adjacent lower layer wirings 22a,
As the film forming conditions for providing the cavity 27 between the lower wirings 22b, when the wiring spacing and the wiring height of the lower wirings 22a and 22b are the same as those in the first embodiment, for example, the source gas is SiH
_4. There is a method of depositing an SiO ₂ film as the insulating film 23 by plasma CVD using O ₂ and a substrate bias of 1200 W. As a result, the adjacent lower wirings 22a,
A cavity 27 is formed in a portion where the interval between the wirings 22b is minimum, but the lower wiring 22b connected to the upper wiring 24 is formed.
No cavity 27 is formed at the contact portion with the plug 25.

As a result, even if the via hole 23a formed in the insulating film 23 is displaced, a contact failure between the upper wiring 24 and the lower wiring 22b does not occur as in the first embodiment. Further, in the present embodiment, the adjacent lower wiring 2
A cavity 27 is provided at the portion where the interval between 2a and 22b is minimum.
Are formed, the parasitic capacitance between adjacent lower-layer wirings is reduced, and the speed of the semiconductor integrated circuit device can be increased.

Here, the yield was compared between the structure of this embodiment and the structure in which the wiring width is constant as shown in FIG. Here, both intentionally form a cavity. As a result, it was about 50% in the structure having a fixed wiring width, whereas it was 100% in the structure of the present embodiment.

Further, in the structure of this embodiment, the parasitic capacitance between the lower wirings 22a and 22b was measured when the wiring interval between the lower wirings 22a and 22b was 0.3 μm. For comparison, a semiconductor integrated circuit device manufactured in the same manner as in the present embodiment except that the wiring width of the lower layer wiring is fixed, that is, a semiconductor having a structure with a fixed wiring width as shown in FIG. With respect to the integrated circuit device, the parasitic capacitance was measured for the case where the cavity was intentionally provided and the case where the cavity was not provided intentionally. The results are shown in the graph of FIG. As is clear from this graph, the structure in which the cavity is intentionally provided (Comparative Example 2) has a lower parasitic capacitance than the structure in which the cavity is not intentionally provided (Comparative Example 1). In Example), a value equivalent to that obtained when the cavity was intentionally provided was obtained.

From the above comparison results, the semiconductor integrated circuit device of the present embodiment can achieve a high yield while reducing the parasitic capacitance between adjacent wirings.

In the above-described two embodiments, the case where one lower wiring is connected to the upper wiring has been described as an example. However, a structure in which two or more lower wirings are connected to the upper wiring may be adopted. Alternatively, two or more upper layer wirings may be provided. In the above two embodiments, the semiconductor integrated circuit device having a two-layer structure has been described as an example.
The present invention can also be applied to a semiconductor integrated circuit device having more than two layers. For example, a third wiring (not shown) is further formed on the upper wiring 14 shown in FIG. 1 on a second insulating film (not shown) formed so as to cover the insulating film 13 and the upper wiring 14.
When the third wiring and the upper wiring 14 are connected by a second plug (not shown) provided in the second insulating film,
The width of the contact portion of the upper layer wiring 14 with the second plug is narrower than other portions.

[0030]

As described above, according to the present invention, the lower layer wiring is made to have a narrow width and the conductive layer embedded in the via hole is formed.
By contacting the material and the underlying wiring at this narrow part ,
Even if the lower layer wiring is arranged at a narrow pitch, it is possible to prevent poor contact between the upper layer wiring and the lower layer wiring due to insufficient filling of the conductive material due to positional deviation of the via hole.

In addition, by intentionally providing a cavity between the wirings in which the wiring of the lower layer of the insulating film is designed to be narrowest, the parasitic capacitance between adjacent wirings can be reduced.
The speed of the semiconductor integrated circuit device can be increased.

[Brief description of the drawings]

1A and 1B are diagrams showing a first embodiment of a semiconductor integrated circuit device of the present invention, wherein FIG. 1A is a plan view of a main part thereof, FIG. 1B is a cross-sectional view taken along line AA of FIG. () Is a sectional view taken along line BB of (a).

FIGS. 2A and 2B are diagrams showing a second embodiment of the semiconductor integrated circuit device of the present invention, wherein FIG. 2A is a plan view of a main part thereof, FIG. 2B is a cross-sectional view taken along line CC of FIG. () Is a sectional view taken along line DD in (a).

FIG. 3 is a graph showing the parasitic capacitance between adjacent wires in the structure according to the second embodiment of the present invention and the conventional structure.

4A and 4B are diagrams showing an example of a conventional semiconductor integrated circuit device, wherein FIG. 4A is a plan view of a main part thereof, and FIG.
It is a line sectional view.

FIG. 5 is a main part plan view of another example of the conventional semiconductor integrated circuit device.

6 is a sectional view taken along line FF of the semiconductor integrated circuit device shown in FIG.

FIG. 7 is a cross-sectional view for describing a problem in a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 11, 21 Semiconductor substrate 12a, 12b, 22a, 22b Lower wiring 13, 23 Insulating film 13a, 23a Via hole 14, 24 Upper wiring 15, 25 Plug 16 Conductive material 17, 27 Cavity

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/3205-21/3213 H01L 21/768

Claims (2)

(57) [Claims] 1. A semiconductor integrated circuit device in which at least two wiring layers are formed on a semiconductor substrate via an insulating film.
, A plurality of lower-layer wirings are arranged at a predetermined pitch, and at least one of the lower-layer wirings is electrically connected to an upper-layer wiring by a conductive material embedded in a via hole provided in the insulating film. A part of the lower wiring is a narrow portion, and the narrow portion is
And the conductive material embedded in the via hole
A semiconductor integrated circuit device, wherein the lower layer wiring is in contact with the lower layer wiring . 2. The semiconductor integrated circuit device according to claim 1, wherein the insulating film has a cavity between the wirings in which the lower wiring is designed to have the smallest spacing.