JP3256977B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multilayer metal wiring.

[0002]

2. Description of the Related Art An increase in the aspect ratio of an interlayer connection hole due to miniaturization has caused a problem that conventional metal sputtering techniques cannot maintain sufficient step coverage in an interlayer connection hole.

[0005] Deterioration of step coverage causes disconnection of wiring and deterioration of long-term reliability.

In recent years, in order to solve this problem, a pillar method has been used in which metal columns are formed in advance at predetermined positions for interlayer connection. FIG. 3 shows a vertical cross-sectional view of the interlayer connection portion formed by using the pillar method. An oxide film 2 is formed on a semiconductor substrate 1 as an insulating film. On the oxide film 2, a metal film 3 having a thickness of about 1000 ° and a lower wiring 4 made of a lower wiring metal having a thickness of 2 μm are formed. On the lower wiring 4, an interlayer connecting portion 6 having a height of about 2 μm is formed.
The upper wiring composed of the metal film 8 and the upper wiring metal 9 is connected to the lower wiring. The thicknesses of the metal film 8 and the upper wiring metal 9 may be about 1000 ° and 2 μm, respectively, similarly to the lower wiring. The thickness of the interlayer film 7 is adjusted so that the upper end of the interlayer connection portion 6 is exposed on the interlayer film.

In the pillar method, an interlayer connection portion 6 is formed in advance at a position where interlayer connection is to be formed, and etch-back is performed after formation of an interlayer film 7 to expose an upper end of the interlayer connection portion 6. There is an advantage that it becomes unnecessary.

[0006]

In the conventional semiconductor device, when the interlayer film 7 is formed, its film thickness depends on the shape of the lower portion of the interlayer film. A film thickness difference of about twice. Therefore, when the interlayer film 7 is etched back to expose the upper end of the interlayer connection portion, as shown in FIG. 4, the upper portion of the lower wiring in the region where the interlayer thickness is small is also exposed, and a short circuit with the upper wiring is caused. There was a serious problem that occurred.

An object of the present invention is to provide a semiconductor device which solves the above-mentioned problems.

[0008]

In order to achieve the above object, a semiconductor device according to the present invention is characterized in that upper and lower metal wirings are connected by using a pillar method, and a pattern dense region and
A semiconductor device having a pattern isolated region in which the thickness of an interlayer insulating film is relatively thinner than that of an interlayer insulating film on the pattern dense region, wherein the semiconductor device has a pattern isolated region on a metal wiring or between metal wires on the pattern dense region. an interlayer insulating film is also inclusive portion is configured differently from the material of the upper and lower layers, the etching rate of the upper layer of the interlayer insulating film is at least three times the etching rate of the lower layer of the interlayer insulating film, the pattern isolated region
The interlayer insulating film on the metal wiring of at least the lower layer
It is composed of an inter-insulating film .

[0009]

In a multi-layer metal wiring for connecting between upper and lower metal wirings by using a pillar method, an interlayer insulating film between the metal wirings is made of two different materials, upper and lower, to prevent the lower wiring from being exposed by etch back. Is what you do.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a longitudinal sectional view showing Embodiment 1 of the present invention.

In FIG. 1, a lower wiring composed of a metal film 3 and a lower wiring 4 is formed on an insulating film 2 on a semiconductor substrate 1. The thickness of each of the metal film 3 and the lower wiring 4 is 10
It is about 00 ° and about 2 μm thick.

An oxide film 5 having a thickness of about 5000 ° is formed on the upper surface of the lower wiring 4 except for a portion in contact with the interlayer connection portion 6.

A metal film 8 having a thickness of about 1000 ° and a thickness of 2 μm
The upper wiring composed of about m upper wirings 9 is connected to the lower wiring via the interlayer connection 6.

Since the oxide film 5 is present on the entire surface of the lower wiring 4 except for the interlayer connection, even if the interlayer film 7 is etched back to expose the upper surface of the interlayer connection 6, an isolated region of the pattern is formed. Is not exposed, and no short circuit occurs with the upper wiring. Here, the interlayer film 7 must be made of a material whose etching rate is three times or more greater than that of the oxide film 5. Conversely, the same effect can be obtained even if the oxide film 5 on the lower wiring is replaced with an insulator whose etching rate is 1/3 or less of the interlayer film 7.

(Embodiment 2) FIG. 2 is a longitudinal sectional view showing Embodiment 2 of the present invention.

This embodiment is different from the first embodiment in that the interlayer film 7
Oxide film 5 underneath is formed on the entire surface except for the interlayer connection portion.

Therefore, the thickness of the interlayer film 7 in the isolated region becomes extremely thin, and short-circuit with the upper wiring does not occur even if the side surface of the lower wiring 4 is exposed after the etch back.

[0019]

As described above, according to the present invention, in a multi-layer metal wiring for performing interlayer connection using the pillar method, the interlayer film has a two-layer structure made of different materials, so that the upper end of the interlayer connection metal is formed by etch back. There is an effect that the lower wiring is not exposed at the time of exposure, so that a short circuit of the upper and lower wiring can be prevented.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a first embodiment of the present invention.

FIG. 2 is a longitudinal sectional view showing a second embodiment of the present invention.

FIG. 3 is a longitudinal sectional view showing a conventional example.

FIG. 4 is a longitudinal sectional view showing a problem in a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2, 5 Oxide film 3, 8 Metal film 4 Lower wiring 6 Interlayer connection part 7 Interlayer film 9 Upper wiring

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/3205 H01L 21/3213 H01L 21/768

Claims (1)

(57) [Claims] 1. The upper and lower metal wirings are connected using a pillar method.
While being, a semiconductor device having a pattern dense region, and a thickness of the pattern dense compared to the interlayer insulating film on the region becomes relatively thin pattern isolated region of the interlayer insulating film, the pattern dense region The interlayer insulating film on the upper metal wiring or the portion including between the metal wirings is composed of upper and lower two different materials, and the etching rate of the upper interlayer insulating film is lower than the etching rate of the lower interlayer insulating film. 3 times or more, the interlayer insulation on the metal wiring in the pattern isolated area
The edge film is composed of at least the lower interlayer insulating film.
Wherein a is.