JPH04302455A - Semiconductor device - Google Patents

Abstract

PURPOSE:With regard to multilayer interconnection, in which electrical connections between layers are formed by employing a pillar technique, to prevent a lower layer of wire from being exposed when the top end of an interlayer connector is exposed by etching back and interlayer film. CONSTITUTION:An oxide film 5 is deposited on a lower layer of wire 4 which has no interlayer connector 6. When the material, which is three times larger than the oxide film 5 in etch rate, is used for the interlayer film 7, it becomes possible to prevent the lower layer of wire 4 from being revealed when the top end of the interlayer connector 6 is exposed by etching back the interlayer film.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having multilayer metal wiring.

0002

2. Description of the Related Art The increase in the aspect ratio of interlayer contact holes due to miniaturization has created a problem in that conventional metal sputtering techniques cannot maintain sufficient step coverage in the interlayer contact hole portions.

[0003] Deterioration of step coverage causes wire breakage and deterioration of long-term reliability.

In recent years, in order to solve this problem, a pillar method has been used in which metal pillars are formed in advance at the planned locations for interlayer connections. FIG. 3 shows a longitudinal cross-sectional view of an interlayer connection formed using the pillar method. An oxide film 2 is formed on a semiconductor substrate 1 as an insulating film. On this oxide film 2, a metal film 3 with a thickness of about 1000 Å and a lower wiring 4 made of a lower wiring metal with a thickness of 2 μm are formed. An interlayer connection part 6 with a height of about 2 μm is formed on the lower layer wiring 4.
The upper layer wiring made of the metal film 8 and the upper layer wiring metal 9 is connected to the lower layer wiring. Note that the film thicknesses of the metal film 8 and the upper layer wiring metal 9 may be approximately 1000 Å and 2 μm, respectively, similar to the lower layer wiring. The thickness of the interlayer film 7 is adjusted so that the upper end of the interlayer connection portion 6 is exposed on the interlayer film.

In the pillar method, the interlayer connection part 6 is formed in advance at the planned position of the interlayer connection, and after the formation of the interlayer film 7, etching back is performed to expose the upper end of the interlayer connection part 6. This has the advantage that it is not necessary.

[0006]

[Problems to be Solved by the Invention] In a conventional semiconductor device, when the interlayer film 7 is formed, the film thickness depends on the shape of the lower part of the interlayer film, and is thicker in areas with dense patterns and thinner in areas with sparse patterns, and in extreme cases. , a difference in film thickness of approximately twice that occurs. Therefore, when the interlayer film 7 is etched back to expose the upper end of the interlayer connection part, the upper part of the lower layer wiring in the area where the interlayer film thickness is thin is also exposed, as shown in FIG. There was a serious problem that occurred.

An object of the present invention is to provide a semiconductor device that solves the above problems.

[0008]

[Means for Solving the Problems] In order to achieve the above-mentioned object, a semiconductor device according to the present invention provides a multi-layer metal wiring for connecting upper and lower metal wirings using a pillar method. The interlayer insulating film is composed of upper and lower layers made of different materials.

[0009]

[Function] In multilayer metal wiring that connects upper and lower metal wiring using the pillar method, the interlayer insulating film between the metal wiring is composed of two layers of different materials, preventing exposure of the lower layer wiring due to etchback. It is something to do.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

(Embodiment 1) FIG. 1 is a longitudinal sectional view showing Embodiment 1 of the present invention.

In the figure, a lower interconnection consisting of a metal film 3 and a lower interconnection 4 is formed on an insulating film 2 on a semiconductor substrate 1. As shown in FIG. The thickness of the metal film 3 and the lower layer wiring 4 are each 10
The thickness is approximately 00 Å and 2 μm.

An oxide film 5 having a thickness of approximately 5000 Å is formed on the upper surface of the lower wiring 4, except for the portion in contact with the interlayer connection portion 6.

Metal film 8 with a thickness of about 1000 Å and a thickness of 2 μm
The upper layer wiring, which is composed of approximately m upper layer wirings 9, is connected to the lower layer wiring via the interlayer connection portion 6.

Since the oxide film 5 is present on the entire surface of the interconnection 4 except for the interlayer connection part, even if the interlayer film 7 is etched back to expose the upper surface of the interlayer connection part 6, the pattern will not be isolated. The lower layer wiring 4 in the area is not exposed and no short circuit with the upper layer wiring occurs. Here, the interlayer film 7 must be made of a material whose etching rate is three times or more higher than that of the oxide film 5. Conversely, the same effect can be obtained even if the oxide film 5 on the lower wiring is replaced with an insulator whose etching rate is ⅓ or less compared to the interlayer film 7.

(Embodiment 2) FIG. 2 is a longitudinal sectional view showing Embodiment 2 of the present invention.

This embodiment differs from Embodiment 1 in that the interlayer film 7
An oxide film 5 underneath is formed over the entire surface except for interlayer connections.

Therefore, the thickness of the interlayer film 7 in the isolated region becomes extremely thin, and even if the side surface of the lower layer wiring 4 is exposed after etching back, no short circuit with the upper layer wiring occurs.

[0019]

Effects of the Invention As explained above, the present invention provides a multilayer metal wiring in which interlayer connections are made using the pillar method, by forming the interlayer film into a two-layer structure made of different materials, so that the upper end of the metal at the interlayer connection by etchback can be removed. This has the effect that the lower layer wiring is not exposed during exposure, thereby preventing short circuits between the upper and lower layer wiring.

[Brief explanation of drawings]

FIG. 1 is a longitudinal cross-sectional view showing Example 1 of the present invention.

FIG. 2 is a longitudinal sectional view showing a second embodiment of the present invention.

FIG. 3 is a longitudinal sectional view showing a conventional example.

FIG. 4 is a vertical cross-sectional view showing problems in the conventional example.

[Explanation of symbols] 1 Semiconductor substrate 2,5 Oxide film 3,8 Metal film 4 Lower layer wiring 6 Interlayer connections 7 Interlayer film 9 Upper layer wiring

Claims (1)

[Claims] Claim 1: A multilayer metal wiring that connects upper and lower metal wiring using the pillar method, wherein the interlayer insulating film between the metal wiring is composed of two different materials, the upper and lower layers. A semiconductor device characterized by: