JP3216124B2 - Semiconductor thin film device and method of manufacturing the same - Google Patents

Semiconductor thin film device and method of manufacturing the same

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Publication number
JP3216124B2
JP3216124B2 JP35086198A JP35086198A JP3216124B2 JP 3216124 B2 JP3216124 B2 JP 3216124B2 JP 35086198 A JP35086198 A JP 35086198A JP 35086198 A JP35086198 A JP 35086198A JP 3216124 B2 JP3216124 B2 JP 3216124B2
Authority
JP
Japan
Prior art keywords
layer
insulating film
layer wiring
interlayer insulating
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP35086198A
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Japanese (ja)
Other versions
JP2000174128A (en
Inventor
稔秋 高田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Filing date
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Publication of JP2000174128A publication Critical patent/JP2000174128A/en
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Publication of JP3216124B2 publication Critical patent/JP3216124B2/en
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Expired - Lifetime legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体薄膜装置及
びその製造方法に関し、より詳細には使用するレジスト
の損傷によるピンホール生成等を生じさせることなく、
正確なプロフィールを有する積層が成できる半導体薄膜
装置及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor thin film device and a method of manufacturing the same, and more particularly, to a method for manufacturing a semiconductor thin film device without generating pinholes due to damage to a resist used.
The present invention relates to a semiconductor thin film device capable of forming a lamination having an accurate profile and a method of manufacturing the same.

【0002】[0002]

【従来の技術】一般に半導体装置では、素子の高密度化
及び高速化が進行し、多層配線構造が汎用されている。
図10に多層配線構造である従来のライトバルブ画素の
断面図を示す。この多層配線構造では、第1層のTi/
Alと第3層のITOを接続するため、1−3層間の絶
縁膜として、平坦化膜/窒化膜/窒化膜の合計1.6μ
mを一気にエッチングして、尚且つ、1層の500
1000のTiを残すエッチングを行う。エッチング
開口後、その上にITOの3層配線を形成する。
2. Description of the Related Art Generally, in semiconductor devices, the density and speed of elements have been increasing, and multilayer wiring structures have been widely used.
FIG. 10 is a cross-sectional view of a conventional light valve pixel having a multilayer wiring structure. In this multilayer wiring structure, the first layer Ti /
In order to connect Al and the ITO of the third layer, a total of 1.6 μm of a flattening film / nitride film / nitride film is used as an insulating film between layers 1-3.
m at a stretch, and one layer of 500 Å
Performing etching to leave the Ti of 1000 Å. After the etching opening, an ITO three-layer wiring is formed thereon.

【0003】[0003]

【発明が解決しようとする課題】ライトバルブの画素に
おいて、3層ITO−1層Ti/Al接続のためのスル
ホールのエッチングが深いためにエッチ量が多く、膜
厚、エッチレート等のバラツキを考慮するとTiを残し
て、エッチングすることが難しく、通常、それぞれ10
%程ばらついてしまう。また、エッチ時間が長くなるこ
とから、マスクとして用いていたレジストが先になくな
り、マスク材としての役割をなさなくなるという問題が
あり、容易に接続することができなかった(図11)。
In the light valve pixel, the etching amount is large due to the deep etching of the through hole for the three-layer ITO-1 layer Ti / Al connection, and variations in the film thickness and the etching rate are taken into consideration. Then, it is difficult to etch while leaving Ti.
%. Further, since the etching time becomes longer, the resist used as a mask is lost first, and there is a problem that it does not play a role as a mask material, so that it was not possible to easily connect (FIG. 11).

【0004】また図12の構造では、1−3層間スルー
ホールを一度で開口しようとするとホトレジストが形状
を維持できず、その下の2−3層間絶縁膜もエッチング
されて2層配線上にピンホールが発生して2層配線と3
層配線がショートしてしまう。更に図13の構造でも、
2層配線と3層配線が2−3層間絶縁膜のピンホールで
ショートすることがある。図13の構造では、1−2層
間絶縁膜と2−3層間絶縁膜の合計の厚さをエッチング
開口しなければならないため、上述の通りレジスト形状
が維持出来ないか、図14に示す通りエッチング不足に
なり、たとえ開口出来ても図15に示すようにバリアメ
タル層を残すことが難しくなる。これらの問題点が生ず
る理由は上述の通り、1−3層間の、例えば絶縁膜の平
坦化膜/窒化膜/窒化膜(合計1.6μm)を一気にエ
ッチングするため、エッチング時間が長く、レジストの
形状が維持出来なくなるからである。更に、SiNとT
iの選択比が20くらい大きくても、ばらつきを考慮す
るとTiがなくなることがある(図15)。
In the structure shown in FIG. 12, if the through hole of the first through third layers is opened at once, the photoresist cannot maintain its shape, and the second through third interlayer insulating film is also etched to form a pin on the second layer wiring. Holes are generated and two-layer wiring and 3
The layer wiring is short-circuited. Further, in the structure of FIG.
The two-layer wiring and the three-layer wiring may be short-circuited by a pinhole in the 2-3 interlayer insulating film. In the structure shown in FIG. 13, since the opening must be opened by the total thickness of the 1-2 interlayer insulating film and the 2-3 interlayer insulating film, the resist shape cannot be maintained as described above, or the etching is performed as shown in FIG. becomes insufficient, can leave the barrier metal layer as shown in FIG. 15 becomes harder made if the opening. The reason why these problems occur is that, as described above, since, for example, the flattening film / nitride film / nitride film (total 1.6 μm) of the insulating film between the 1-3 layers is etched at once, the etching time is long, and This is because the shape cannot be maintained. Furthermore, SiN and T
Even when the selectivity of i is as large as about 20, Ti may disappear in consideration of the variation (FIG. 15).

【0005】[0005]

【課題を解決するための手段】本発明に係る半導体薄膜
装置は、1層配線と、1層配線表面に被覆された一部に
スルーホールが形成された1−2層間絶縁膜と、該1−
2層間絶縁膜表面と前記スルーホール内側側壁と該スル
ーホール底面に露出した前記1層配線表面を被覆し表面
側に開口部を有する2層配線と、前記開口部の内側側壁
の2層配線上に形成されたバリアメタル層と、少なくと
も前記開口部底面の2層配線と前記バリアメタル層に接
触しかつ前記開口部及び2−3層間絶縁膜を被覆してい
る透明導体膜を含んでなることを特徴とする半導体薄膜
装置であり、この積層構造は後述する本発明方法により
製造できる。
According to the present invention, there is provided a semiconductor thin-film device comprising a single-layer wiring and a part covered on the surface of the single-layer wiring.
A 1-2 interlayer insulating film in which a through hole is formed;
The surface of the two interlayer insulating film, the inner side wall of the through hole and the through hole
-Cover the surface of the single-layer wiring exposed at the bottom of the hole
Wiring having an opening on the side, and an inner side wall of the opening
Barrier metal layer formed on the two-layer wiring of
Also contacts the two-layer wiring at the bottom of the opening and the barrier metal layer.
A semiconductor thin film device comprising a transparent conductor film that touches and covers the opening and the 2-3 interlayer insulating film, and the laminated structure can be manufactured by the method of the present invention described later.

【0006】[0006]

【発明の実施の形態】以下に、本発明を詳細に説明す
る。本発明の特徴は、バリアメタル層及び該層を挟む2
層を横方向に積層接続することにより、エッチング量を
少なくして、長時間のエッチングによりレジストが損傷
しないようにし、これによりレジスト損傷によるピンホ
ール形成等の問題点が解消できる。具体的には、溝のあ
る下地配線、例えばAlの溝を利用する。スルーホール
形成で露出したAl溝の側面にバリアメタルのTiを残
し、全面に透明電極のITOを乗せると、溝側面でAl
−Ti−ITOの構成となる。図1に具体的な断面図を
示したプロジェクター用ライトバルブの画素は、開口率
を上げるために、画素周辺に素子、配線を配置し、最後
に透明電極としてITOを用いている。ITOは、3層
目にあり、1層目の配線と接続して電極としている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail. The feature of the present invention is that the barrier metal layer and
By laminating and connecting the layers in the lateral direction, the amount of etching is reduced, so that the resist is not damaged by long-time etching, whereby problems such as pinhole formation due to resist damage can be solved. Specifically, an underlying wiring having a groove, for example, an Al groove is used. When the barrier metal Ti is left on the side surface of the Al groove exposed by the formation of the through hole and the ITO of the transparent electrode is put on the entire surface, the Al
-Ti-ITO configuration. In the pixel of the light valve for a projector whose specific cross-sectional view is shown in FIG. 1, elements and wirings are arranged around the pixel in order to increase the aperture ratio, and finally, ITO is used as a transparent electrode. ITO is in the third layer and is connected to the first layer wiring to form an electrode.

【0007】1層配線のAlと3層目のITOを接続す
る場合に、AlとITOを直接に接続するとITOの酸
素によって、Al表面が酸化しアルミナになるため、導
通がとれなくなる。そのため、間にTiを挟み、ITO
からの酸素のバリアとすることで、導通をとることは、
一般に良く知られている。しかし、2−3層間絶縁膜と
1−2層間絶縁膜を合わせた非常に厚い絶縁膜を1Al
上にバリアメタルのTiを残して、エッチング開口する
ことは難しい。また、段差も大きく、急峻なため、3層
目のITOも断線する。
In the case where Al of the first layer wiring is connected to ITO of the third layer, if Al is directly connected to ITO, the oxygen of the ITO oxidizes the Al surface to become alumina, so that conduction cannot be established. Therefore, insert Ti between them and use ITO
By making it a barrier for oxygen from
Generally well known. However, a very thick insulating film combining the 2-3 interlayer insulating film and the 1-2 interlayer insulating film is formed of 1Al.
It is difficult to form an etching opening while leaving the barrier metal Ti thereon. Further, since the step is large and steep, the ITO of the third layer is also disconnected.

【0008】本発明は、このライトバルブ配線系の異層
間における配線接続の問題点を改善する提案であり、以
下に、本発明の実施形態例を説明する。図2は、本発明
の代表例について示した断面図であり、この代表例の製
造方法について、図3〜7を用いて説明する。1層配線
1上の1−2層間絶縁膜2を異方性エッチングで開口
し、1−2層間スル−ホール(開口部)3を形成して凹
部とする(図3)。その上に、孤立パターンの2層メタ
ルを2層配線4形成時に、前記開口部3を覆うように乗
せる。このとき、前記孤立パターンのAl2層配線4上
にTiやCr製のバリアメタル層5を形成しておき(図
4)、この際に前記1−2層間スルーホール3の形状に
対応して2層配線4の開口部の内壁にもバリアメタル層
5が形成される。
The present invention is a proposal for improving the problem of wiring connection between different layers of the light valve wiring system, and an embodiment of the present invention will be described below. FIG. 2 is a cross-sectional view showing a representative example of the present invention. A method of manufacturing the representative example will be described with reference to FIGS. An opening is formed in the 1-2 interlayer insulating film 2 on the single-layer wiring 1 by anisotropic etching, and a through hole (opening) 3 for the 1-2 interlayer is formed as a concave portion (FIG. 3). A two-layer metal having an isolated pattern is placed thereon so as to cover the opening 3 when the two-layer wiring 4 is formed. At this time, a barrier metal layer 5 made of Ti or Cr is formed on the Al2 layer wiring 4 of the isolated pattern (FIG. 4). The barrier metal layer 5 is also formed on the inner wall of the opening of the layer wiring 4.

【0009】次に、その上に、2−3層間絶縁膜6を形
成する(図5)。この2−3層間絶縁膜6は上面を平坦
化するため必然的に使用量が多くなる。次いで1−2層
間スルーホール3と、ほぼ同一の大きさで異方性エッチ
ング(RIE)し、2−3層間スルーホール7を開口す
る(図6)。このとき、1−2層間スルーホール3の段
に沿って、2層配線のAlとTiも形成されており、異
方性エッチングのオーバーエッチで、底部のTiが無く
なっても、前記段の側面にTiが残り、プロセスマージ
ンを大きくとることが出来る。バリアメタル層5のTi
の膜厚は、コンタクト抵抗の関係から300−1000
程度と薄く形成してある。次に、3層目のITO8を
形成すると前記段の側面でAl−Ti−ITOの構造が
出来上がり、良好な導通が得られるようになる。(図
7)。
Next, a 2-3 interlayer insulating film 6 is formed thereon (FIG. 5). The use amount of the 2-3 interlayer insulating film 6 is inevitably increased because the upper surface is flattened. Next, anisotropic etching (RIE) is performed with the same size as that of the through hole 3 between the first and second layers to open a through hole 7 between the second and third layers (FIG. 6). At this time, Al and Ti of the two-layer wiring are also formed along the step of the 1-2 interlayer through-hole 3, and even if Ti at the bottom is lost due to an overetch of anisotropic etching, the side surface of the step is removed. , Ti remains, and the process margin can be increased. Ti of barrier metal layer 5
Is 300-1000 from the relation of contact resistance.
It is formed as thin as Å . Next, when a third layer of ITO 8 is formed, a structure of Al-Ti-ITO is completed on the side surface of the step, and good conduction can be obtained. (FIG. 7).

【0010】本実施例によると、工程を増やさず、1−
2層間膜2と2−3層間膜6の積層の厚い膜の開口を容
易にし、プロセスマージンを増やすことができる。ま
た、接続に側面を利用するため、断切れなどの不具合も
防止できる。そのため、層間接続間の不具合が改善さ
れ、歩留まりが向上する。具体的な実施例として挙げた
プロジェクタ用ライトバルブの例では、ITO電極8と
1Al1の接続が良くなることにより、画素が正常に動
作し、画素が動作していない状況(点欠陥)が解消さ
れ、欠陥のない画像を得ることが出来る。通常、1−2
層間膜2と2−3層間膜6が合わさったような厚い絶縁
膜(1−2μm)をTiのような薄いバリアメタル5
(500−1000)を残して開口することは、プロ
セスマージンを考慮するとTiとの選択比を20−40
以上確保しなければならない。しかし、ガラス基板のよ
うな広い基板を高選択比でエッチングすることは、不可
能であり、せいぜい15までである。
According to this embodiment, the number of steps is increased without increasing the number of steps.
It is possible to easily open a thick film of the laminated structure of the two-layered film 2 and the 2-3-layered film 6, and to increase a process margin. Further, since the side surface is used for the connection, troubles such as disconnection can be prevented. Therefore, the problem between the interlayer connections is improved, and the yield is improved. In the example of the projector light valve as a specific example, the connection between the ITO electrode 8 and 1Al1 is improved, so that the pixel operates normally and the situation where the pixel does not operate (point defect) is solved. And an image without defects can be obtained. Usually 1-2
A thick insulating film (1-2 μm) such that the interlayer film 2 and the 2-3 interlayer film 6 are combined with a thin barrier metal 5 such as Ti
Opening while leaving (500-1000 ° ) makes it possible to increase the selectivity with Ti by 20-40 in consideration of the process margin.
More than that. However, it is impossible to etch a wide substrate such as a glass substrate with a high selectivity, and it is up to 15 at most.

【0011】本発明は、1−2層間膜2のスルーホール
開口工程を利用して形成した開口部に上部にTi(バリ
アメタル層5)を堆積した2Al(2層配線4)を乗
せ、その上部に形成した2−3層間膜6を1−2層間膜
スルーホール2とほぼ同じ大きさで開口する。このと
き、開口の深さは、1−2層間膜スルーホール開口と2
−3層間膜スルーホール開口に分けて垂直に異方性エッ
チングしているため、エッチング深さが浅くなり、Ti
との選択比が従来の半分程度で良いことになる。さら
に、1−2層間膜スル−ホール2の段により形成された
側面の2Al4上のTi5は、異方性エッチングのサイ
ドウォール形成と同じ原理で側面に残る。2−3層間膜
スル−ホール6のオーバーエッチで底部のTiがなくな
っても、垂直の高さ分だけの厚みがあるのと同じで確実
に残すことが出来る。そのため、その上部に透明電極の
ITO8を形成しても段側面では、確実に、Al−Ti
−ITOの構造が出来上がりAlがITOの酸素によっ
て、酸化して接続不良となることがなくなる。この酸化
は、上部にだけ影響を及ぼすため、側面でAl−Ti−
ITOの構造が出来ていれば、確実に導通させることが
できる。そのため、プロセスマージンを大きくとること
ができ、画素歩留まりを確実に向上できる。
According to the present invention, 2Al (two-layer wiring 4) on which Ti (barrier metal layer 5) is deposited is placed on the opening formed by using a through-hole opening step of the 1-2 interlayer film 2, and the opening is formed. The 2-3 interlayer film 6 formed on the upper portion is opened with substantially the same size as the 1-2 interlayer film through hole 2. At this time, the depth of the opening is the same as that of the 1-2 interlayer film through hole opening.
-3 interlayer anisotropic etching is performed vertically in the through hole opening, so that the etching depth becomes shallow and Ti
Is about half the conventional ratio. Further, Ti5 on 2Al4 on the side surface formed by the step of the 1-2 interlayer film through-hole 2 remains on the side surface according to the same principle as the formation of the sidewall in the anisotropic etching. Even if Ti at the bottom is lost by overetching the 2-3 interlayer film through-hole 6, it can be surely left as it has a thickness corresponding to the vertical height. Therefore, even if the transparent electrode ITO8 is formed on the upper side, the Al-Ti
-The structure of ITO is completed, and Al is not oxidized by the oxygen of ITO to cause a connection failure. Since this oxidation affects only the upper part, Al-Ti-
If the structure of ITO is made, conduction can be ensured. Therefore, the process margin can be increased, and the pixel yield can be reliably improved.

【0012】次に本発明の層間接続の応用として他の実
施例について、簡単に述べる。1−2層間配線の接続で
あっても、絶縁膜が厚くて接続が難しい場合には本発明
が有効である。下地の段を利用して、層間接続する部分
に第1配線を通るようにパターンを設計しておくと、そ
の下地の段で転写された第1配線の段の側面にもバリア
メタル又は、緩衝メタルがある。そして、次のスルーホ
ール工程で、その上部の層間絶縁膜を異方性(RIE)
でエッチングすると、たとえ、オーバーエッチしても側
面にバリアメタル又は、緩衝メタルが残り、第2配線と
の接続が容易にできる。図8は、2−3層間の接続につ
いて示した断面図で、どの層間でも適用できる。図9
は、下地パターンと層間接続スルーホールの位置関係を
示す平面図で、下地の段のパターンは、四角形でもスト
ライプ状でも良く、上部のスルーホールパターンがこの
段にかかっていれば、段の側面にバリアメタルが残り、
確実に接続することができる。また、段の形状も階段状
でも良く、垂直面にバリアメタルまたは、緩衝メタルが
残るような構造であれば良いことになる。
Next, another embodiment will be briefly described as an application of the interlayer connection of the present invention. The present invention is effective when connection is difficult due to a thick insulating film even in connection of 1-2 interlayer wiring. If a pattern is designed so as to pass through the first wiring through a portion connected between layers by using a lower layer, a barrier metal or a buffer may be formed on the side surface of the lower layer transferred on the first wiring. There is metal. Then, in the next through hole process, the interlayer insulating film on the upper portion is anisotropically (RIE).
Even if overetching is performed, the barrier metal or the buffer metal remains on the side surface even if overetching is performed, and connection with the second wiring can be easily performed. FIG. 8 is a cross-sectional view showing the connection between the 2-3 layers, and can be applied to any layer. FIG.
Is a plan view showing the positional relationship between the underlying pattern and the interlayer connection through-holes.The pattern of the underlying step may be square or striped, and if the upper through-hole pattern covers this step, Barrier metal remains,
Connection can be made securely. Also, the shape of the step may be stepped, and any structure may be used as long as the barrier metal or the buffer metal remains on the vertical surface.

【0013】[0013]

【発明の効果】本発明は、1層配線と、1層配線表面に
被覆された一部にスルーホールが形成された1−2層間
絶縁膜と、該1−2層間絶縁膜表面と前記スルーホール
内側側壁と該スルーホール底面に露出した前記1層配線
表面を被覆し表面側に開口部を有する2層配線と、前記
開口部の内側側壁の2層配線上に形成されたバリアメタ
ル層と、少なくとも前記開口部底面の2層配線と前記バ
リアメタル層に接触しかつ前記開口部及び2−3層間絶
縁膜を被覆している透明導体膜を含んでなることを特徴
とする半導体薄膜装置(請求項1)である。この半導体
薄膜装置は、2層配線にスルーホールが形成され、この
部分で水平方向に2層配線−バリアメタル層−透明導体
膜の3層構造が実現されるため、導通が確実になる。し
かも接続に側面を利用するため、断切れなどの不具合も
防止でき、そのため層間接続間の不具合が改善され、歩
留まりが向上する。
According to the present invention, the single-layer wiring and the surface of the single-layer wiring are provided.
1-2 layers with through holes formed in part of the coating
An insulating film, the surface of the 1-2 interlayer insulating film, and the through hole
The one-layer wiring exposed on the inner side wall and the bottom of the through hole
A two-layer wiring covering the surface and having an opening on the surface side;
Barrier meta formed on the two-layer wiring on the inner side wall of the opening
Layer, at least two-layer wiring on the bottom of the opening, and the
A semiconductor thin film device (Claim 1) comprising a transparent conductor film in contact with a rear metal layer and covering the opening and the 2-3 interlayer insulating film. In this semiconductor thin film device, through-holes are formed in the two-layer wiring, and a three-layer structure of the two-layer wiring, the barrier metal layer, and the transparent conductor film is realized in this portion in the horizontal direction, so that conduction is ensured. In addition, since the side surface is used for the connection, problems such as disconnection can be prevented, so that problems between the interlayer connections are improved, and the yield is improved.

【0014】前記3層構造の材質は、2層配線の材質が
Al、バリアメタル層の材質がTi、透明導体膜の材質
がITOとなるように(請求項2)選択することが最適
である。又前記半導体薄膜装置を製造するプロセス(請
求項3)を使用すると、3層に跨がるような大きなエッ
チングが不要になり、従ってエッチング操作間にレジス
トの形状が保持されて正確なプロフィールを有する素子
が形成できる。
The material of the three-layer structure is optimally selected so that the material of the two-layer wiring is Al, the material of the barrier metal layer is Ti, and the material of the transparent conductor film is ITO. . The use of the process for manufacturing a semiconductor thin film device (claim 3) eliminates the need for a large etching that extends over three layers, so that the shape of the resist is maintained during the etching operation and has an accurate profile. An element can be formed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明で使用可能なプロジェクター用ライトバ
ルブの画素断面図。
FIG. 1 is a pixel sectional view of a light valve for a projector that can be used in the present invention.

【図2】本発明の代表的な半導体薄膜装置を例示する断
面図。
FIG. 2 is a cross-sectional view illustrating a typical semiconductor thin film device of the present invention.

【図3】図2の半導体薄膜装置を製造するプロセスの第
1段階を示す断面図。
FIG. 3 is a sectional view showing a first stage of a process for manufacturing the semiconductor thin film device of FIG. 2;

【図4】同じく第2段階を示す断面図。FIG. 4 is a sectional view showing a second stage in the same manner.

【図5】同じく第3段階を示す断面図。FIG. 5 is a sectional view showing a third stage.

【図6】同じく第4段階を示す断面図。FIG. 6 is a sectional view showing a fourth stage.

【図7】同じく第5段階を示す断面図。FIG. 7 is a sectional view showing a fifth stage.

【図8】本発明の代表的な半導体薄膜装置の他の例を示
す断面図。
FIG. 8 is a sectional view showing another example of a typical semiconductor thin film device of the present invention.

【図9】下地パターンと層間接続スルーホールの一関係
を示す平面図。
FIG. 9 is a plan view showing a relationship between a base pattern and an interlayer connection through hole.

【図10】従来のプロジェクター用ライトバルブを例示
する画素断面図。
FIG. 10 is a pixel sectional view illustrating a conventional light valve for a projector.

【図11】従来の半導体薄膜装置の第1の欠点を示す断
面図。
FIG. 11 is a sectional view showing a first defect of a conventional semiconductor thin film device.

【図12】従来の半導体薄膜装置の第2の欠点を示す断
面図。
FIG. 12 is a sectional view showing a second disadvantage of the conventional semiconductor thin film device.

【図13】従来の半導体薄膜装置の第3の欠点を示す断
面図。
FIG. 13 is a sectional view showing a third disadvantage of the conventional semiconductor thin film device.

【図14】従来の半導体薄膜装置の第4の欠点を示す断
面図。
FIG. 14 is a sectional view showing a fourth disadvantage of the conventional semiconductor thin film device.

【図15】従来の半導体薄膜装置の第5の欠点を示す断
面図。
FIG. 15 is a sectional view showing a fifth disadvantage of the conventional semiconductor thin film device.

【符号の説明】[Explanation of symbols]

1 1層配線 2 1−2層間絶縁膜 3 1−2層間スルーホール 4 2層配線 5 バリアメタル層 6 2−3層間絶縁膜7 2−3層間スルーホール 8 透明導体膜 DESCRIPTION OF SYMBOLS 1 1-layer wiring 2 1-2 interlayer insulating film 3 1-2 interlayer through hole 4 2-layer wiring 5 barrier metal layer 6 2-3 interlayer insulating film 7 2-3 interlayer through hole 8 transparent conductor film

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 1層配線と、1層配線表面に被覆された
一部にスルーホールが形成された1−2層間絶縁膜と、
該1−2層間絶縁膜表面と前記スルーホール内側側壁と
該スルーホール底面に露出した前記1層配線表面を被覆
し表面側に開口部を有する2層配線と、前記開口部の内
側側壁の2層配線上に形成されたバリアメタル層と、少
なくとも前記開口部底面の2層配線と前記バリアメタル
層に接触しかつ前記開口部及び2−3層間絶縁膜を被覆
している透明導体膜を含んでなることを特徴とする半導
体薄膜装置。
A single-layer wiring and a surface of the single-layer wiring are covered.
A 1-2 interlayer insulating film in which a through hole is partially formed,
The surface of the 1-2 interlayer insulating film and the inner side wall of the through hole;
Covering the surface of the one-layer wiring exposed on the bottom surface of the through hole
A two-layer wiring having an opening on the surface side;
A barrier metal layer formed on the two-layer wiring on the side wall;
At least the two-layer wiring at the bottom of the opening and the barrier metal
A semiconductor thin film device comprising a transparent conductor film in contact with a layer and covering the opening and the 2-3 interlayer insulating film.
【請求項2】 2層配線の材質がAl、バリアメタル層
の材質がTi、透明導体膜の材質がITOである、請求
項1に記載の半導体薄膜装置。
2. The semiconductor thin film device according to claim 1, wherein the material of the two-layer wiring is Al, the material of the barrier metal layer is Ti, and the material of the transparent conductor film is ITO.
【請求項3】 1層配線上に1−2層間絶縁膜を被覆
し、該1−2層間絶縁膜に1−2層間スルーホールを形
成し、該1−2層間絶縁膜表面及び前記スルーホール内
壁表面に2層配線を被覆し続いて該2層配線表面にバリ
アメタル層を被覆し、該バリアメタル層表面に2−3層
間絶縁膜を被覆し、該2−3層間絶縁膜及びバリアメタ
ル層を、1−2層間絶縁膜の前記1−2層間スルーホー
ルに対応する開口側壁に形成されている少なくとも下部
のバリアメタル層が残るようにエッチングし、前記2層
配線、バリアメタル層及び2−3層間絶縁膜を被覆する
ように透明導体膜を形成することを特徴とする半導体薄
膜装置の製造方法。
3. A 1-2 interlayer insulating film is coated on the one-layer wiring, a 1-2 interlayer through hole is formed in the 1-2 interlayer insulating film, and the 1-2 interlayer insulating film surface and the through hole are formed. The surface of the inner wall is covered with a two-layer wiring, then the surface of the two-layer wiring is coated with a barrier metal layer, and the surface of the barrier metal layer is coated with a 2-3 interlayer insulating film. The layer is etched such that at least the lower barrier metal layer formed on the side wall of the opening corresponding to the 1-2 interlayer through hole of the 1-2 interlayer insulating film remains, and the two-layer wiring, the barrier metal layer, and the (3) A method for manufacturing a semiconductor thin film device, comprising forming a transparent conductor film so as to cover an interlayer insulating film.
JP35086198A 1998-12-10 1998-12-10 Semiconductor thin film device and method of manufacturing the same Expired - Lifetime JP3216124B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP35086198A JP3216124B2 (en) 1998-12-10 1998-12-10 Semiconductor thin film device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP35086198A JP3216124B2 (en) 1998-12-10 1998-12-10 Semiconductor thin film device and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JP2000174128A JP2000174128A (en) 2000-06-23
JP3216124B2 true JP3216124B2 (en) 2001-10-09

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Country Status (1)

Country Link
JP (1) JP3216124B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9164341B2 (en) 2011-11-18 2015-10-20 Sharp Kabushiki Kaisha Active matrix substrate, liquid crystal display device and method for manufacturing active matrix substrate
US8912547B2 (en) * 2012-01-20 2014-12-16 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device, display device, and semiconductor device
CN104380189B (en) * 2012-06-25 2017-03-29 夏普株式会社 The manufacture method of active-matrix substrate, liquid crystal indicator and active-matrix substrate
JP6336765B2 (en) 2014-01-31 2018-06-06 株式会社ジャパンディスプレイ Display device

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