JPH0817914A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To surely cover a second wiring layer, by forming a first insulating film on a first wiring layer formed on a semiconductor substrate, forming a connection hole reaching the first wiring layer, in the first insulating film, depositing a second insulating film in the hole, exposing the first wiring layer by etching, and connecting the first wiring layer with the second wiring layer. CONSTITUTION:An SiO2 film 2 is deposited on a semiconductor substrate 1. After the whole surface of the SiO2 film 2 is vapor-deposited, a first wiring layer 3 is formed on the SiO2 film 2. A first insulating film 4, as an interlayer insulating film, is formed on the surface of the first wiring layer 3. A connection hole 6 reaching the first wiring layer 3 is formed in the first insulating film 4. A second insulating film 7 is deposited in the connection hole 6. The first wiring layer 3 is exposed in the connection hole 6 by etching the second insulating film 7. The first wiring layer 3 is connected with the second wiring layer 8 through the connection hole 6. Thereby the second wiring layer 8 can be surely covered, when misalignment is generated between the first wiring layer 3 and the connection hole 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a multilayer wiring structure, and more particularly to a method for manufacturing a semiconductor device in consideration of misalignment of wiring interlayer connection holes.

[0002]

2. Description of the Related Art A multilayer wiring structure in which wirings in an integrated circuit are multi-layered is an important wiring technology for providing a high degree of freedom in coupling elements and forming a high density device.

5A and 5B are views showing the structure of a conventional semiconductor device having a multi-layer wiring structure. FIG. 5A is a plan view thereof, and FIG. 5B is a view thereof. a) A-A
It is a cross-sectional view.

As shown in FIG. 5B, the semiconductor substrate 10
The insulating layer 102 is formed on the upper surface of the insulating layer 10.
The first wiring layer 103 is formed on the surface of No. 2. Further, the first wiring layer 103 is formed via the interlayer insulating film 104.
The second wiring layer 105 is formed so as to be orthogonal to
And the second wiring layers 103 and 105 are wiring interlayer connection holes 106.
Connected through.

In the semiconductor device having such a structure,
When forming the connection hole 106 for connecting the first and second wiring layers 103 and 105, the first wiring layer below the connection hole 106 is formed so that the connection hole 106 does not come off from the first wiring layer 103. 103 is provided with a margin width (length, width) r1 in consideration of misalignment with the connection hole 106.

[0006]

However, in the above-described conventional semiconductor device, there is a problem that the above margin width r1 hinders the miniaturization of the multilayer wiring as the miniaturization of the element progresses.

Therefore, in order to cope with the miniaturization of the multilayer wiring, it is conceivable to form the first wiring layer 103a in a shape with the margin width r1 removed as shown in FIG. 6 (a). In this case, the adjacent first wiring layer 103a
The wiring pitch P1 between them is obviously reduced as compared with the wiring pitch P2 (FIG. 6B) when the margin width r1 is provided, and the multilayer wiring can be miniaturized.

However, when the connection hole 106 is removed from the first wiring layer 103a (FIG. 7 (a)), as shown in FIG. 7 (b), one side wall surface of the first wiring layer 103a is removed. The deep groove 106a that is etched along or below the insulating film 102 has a width corresponding to the shift amount Z1.
It is formed at the bottom of 06. The groove 106a causes deterioration of the covering property of the second wiring layer 105 deposited thereafter, which causes disconnection of the second wiring layer 105 and deterioration of reliability, and also causes the groove 106a to be formed on the second wiring layer 105. This causes a problem that the coverage of the deposited film also deteriorates.

Further, even when the width of the connection hole 106 is larger than the width of the first wiring layer 103a (see FIG. 8).
(A)), as shown in FIG. 8 (b), the first wiring layer 10
Deep grooves 106a and 106b etched along both side wall surfaces of 3a to the insulating film 102 thereunder are formed at the bottom of the connection hole 106 with a width corresponding to the protruding amount Z2, and the same problem as described above occurs. .

The present invention has been made to solve the above-mentioned conventional problems, and an object thereof is to connect a first wiring layer and a second wiring layer above the first wiring layer through a connection hole. In the multilayer wiring structure, even if misalignment occurs between the first wiring layer and the wiring interlayer connection hole, the second wiring layer can be satisfactorily covered and the reliability of the multilayer wiring is improved. Another object of the present invention is to provide a method of manufacturing a semiconductor device. Another object of the present invention is to provide a method for manufacturing a semiconductor device capable of promoting miniaturization of multilayer wiring while ensuring reliability of the multilayer wiring.

[0011]

To achieve the above object, the present invention is characterized in that a step of forming a first insulating film on the surface of a first wiring layer provided on a semiconductor substrate, Forming a connection hole reaching the first wiring layer in the first insulating film; depositing a second insulating film in the connection hole; etching the second insulating film to etch the second insulating film; There is a step of exposing the first wiring layer in the connection hole, and a step of forming a second wiring layer connected to the first wiring layer through the connection hole.

In the above invention, it is preferable that the film thickness of the second insulating film is set to half the maximum value of the misalignment amount between the first wiring layer and the connection hole.

[0013]

According to the above structure, the first insulating film is formed on the surface of the first wiring layer provided on the semiconductor substrate,
Further, a connection hole reaching the first wiring layer is formed in the first insulating film. At this time, when the connection hole is separated from the first wiring layer, a deep groove etched along the side wall surface of the first wiring layer or to the underlying layer is formed. By depositing the second insulating film, the deep groove is filled with the second insulating film.

Further, by etching the second insulating film to expose the first wiring layer in the connection hole, the connection hole is formed with the deep groove filled with the second insulating film. It is formed.

As a result, even if a second wiring layer connected to the first wiring layer through the connection hole is formed thereafter, the deep groove does not exist, and therefore, the second groove in the connection hole is formed.
The wiring layer has good coverage.

Further, the film thickness of the second insulating film is set to half the maximum value of the misalignment amount between the first wiring layer and the connection hole, whereby the first wiring layer and the connection hole are formed. Even when the deep groove is generated due to misalignment with
The deep groove can be accurately filled with the second insulating film regardless of the misalignment amount, and the coverage of the second wiring layer in the connection hole can be kept good.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. 1 (a) to 1 (c) and 2 (d) to (f),
FIG. 3A is a process diagram showing the manufacturing method of the semiconductor device according to the first embodiment of the present invention.

First, as shown in FIG. 1A, a SiO 2 film (silicon oxide film) 2 as an interlayer insulating film is deposited on the upper surface of a semiconductor substrate 1 by a CVD method to a thickness of, for example, 10000Å, and subsequently, After vacuum-depositing aluminum (Al) on the entire surface of the CVD-SiO2 film 2, desired patterning is performed to form a first wiring layer 3 having a width of 1 .mu.m. Furthermore, a CVD-SiO2 film is added to 20000Å
After being deposited to a thickness of 1, an interlayer insulating film (first insulating film) 4 is formed by performing a flattening process. At this time, the thickness of the interlayer insulating film 4 on the first wiring layer 3 was 10000Å.

Next, as shown in FIG. 1B, the first
Since the wiring interlayer connection hole (for example, 1 μm square) 6 for connecting the wiring layer 3 and the second wiring layer 8 to be formed later is opened, the register pattern 5 is formed on the upper surface of the interlayer insulating film 4. . At this time, the pattern misalignment amount Z1 between the first wiring layer 3 and the resist pattern 5 is 0. 3 μm
0.2 μm was generated with respect to the standard.

Thereafter, as shown in FIG. 1C, the interlayer insulating film 4 is etched by a reactive ion etching method using the resist pattern 5 as a mask.
A connection hole 6 is formed to connect the wiring layer 3 and the second wiring layer 8 to be formed later. The etching amount at this time is, for example, 1.5 times the film thickness of the interlayer insulating film 4 on the first wiring layer 3. Therefore, 0.2 out of the first wiring layer 3
A deep groove 6a having a width of μm (pattern alignment shift amount Z1) and a depth of 1.5 μm was formed along one side wall surface of the first wiring layer 3.

Further, after the resist pattern 5 is peeled off, as shown in FIG. 2 (d), half the pattern alignment deviation standard (0.30 μm) between the first wiring layer 3 and the connection hole 6 (0.30 μm) (0. CVD with film thickness L of 15 μm = 1500Å)
A -SiO2 film (second insulating film) 7 is deposited. As a result, the groove 6a is filled with the CVD-SiO2 film 7.

To fill the groove 6a, at least half of the width Z1 of the CVD-SiO2 film is formed.
The film 7 may be deposited. However, since the width of the groove 6a varies depending on the misalignment amount Z1 between the first wiring layer 3 and the contact hole 6, the thickness of the CVD-SiO2 film 7 for filling the groove 6a in the present embodiment. L is the maximum value of the pattern misalignment amount, that is, half of the misalignment standard.

Next, as shown in FIG. 2 (e), the groove 6 is formed.
Reactive ion etching is used so as to remove the CVD-SiO2 film 7 deposited in the contact hole 6 on the upper surface of the first wiring layer 3 while maintaining the shape of the CVD-SiO2 film 7 in which a is embedded. Then, the CVD-SiO2 film 7 is etched to expose the first wiring layer 3 in the connection hole 6.

The etching amount at this time is set to the above-mentioned CVD-S.
Although the film thickness of the iO2 film 7 is set to 1.5 times, the CVD-SiO2 film 7a filling the groove 6a only needs to be lower than the exposed surface of the first wiring layer 3 by 0.075 μm (750Å). Therefore, the second wiring layer 8 after the connection hole 6 is formed.
Has good coverage.

Then, as shown in FIG. 2 (f), aluminum (Al) is vacuum-deposited to a thickness of 10,000 Å and desired patterning is applied to form the second wiring layer 8. The wiring layer 3 and the second wiring layer 8 connect to the connection hole 6
A semiconductor device connected by is obtained.

As described above, according to this embodiment, the deep groove 6a generated when the connection hole 6 is removed from the first wiring layer 3 is C
Since it is filled with the VD-SiO2 film 7, the coverage of the second wiring layer 8 in the connection hole 6 can be improved.

FIGS. 3A and 3B are process drawings showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention.
Elements common to those in FIGS. 1 and 2 are designated by the same reference numerals.

In this embodiment, in the step shown in FIG. 1C, when the interlayer insulating film 4 is etched by using the resist pattern 5 as a mask to form the connection hole 6, the etching amount is set to the film of the interlayer insulating film 4. Since the thickness is 1.5 times or more, the deep groove 6b reaching the inside of the interlayer insulating film 2 which is the base layer of the first wiring layer 3 is generated.

Even in the case where the deep trench 6b reaching the interlayer insulating film 2 is formed in this way, the CVD-process as shown in FIG. 3B is performed by the manufacturing method similar to that of the first embodiment.
Since the deep groove 6b is filled with the SiO2 film 7, the coverage of the second wiring layer 8 on the connection hole 6 can be improved.

FIGS. 4A and 4B are process drawings showing a method of manufacturing a semiconductor device according to the third embodiment of the present invention.
Elements common to those in FIGS. 1 and 2 are designated by the same reference numerals.

This embodiment describes a case where the width of the connection hole 6 is larger than the width of the first wiring layer 3.
In such a case, as shown in FIG. 4A, deep trenches 6 etched along both side wall surfaces of the first wiring layer 3 are formed.
a and 6c occur in a width corresponding to the protrusion amount Z2.

Even if such deep grooves 6a and 6c are formed, the same manufacturing method as in the first embodiment is used.
Since the deep trenches 6a and 6c can be filled with the CVD-SiO2 film 7 as shown in FIG. 4 (b), the covering property of the second wiring layer 8 in the connection hole 6 can be similarly improved.

[0033]

As described above in detail, according to the present invention, the first insulating film is formed on the surface of the first wiring layer provided on the semiconductor substrate, and the first wiring layer is formed. A reaching contact hole is formed in the first insulating film, a second insulating film is deposited in the connecting hole, and the second insulating film is etched to expose the first wiring layer in the connecting hole. Since the second wiring layer connected to the first wiring layer is formed through the connection hole, when a misalignment occurs between the first wiring layer and the connection hole in the multilayer wiring structure. Even in this case, the coverage of the second wiring layer in the connection hole can be kept good. As a result, it is not necessary to provide the first wiring layer with a margin, and it is possible to promote the miniaturization of the multilayer wiring while ensuring the reliability of the multilayer wiring.

Further, in the above invention, the film thickness of the second insulating film is set to half the maximum value of the misalignment amount between the first wiring layer and the connection hole, so that the misalignment amount becomes Regardless of this, the coverage of the second wiring layer in the connection hole can be kept good.

[Brief description of drawings]

FIG. 1 is a process diagram (1) showing a method for manufacturing a semiconductor device according to a first embodiment.

FIG. 2 is a process drawing (2) showing the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 3 is a process drawing showing the manufacturing method of the semiconductor device according to the second example.

FIG. 4 is a process drawing showing the manufacturing method of the semiconductor device according to the third example.

FIG. 5 is a diagram showing a structure of a conventional semiconductor device having a multilayer wiring structure.

FIG. 6 is a diagram showing a shape of a conventional first wiring layer.

FIG. 7 is an explanatory diagram for explaining a conventional problem.

FIG. 8 is an explanatory diagram for explaining a conventional problem.

[Explanation of symbols]

 1 semiconductor substrate 2 CVD-SiO2 film 3 first wiring layer 4 interlayer insulating film (first insulating film) 5 register pattern 6 connection hole 6a, 6b, 6c groove 7 CVD-SiO2 film (second insulating film) 8 Second wiring layer

Claims (2)

[Claims] 1. A step of forming a first insulating film on a surface of a first wiring layer provided on a semiconductor substrate, and a connection hole reaching the first wiring layer in the first insulating film. A step of forming, a step of depositing a second insulating film in the connection hole, a step of etching the second insulating film to expose the first wiring layer in the connection hole, the connection hole A second wiring connected to the first wiring layer through
And a step of forming a wiring layer, the method for manufacturing a semiconductor device. 2. The semiconductor according to claim 1, wherein the film thickness of the second insulating film is set to half the maximum value of the misalignment amount between the first wiring layer and the connection hole. Device manufacturing method.