JP4492982B2 - Manufacturing method of semiconductor device having multilayer wiring - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a multilayer wiring structure and a manufacturing method thereof.
[0002]
[Prior art]
Since the semiconductor process technology that has been remarkably advanced in recent years has made it possible to miniaturize and highly integrate wiring and elements, the performance of ULSI has been improved. However, with the integration of wiring, signal delays in the wiring control the speed of the device. Therefore, in ULSIs of the so-called 0.25 μm generation and beyond, conventional SiO2 is used as a material for the interlayer insulating film. ₂ Instead of (relative permittivity ε = 4.3), a material having a low relative permittivity, for example, SiOF doped with fluorine having a low relative permittivity (ε = 3.5) or SiO: C containing organic matter (ε = 2) .8 to 3.2) are going to be used. However, since these materials have problems in terms of moisture absorption and heat resistance, it is difficult to construct a process using the materials.
[0003]
In addition, in order to reduce the delay between the wirings, which is a particularly large delay, a hole formed by air (ε = 1.0) is intentionally provided in the insulating material between the wirings. A technique for lowering the relative dielectric constant in the above has been proposed (Japanese Patent Laid-Open No. 62-5543). Hereinafter, this technique will be described with reference to FIG. FIG. 20 is a cross-sectional view showing the structure of a conventional semiconductor device. In FIG. 20, in the insulating substance 2 provided on the semiconductor substrate 1 included in the semiconductor device, a hole 6 is provided between the wirings 3 and 4, and a hole 7 is provided between the wirings 4 and 5, respectively. The material of the insulating substance 2 is SiO. ₂ Is used. The capacity between the wiring 3 and the wiring 4 is equal to the capacity in which the capacity between the wiring 3 and the hole 6, the capacity of the hole 6 itself, and the capacity between the hole 6 and the wiring 4 are connected in series. Can be considered. Insulating substance 2 material SiO that is a part other than holes ₂ In comparison with the relative dielectric constant, the relative dielectric constant of the air holes formed by air is about 1/4. Therefore, the capacitance between adjacent wirings can be reduced by providing the holes. As a result, signal delay between adjacent wirings can be suppressed, so that a semiconductor device with a wide operation margin and hardly malfunctioning can be realized, and a new material does not need to be used, which can be a low-cost process.
[0004]
[Problems to be solved by the invention]
However, according to the above-described conventional configuration, the wiring and the interlayer connection hole are borderless, that is, the wiring width and the diameter of the interlayer connection hole are designed to have the same dimension, and misalignment occurs in the photolithography process. In such a case, the following problems occur. First, since the interlayer connection hole and the hole are integrated when the interlayer connection hole is opened, a short circuit of the wiring occurs when the interlayer connection metal enters the integrated region. Second, since the connection area between the interlayer connection metal and the wiring in the interlayer connection hole is small, a connection failure occurs.
[0005]
These defects will be described with reference to FIG. 21 and FIG. FIG. 21A, FIG. 21B, and FIG. 22A to FIG. 22C are process flow diagrams showing a conventional method for manufacturing a multilayer wiring included in a semiconductor device. First, as shown in FIG. 21A, an insulating film 12, a first wiring 13, and an interlayer insulating film 14 are sequentially formed on the semiconductor substrate 11. SiO deposited by plasma CVD as the interlayer insulating film 14 ₂ So step coverage is bad. That is, the ratio of the deposited film thickness in the wiring gap 15 that is the region between the first wirings 13 to the deposited film thickness in the flat portion is low. As a result, holes 16 are formed in the interlayer insulating film 14 in the wiring gap 15. However, since the step coverage does not become 0%, the entire wiring gap 15 is not a hole, and the interlayer insulating film 14 exists between the wirings. Therefore, for the purpose of reducing the relative dielectric constant between the wirings, a method of lowering the relative dielectric constant by further reducing the deposition rate of the interlayer insulating film 14 in the wiring gap 15 can be considered. In this case, the holes 16 occupy a larger area. Next, as shown in FIG. 21B, a part of the interlayer insulating film 14 is removed by using a resist etch back method, a chemical mechanical polishing (CMP) method, or the like, so that the interlayer insulating film 14 is formed. Flatten.
[0006]
Next, as shown in FIG. 22A, interlayer connection holes 17 are formed using photolithography and dry etching. Here, a case is considered in which the wiring width 18 of the first wiring and the diameter 19 of the interlayer connection hole have the same dimension and an alignment shift of only the shift dimension 20 occurs in photolithography. In this case, the portion of the interlayer connection hole 17 that is displaced from the upper surface of the first wiring 13 due to the misalignment is formed deeper than the position of the upper surface. Therefore, the interlayer connection hole 17 is integrated with the hole 16. Next, as shown in FIG. 22B, an interlayer connection metal 21 made of tungsten is formed in the interlayer connection hole 17 by CVD. Since the tungsten 21 formed by the CVD method has good step coverage, not only the interlayer connection hole 17 in FIG. As a result, a short-circuit defect occurs in which the adjacent first wirings 13 are connected to each other through the interlayer connection metal 21 formed in the portion that is the hole 16. If the relative dielectric constant in the wiring gap 15 is to be lowered, the holes 16 occupy a larger area, so that short-circuit defects are more likely to occur. On the other hand, when the displacement dimension 20 in FIG. 22A is further increased, the connection area between the first wiring 13 and the interlayer connection metal 21 embedded in the interlayer connection hole 17 is reduced. Connection failure between the wiring 13 and the interlayer connecting metal 21 occurs. In particular, when an organic material is used as the material of the interlayer insulating film 14, the connection failure is likely to occur. Further, when the interlayer connection hole 17 is etched deeper, a short circuit defect occurs in which the first wiring 13 and the semiconductor substrate 11 are connected by the formed interlayer connection metal 21. Next, as shown in FIG. 22C, the second wiring 22 to be connected to the first wiring 13 through the interlayer connection metal 21 is connected to the interlayer connection metal 21 and the interlayer insulating film 14. And form on top.
[0007]
SUMMARY OF THE INVENTION The present invention has been made in view of the above-described conventional problems, and an object thereof is to provide a semiconductor device that minimizes inter-wiring capacitance and is less likely to cause short-circuit failure or connection failure even when misalignment occurs, and a method for manufacturing the same. And
[0008]
[Means for Solving the Problems]
A method of manufacturing a semiconductor device according to the present invention is a lower wiring layer composed of a plurality of wirings formed on the same insulating film, wherein the plurality of wirings are first wiring and first wiring to first wiring. A lower wiring layer including a second wiring adjacent to each other with a gap, and a third wiring adjacent to the second wiring that is wider than the first gap from the first wiring; the first wiring; Forming a structure including two wirings and a first interlayer insulating film formed on the third wiring, substantially closing the upper portion of the first gap, and within the first gap A step of depositing a first interlayer insulating layer constituting a lower portion of the second interlayer insulating film so as to form a void; and a step of forming the upper portion of the second interlayer insulating film from the first interlayer insulating layer The second gap is buried by depositing a second interlayer insulating layer with good coverage And comprising a step of completely covering the holes.
[0009]
It is preferable that the method further includes a step of planarizing the second interlayer insulating film so as not to expose the holes.
[0010]
The second interlayer insulating layer is preferably formed from an organic film having a lower dielectric constant than the first interlayer insulating layer.
[0011]
A semiconductor device according to the present invention is a lower wiring layer composed of a plurality of wirings formed on the same insulating film, wherein the plurality of wirings pass through a first gap and a first gap from the first wiring. A lower wiring layer including a second wiring adjacent to the first wiring and a third wiring adjacent to the first wiring with a second gap, and on the first wiring, the second wiring, and the third wiring. The formed first interlayer insulating film, the connecting metal formed in the first interlayer insulating film and in contact with the upper surface of the first wiring, and above the first gap and the second gap A second interlayer insulating film formed in each of the first gap and the second gap, and formed on the second interlayer insulating film, and electrically connected to the interlayer connecting metal. And an upper wiring layer connected to each other.
[0012]
The upper wiring layer may be a wiring having a buried structure, and the upper wiring layer may be formed in the second interlayer insulating film.
[0013]
The base insulating film of the lower wiring layer has a groove formed below the first gap and the second gap, and the groove is above the upper surface of the base insulating film. A part of the second interlayer insulating film having a height that does not protrude may be present.
[0014]
It is preferable that the upper end portion of the interlayer connecting metal protrudes above the upper surface of the first interlayer insulating film.
[0015]
The first wiring has a side surface portion locally projecting toward the second wiring and / or the third wiring, and the upper surface of the side surface portion is covered with the metal for interlayer connection. Also good. Moreover, it is preferable that the said side part of the said 1st wiring is formed in the self-alignment with respect to the said metal for interlayer connection.
[0016]
Another semiconductor device according to the present invention is a lower wiring layer composed of a plurality of wirings formed on the same insulating film, wherein the plurality of wirings are a first wiring and a first gap from the first wiring. A lower wiring layer including a second wiring adjacent to the first wiring and a third wiring adjacent to the first wiring with a second gap, and the first wiring, the second wiring, and the third wiring. A first interlayer insulating film formed thereon; and a second interlayer insulating film covering the lower wiring layer and having a flat upper surface, wherein the second gap is wider than the first gap. The second interlayer insulating film includes a first interlayer insulating layer and a second interlayer insulating layer formed on the first interlayer insulating layer, and an upper surface of the second interlayer insulating film is planarized, The first interlayer insulating layer and the second interlayer insulating layer block the upper portion of the first gap, and are within the first gap. Holes are formed, said second gap is filled by the first interlayer insulating layer and the second interlayer insulating layer.
[0017]
The second interlayer insulating layer preferably has better coverage than the first interlayer insulating layer.
[0018]
The first interlayer insulating layer is formed of a silicon oxide film, and the second interlayer insulating layer is formed of an organic coating film having a dielectric constant lower than that of the first interlayer insulating layer. preferable.
[0019]
A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having multilayer wiring, in which a first interlayer insulating film is formed on a first wiring layer, and the formed first interlayer insulating film is formed. Forming an interlayer connection hole in the film and embedding an interlayer connection metal in the opened interlayer connection hole; and using the first wiring pattern as a mask, the first interlayer insulating film and the first wiring layer; Sequentially forming the first wiring, forming a second interlayer insulating film on the semiconductor substrate on which the first interlayer insulating film and the first wiring are formed, and By removing the second interlayer insulating film until the surface of the first interlayer insulating film is exposed, each of the second interlayer insulating film, the first interlayer insulating film, and the interlayer connecting metal has A step of flattening the surface to be in the same plane; and the same plane. A second metal layer is formed on, and a step of forming a second wiring by etching the second metal layer to the second wiring pattern as a mask.
[0020]
Another method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a multi-layer wiring, in which a first interlayer insulating film is formed on a first wiring layer, and the formed first A step of opening an interlayer connection hole in the interlayer insulating film, embedding an interlayer connection metal in the opened interlayer connection hole, and the first interlayer insulating film and the first wiring using the first wiring pattern as a mask; Forming a first wiring by sequentially etching the layers, and forming a second interlayer insulating film on the semiconductor substrate on which the first interlayer insulating film and the first wiring are formed. And removing the second interlayer insulating film until the surface of the first interlayer insulating film is exposed, so that the second interlayer insulating film, the first interlayer insulating film, and the interlayer connecting metal are The process of flattening each surface to be in the same plane and for groove preparation Etching at least the first interlayer insulating film with a turn as a mask to form a groove having a predetermined depth from the surface of the first interlayer insulating film, the interlayer connecting metal and the first Forming a second metal layer on the interlayer insulating film and the second interlayer insulating film, and removing a portion of the second metal layer other than the inside of the groove to remove the second wiring Forming a step.
[0021]
Still another method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a multilayer wiring, and a first interlayer insulating film is formed on a first wiring layer formed on the insulating film. Then, an interlayer connection hole is opened in the formed first interlayer insulating film, an interlayer connection metal is embedded in the opened interlayer connection hole, and the first wiring resist pattern is used for masking. A step of forming a first wiring by sequentially etching the first interlayer insulating film, the first wiring layer, and at least a part of the insulating film; and on the semiconductor substrate on which the first wiring is formed. Forming a second interlayer insulating film on the substrate, and removing the second interlayer insulating film until the surface of the interlayer connecting metal is exposed, thereby forming the second interlayer insulating film and the interlayer connecting metal, Flat so that the surface of each has the same plane Forming a second metal layer on the same plane and etching the second metal layer by using the second wiring resist pattern for masking to form a second wiring. Process.
[0022]
Still another method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a multilayer wiring, and a first interlayer insulating film is formed on a first wiring layer formed on the insulating film. A step of opening an interlayer connection hole in the formed first interlayer insulating film, and embedding an interlayer connection metal in the opened interlayer connection hole; and a part from the surface of the first interlayer insulating film; Etching, using the first wiring resist pattern for masking, sequentially etching the first interlayer insulating film and the first wiring layer, thereby forming a first wiring; Forming a second interlayer insulating film on the semiconductor substrate on which the first wiring is formed, and removing the second interlayer insulating film until the surface of the interlayer connecting metal is exposed. Each of the interlayer insulating film and the interlayer connecting metal has Flattening the surfaces to be in the same plane, forming a second metal layer on the same plane, and etching the second metal layer using the second wiring resist pattern for masking Thereby forming a second wiring.
[0023]
Still another method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a multilayer wiring, and a first interlayer insulating film is formed on a first wiring layer formed on the insulating film. Then, an interlayer connection hole is opened in the formed first interlayer insulating film, an interlayer connection metal is embedded in the opened interlayer connection hole, and the first wiring resist pattern is used for masking. A step of forming a first wiring by sequentially etching the first interlayer insulating film, the first wiring layer, and the insulating film; and a second step on the semiconductor substrate on which the first wiring is formed. Forming an interlayer insulating film; and removing the second interlayer insulating film until a surface of the first interlayer insulating film is exposed, thereby forming the second interlayer insulating film and the first interlayer insulating film. To flatten the surface of each And a step of selectively etching the surface of the second interlayer insulating film and then depositing a third interlayer insulating film; and the third interlayer insulating until the surface of the first interlayer insulating film is exposed. Removing the film to planarize the surfaces of the third interlayer insulating film, the first interlayer insulating film, and the interlayer connection metal so as to be on the same plane; Forming a second wiring by forming a second metal layer and etching the second metal layer using the second wiring resist pattern for masking.
[0024]
It is preferable that a hole formed of a closed region where the second interlayer insulating film does not exist is further provided in a wiring gap between the first wirings.
[0025]
It is preferable that the dielectric constant of the second interlayer insulating film is smaller than the dielectric constant of the first interlayer insulating film.
[0026]
Prior to the step of forming the first wiring, a step of etching a part from the surface of the first interlayer insulating film may be further provided.
[0027]
As a method for forming the second interlayer insulating film, high-density plasma CVD may be used.
[0028]
As a method of forming the second interlayer insulating film, high density plasma CVD in which a bias voltage is applied to the substrate may be used.
[0029]
The dielectric constant of the material used for the second interlayer insulating film is preferably smaller than the dielectric constant of the material used for the first interlayer insulating film.
[0030]
In the step of planarizing the second interlayer insulating film, it is preferable to use chemical mechanical polishing.
[0031]
The step of forming the second interlayer insulating film includes the step of forming a first interlayer insulating layer that constitutes a part of the second interlayer insulating film, and the other part of the second interlayer insulating film. You may include the process of forming the 2nd interlayer insulation layer to comprise on the said 1st interlayer insulation layer.
[0032]
In the step of forming the first interlayer insulating layer, the gap is formed by the first interlayer insulating layer so as to form a void in a gap of 0.5 μm or less among the gaps formed by the first wiring layer. In the step of substantially covering the gap of 0.5 μm or less and forming the second interlayer insulating layer, the first interlayer insulating layer substantially covers the gap formed by the first wiring layer. A part of the second interlayer insulating layer may enter the gap that is not covered.
[0033]
As the first interlayer insulating layer, silane / N ₂ A first plasma CVD film formed using O-based gas plasma may be used.
[0034]
As the second interlayer insulating layer, a second plasma CVD film formed using high density plasma to which a substrate bias voltage is applied may be used.
[0035]
In the step of planarizing the second interlayer insulating film, the second interlayer insulating layer may be removed without removing the first interlayer insulating layer.
[0036]
In the step of forming the second interlayer insulating film, the height of the upper end of the hole measured from the upper surface of the first wiring is preferably 500 nm or less.
[0037]
In the step of forming the second interlayer insulating film, it is preferable that voids are formed in a gap of 0.8 μm or less among the gaps formed by the first wiring layer.
[0038]
In the step of forming the second interlayer insulating film, a hole having a porosity of 0.5 or more is formed in a gap having an interval of 0.5 μm or less among the gaps formed by the first wiring layer. preferable.
[0039]
In the step of planarizing the second interlayer insulating film, the second interlayer insulating layer may be removed without removing the first interlayer insulating layer.
[0040]
The semiconductor device according to the present invention is a semiconductor device having a multilayer wiring, and the first wiring formed on the semiconductor substrate is connected to the first wiring and another layer wiring. The interlayer connection metal formed on the wiring, the first interlayer insulating film formed in all regions of the first wiring other than the portion where the interlayer connection metal exists, and the semiconductor substrate When viewed, the second interlayer insulating film formed in all regions other than the first wiring and at least the interlayer connecting metal, and the interlayer connecting metal through the interlayer connecting metal And a second wiring connected to the first wiring.
[0041]
Another semiconductor device according to the present invention is a semiconductor device having a multilayer wiring, and is formed on each of a plurality of first wiring layers arranged on an insulating film and the plurality of first wiring layers. A first interlayer insulating film, an opening in the first interlayer insulating film, an interlayer connection hole located on the plurality of first wiring layers, and embedded in the interlayer connection hole; An interlayer connection metal in contact with the wiring layer, a second interlayer insulating film formed to cover the plurality of first wiring layers, and the insulating film between the plurality of first wiring layers. And a recess formed on the surface.
[0042]
Still another semiconductor device according to the present invention is a semiconductor device having a multilayer wiring formed on a plurality of first wiring layers arranged on an insulating film and each of the plurality of first wiring layers. A first interlayer insulating film formed, an interlayer connection hole that is opened in the first interlayer insulating film, is located on the plurality of first wiring layers, and is embedded in the interlayer connection hole. And a second interlayer insulating film provided on a region where the first wiring layer is not formed, and the upper surface of the interlayer connecting metal is the first metal layer. It protrudes above the upper surface of the interlayer insulating film.
[0043]
The second interlayer insulating film includes a plurality of first wiring layers, a first interlayer insulating layer that constitutes a part of the second interlayer insulating film, and another one of the second interlayer insulating films. A second interlayer insulating layer constituting a portion, wherein the first interlayer insulating layer forms a hole in a gap of 0.5 μm or less among gaps formed by the first wiring layer. The gap substantially covers the gap of 0.5 μm or less, and a part of the second interlayer insulating layer is substantially covered by the first interlayer insulating layer in the gap formed by the first wiring layer. It is preferable to enter the inside of an uncovered gap.
[0044]
The height of the upper end of the hole measured from the upper surface of the first wiring is preferably 500 nm or less.
[0045]
It is preferable that voids are formed in the gaps of 0.8 μm or less among the gaps formed by the first wiring layer.
[0046]
It is preferable that voids having a porosity of 0.5 or more are formed in gaps having an interval of 0.5 μm or less among the gaps formed by the first wiring layer.
[0047]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
A first embodiment of the present invention will be described with reference to FIGS. FIGS. 1A to 1D and FIGS. 2A to 2C are process flow diagrams showing a method for manufacturing a semiconductor device according to the present embodiment. First, as shown in FIG. 1A, an insulating film 102 (thickness 0.8 μm), a laminated structure of aluminum and a titanium alloy is formed on a semiconductor substrate 101 on which a semiconductor active element (not shown) is formed in advance. A first metal layer 103 (having a thickness of 0.5 μm) and a first interlayer insulating film 104 (having a thickness of 1.0 μm) are sequentially deposited. Thereafter, an interlayer connection resist pattern 105 is formed, and an interlayer connection hole 106 is opened by dry etching.
[0048]
Next, as shown in FIG. 1B, an adhesion layer 107 made of TiN / Ti, for example, is deposited on the surface having the interlayer connection hole 106 after the interlayer connection resist pattern 105 is peeled off, and then the blanket. An interlayer connection material 108 made of tungsten is deposited by W-CVD. The adhesion layer 107 and the interlayer connection material 108 that exist outside the inside of the interlayer connection hole 106 are removed by dry etching or CMP. The adhesion 107 and the interlayer connection material 108 existing only inside the interlayer connection hole 106 together constitute an interlayer connection metal 109.
[0049]
Next, as shown in FIG. 1C, a first wiring resist pattern (masking layer defining the first wiring layer pattern) is formed on the first interlayer insulating film 104 and the interlayer connecting metal 109. 110 is formed. Consider a case where the first wiring resist pattern 110 is formed with a misalignment of 111 by misalignment. For example, if the diameter of the interlayer connection hole 106 is 0.3 μm and the width of the first wiring resist pattern 110 is 0.3 μm, the interlayer connection metal 109 embedded in the interlayer connection hole 106 and the first connection metal 109 The allowable deviation dimension 111 with respect to the wiring resist pattern 110 is 0.1 μm at the maximum.
[0050]
FIG. 3A is a plan view showing the relationship between the displacement of the first wiring resist pattern 110 and the interlayer connection metal 109. The case where the position of the first wiring resist pattern 110 is shifted from the position of the interlayer connection metal 109 is shown on the lower side of the wavy line in FIG. 3A, and the first wiring is shown on the upper side of the wavy line. In this example, the position of the resist pattern 110 for alignment and the position of the interlayer connection metal 109 are aligned.
[0051]
Next, as shown in FIG. 1D, a first wiring resist pattern is formed using a CF-based etching gas for patterning the oxide film and a Cl-based etching gas for patterning the aluminum film. From the surface having 110, dry etching is sequentially performed using the first wiring resist pattern 110 as a mask. First, the first interlayer insulating film 104 in the opening of the first wiring resist pattern 110 is removed by dry etching using a CF-based etching gas at a low temperature. In this case, the interlayer connection metal 109 in the misalignment portion 112 is hardly etched by the CF-based etching gas. Further, the first metal layer 103 in the opening of the first wiring resist pattern 110 is removed by dry etching using a Cl-based etching gas until the insulating film 102 is exposed. As a result, the first wiring 113A is formed. Also in this case, the interlayer connection metal 109 in the misalignment portion 112 is not etched by the Cl-based etching gas. In the etching for forming the first wiring 113A, both the first wiring resist pattern 110 and the interlayer connection metal 109 function as an etching mask.
[0052]
FIG. 3B is a perspective view showing the positional relationship between the first wiring 113 and the interlayer connection metal 109 corresponding to the presence or absence of misalignment. First, consider the case of the wiring 113B formed from the first metal layer 103 without being misaligned by dry etching. In this case, an interlayer connection metal 109 having the same diameter as the width of the wiring 113B is formed on the upper surface of the wiring 113B. On the other hand, consider the case of the wiring 113C formed out of alignment from the first metal layer by dry etching. In this case, the first metal layer located under the interlayer connecting metal 109 is not etched during the dry etching. Therefore, in the misalignment portion 112 in FIG. 8A, the first metal layer located under the interlayer connecting metal 109 remains without being etched by self-alignment, so that the shape as shown in FIG. A wiring 113 </ b> C having is formed. Thus, the first wiring 113A composed of the wiring 113B or the wiring 113C is necessarily formed on the entire lower surface of the interlayer connection metal 109. In addition, since the portion under the first wiring resist pattern 110 in FIG. 8A is not etched, the portion above the first wiring 113A where the interlayer connection metal 109 does not exist is the first portion. The interlayer insulating film 104 remains as it is. As a result, either the first interlayer insulating film 104 or the interlayer connection metal 109 always exists on the first wiring 113A. Therefore, the first metal layer 103 existing under the interlayer connection metal 109 or the first wiring resist pattern 110 forms the first wiring 113A. The total film thickness of the first wiring 113A formed from the first metal layer 103 and the first interlayer insulating film 104 is 1.5 μm. Therefore, the aspect ratio of the groove 115 formed in the portion having the minimum width of 0.3 μm in the wiring gap 114 which is a region between the adjacent first wirings 113A is about 5. A wiring dummy pattern may be formed in the field portion 116 where the first wiring does not exist.
[0053]
Thus, according to the present embodiment, the planar pattern of both the first interlayer insulating film 104 and the interlayer connecting metal 109 defines the planar pattern of the first wiring 113A.
[0054]
Next, as shown in FIG. 2A, the insulating film 102, the first interlayer insulating film 104, and the interlayer connecting metal 109 of the semiconductor substrate 101 after the first wiring resist pattern 110 is peeled off are removed. A second interlayer insulating film 117 is deposited thereon using a plasma CVD apparatus. A part or all of the region of the wiring gap 114 in the groove formed in the wiring gap 114 becomes a hole 118 without being filled with the second interlayer insulating film 117. In particular, in the groove having a high aspect ratio, the entire region of the wiring gap 114 becomes the hole 118.
[0055]
Next, as shown in FIG. 2B, the surfaces of the first interlayer insulating film 104, the interlayer connecting metal 109, and the second interlayer insulating film 117 are substantially flush using the CMP method. Thus, the second interlayer insulating film 117 is planarized. The first interlayer insulating film 104 and the second interlayer insulating film 117 are made of different materials, and the etching rate of the first interlayer insulating film 104 in CMP is lower than the etching rate of the second interlayer insulating film 117. Set as follows. Thus, the first interlayer insulating film 104 is used as an etching stopper. Since the second interlayer insulating film 117 is buried to some extent in the upper part of the trench having a high aspect ratio, the void 118 forms an opening in the surface of the second interlayer insulating film 117 after CMP. There is no.
[0056]
Next, as shown in FIG. 2C, a metal layer having a laminated structure of aluminum and a titanium alloy is deposited, and a second wiring 119 is formed using photolithography and dry etching.
[0057]
As described above, according to the present embodiment, a part or all of the region of the wiring gap 114 becomes the air hole 118 made of air, so that the relative dielectric constant between the first wirings 113A sandwiching the wiring gap 114 is obtained. Can be reduced. In particular, when the groove 115 formed in the wiring gap 114 has a high aspect ratio, the entire area of the wiring gap 114 becomes a hole 118, so that the relative dielectric constant between the first wirings 113A is minimized. can do.
[0058]
Further, since the first wiring 113A is formed after the interlayer connection metal 109 is formed, the first wiring 113A is always formed on the entire lower surface of the interlayer connection metal 109. Accordingly, connection failure between the first wiring 113A and the interlayer connection metal 109 can be prevented.
[0059]
Further, after the interlayer connection metal 109 is formed in the interlayer connection hole 106 of the first interlayer insulating film 104, the first wiring 113A and the second interlayer insulating film 117 are sequentially formed. Thus, even if misalignment occurs during the formation of the first wiring, either the interlayer connection metal 109 or the first interlayer insulating film 104 is necessarily present on the upper surface of the first wiring 113A, and The interlayer connection metal 109 is not embedded in the hole 118 formed simultaneously with the second interlayer insulating film 117. Therefore, it is possible to prevent a short circuit failure between the first wirings 113A and a short circuit failure between the wiring and the semiconductor substrate 101 via the interlayer connection metal 109.
[0060]
(Second Embodiment)
A second embodiment of the present invention will be described with reference to FIG. 4A to 4C are process flow diagrams showing a method for manufacturing a semiconductor device according to this embodiment. Since the steps up to FIG. 1A are the same as those in FIGS. 1A to 1D, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. . In the present embodiment, instead of depositing the second interlayer insulating film 117 by the plasma CVD apparatus in the first embodiment, the second interlayer insulating film 217 is formed by a coating method. As the second interlayer insulating film 217, for example, an organic film made of a material such as organic polysiloxane or an organic substance containing fluorine, an inorganic porous film, or the like can be considered. Many of these materials are fluid.
[0061]
First, as shown in FIG. 4A, the material is applied on the first interlayer insulating film 104, the interlayer connecting metal 109, and the wiring gap 214. As a result, the second interlayer insulating film 217 can be formed by filling the groove in the wiring gap 214 with the fluid material without generating voids. A material having a relative dielectric constant lower than that of the first interlayer insulating film 104 is selected as the material of the second interlayer insulating film 217. Therefore, the relative dielectric constant between the first wirings 113A sandwiching the wiring gap 214 can be reduced. Next, as shown in FIG. 4B, the surfaces of the first interlayer insulating film 104, the interlayer connecting metal 109, and the second interlayer insulating film 217 are flush with each other using the CMP method. Then, the second interlayer insulating film 217 is planarized. The first interlayer insulating film 104 and the second interlayer insulating film 217 are made of different materials, and the etching rate of the first interlayer insulating film 104 in CMP is lower than the etching rate of the second interlayer insulating film 217. Set as follows. Thus, the first interlayer insulating film 104 is used as an etching stopper. Next, as shown in FIG. 4C, a metal layer having a laminated structure of aluminum and a titanium alloy is deposited, and a second wiring 219 is formed using photolithography and dry etching.
[0062]
As described above, according to the present embodiment, the entire region of the wiring gap 214 is filled with the second interlayer insulating film 217 using a material having a relative dielectric constant lower than that of the first interlayer insulating film 104. Therefore, the relative dielectric constant between the first wirings 113A sandwiching the wiring gap 214 can be reduced, and the relative dielectric constant can be determined by the material of the second interlayer insulating film 217.
[0063]
Further, since the first wiring 113A is formed after the interlayer connection metal 109 is formed, the first wiring 113A is always formed on the entire lower surface of the interlayer connection metal 109. Accordingly, connection failure between the first wiring 113A and the interlayer connection metal 109 can be prevented.
[0064]
In addition, after the interlayer connection metal 109 is formed in the interlayer connection hole of the first interlayer insulating film 104, the first wiring 113A and the second interlayer insulating film 217 are sequentially formed. Thus, even if misalignment occurs during the formation of the first wiring, either the interlayer connection metal 109 or the first interlayer insulating film 104 always exists on the upper surface of the first wiring 113A, and the wiring A second interlayer insulating film 217 always exists in the gap 214. Therefore, it is possible to prevent a short circuit failure between the first wirings 113A and a short circuit failure between the wiring and the semiconductor substrate 101 via the interlayer connecting metal 109.
[0065]
(Third embodiment)
A third embodiment of the present invention will be described with reference to FIGS. FIGS. 5A to 5D are process flow diagrams showing a method for manufacturing a semiconductor device according to this embodiment. The steps up to FIG. 5A are the same as those in the first embodiment, that is, FIGS. 1A to 1D and FIG. 1 except that the thickness (2.5 μm) of the first interlayer insulating film 304 is increased. 2 (a) and (b) are the same as those in the first embodiment, and the same reference numerals are given to the same components as in the first embodiment, and the description thereof is omitted.
[0066]
First, as shown in FIG. 5A, a second wiring reverse resist pattern 320 is formed on the first interlayer insulating film 304, the interlayer connection metal 309, and the second interlayer insulating film 317 by photolithography. Form. Consider a case where the second wiring reverse resist pattern 320 is formed with a misalignment of 311. For example, when the diameter of the interlayer connection hole is 0.3 μm and the width of the groove of the second wiring reverse resist pattern 320 is 0.3 μm, the interlayer connection metal 309 embedded in the interlayer connection hole and The allowable deviation dimension 311 from the groove of the second wiring reverse resist pattern 320 is 0.1 μm at the maximum. Next, as shown in FIG. 5B, the first interlayer insulating film 304 and the second interlayer insulating film 317 are etched to form a wiring groove 321A having a depth of 0.5 μm. Next, as shown in FIG. 5C, after depositing an adhesion layer (not shown) made of a titanium alloy, a second metal layer 322 made of aluminum, an alloy of aluminum and copper, or copper or the like. Form. In order to form the second metal layer 322, a vacuum deposition method, a CVD method, or the like is used. Next, as shown in FIG. 5D, the second wiring 323 is formed by removing the second metal layer that exists in areas other than the wiring trenches by CMP.
[0067]
The relationship between the displacement of the second wiring 323 caused by the displacement of the second wiring reversal resist pattern 320 and the interlayer connection metal 309 will be described with reference to FIGS. 6 and 5B to 5D. . FIG. 6 is a perspective view showing the positional relationship between the wiring groove in which the second wiring is to be formed and the interlayer connection metal, corresponding to the presence or absence of misalignment. In FIG. 6, the case of the wiring groove 321B formed without misalignment by dry etching is considered. In this case, a wiring groove 321B having the same width as the diameter of the interlayer connection metal 309 is formed. Since the second wiring is formed inside the wiring groove 321B, the interlayer connecting metal 309 and the second wiring are in contact with each other over almost the entire side surface of the interlayer connecting metal 309. On the other hand, consider the case of the wiring trench 321C formed by misalignment by dry etching. In this case, the wiring groove 321C having the same width as the diameter of the interlayer connection metal 309 is formed by being shifted by the shift dimension 311 in FIG. Since the interlayer connection metal 309 is not etched, the portion other than the portion of the side surface of the interlayer connection metal 309 that bites into the first interlayer insulating film 304 by the deviation dimension 111 is exposed to the wiring trench 321C. Therefore, most of the side surfaces of the interlayer connection metal 309 are in contact with the second metal layer 322 in FIG. 5C, and further in contact with the second wiring 323 in FIG. 5D after CMP.
[0068]
As described above, according to the present embodiment, even when the second wiring reverse resist pattern 320 for forming the second wiring 323 is misaligned, most of the side surfaces of the interlayer connection metal 309 are formed. The second wiring 323 is contacted. Therefore, in addition to the same effects as those of the first embodiment, even when the second wiring reverse resist pattern 320 is misaligned, the reliability of the connection between the interlayer connection metal 309 and the second wiring 323 is improved. Can be improved.
[0069]
(Fourth embodiment)
With reference to FIGS. 7A to 7D, FIGS. 8A to 8C, and FIGS. 9A and 9B, a method for manufacturing the semiconductor device according to the present embodiment will be described.
[0070]
First, as shown in FIG. 7A, an insulating film 102 (thickness 0.8 μm), a laminated structure of aluminum and a titanium alloy is formed on a semiconductor substrate 101 on which a semiconductor active element (not shown) is formed in advance. A first metal layer 103 (having a thickness of 0.5 μm) and a first interlayer insulating film 104 (having a thickness of 1.0 μm) are sequentially deposited. Thereafter, an interlayer connection resist pattern 105 is formed, and an interlayer connection hole 106 is opened by dry etching.
[0071]
Next, as shown in FIG. 7B, an adhesion layer 107 made of TiN / Ti, for example, is deposited on the surface having the interlayer connection hole 106 after the interlayer connection resist pattern 105 is peeled off, and the blanket. An interlayer connection material 108 made of tungsten is deposited by W-CVD. The adhesion layer 107 and the interlayer connection material 108 that exist outside the inside of the interlayer connection hole 106 are removed by dry etching or CMP. The adhesion 107 and the interlayer connection material 108 existing only inside the interlayer connection hole 106 together constitute an interlayer connection metal 109.
[0072]
Next, as shown in FIG. 7C, the first interlayer insulating film 104 is etched back by about 0.5 μm, and the remaining film thickness of the first interlayer insulating film 104 is adjusted to 0.5 μm. At this time, the interlayer connection metal 109 protrudes upward from the surface of the first interlayer insulating film 104.
[0073]
Next, as shown in FIG. 7D, a first wiring resist pattern 110 is formed on the first interlayer insulating film 104 and the interlayer connecting metal 109. Consider a case where the first wiring resist pattern 110 is formed with a misalignment of 111 by misalignment. For example, if the diameter of the interlayer connection hole 106 is 0.3 μm and the width of the first wiring resist pattern 110 is 0.3 μm, the interlayer connection metal 109 embedded in the interlayer connection hole 106 and the first connection metal 109 The allowable deviation dimension 111 with respect to the wiring resist pattern 110 is 0.1 μm at the maximum.
[0074]
FIG. 3A is a plan view showing the relationship between the displacement of the first wiring resist pattern 110 and the interlayer connection metal 109. The case where the position of the first wiring resist pattern 110 is shifted from the position of the interlayer connection metal 109 is shown on the lower side of the wavy line in FIG. 3A, and the first wiring is shown on the upper side of the wavy line. In this example, the position of the resist pattern 110 for alignment and the position of the interlayer connection metal 109 are aligned.
[0075]
Next, as shown in FIG. 8A, a first wiring resist pattern 110 is formed using a CF-based etching gas for removing the oxide film and a Cl-based etching gas for removing aluminum. The surface having the is sequentially dry-etched. First, the first interlayer insulating film 104 in the opening of the first wiring resist pattern 110 is removed by dry etching using a CF-based etching gas at a low temperature. In this case, the interlayer connection metal 109 in the misalignment portion 112 is not etched by the CF-based etching gas. Further, the first metal layer 103 in the opening of the first wiring resist pattern 110 is removed by dry etching using a Cl-based etching gas until the insulating film 102 is exposed. As a result, the first wiring 113A is formed. Also in this case, the interlayer connection metal 109 in the misalignment portion 112 is not etched by the Cl-based etching gas.
[0076]
FIG. 3B is a perspective view showing the positional relationship between the first wiring 113 and the interlayer connection metal 109 corresponding to the presence or absence of misalignment. First, consider the case of the wiring 113B formed from the first metal layer 103 without being misaligned by dry etching. In this case, an interlayer connection metal 109 having the same diameter as the width of the wiring 113B is formed on the upper surface of the wiring 113B. On the other hand, consider the case of the wiring 113C formed out of alignment from the first metal layer by dry etching. In this case, the first metal layer located under the interlayer connecting metal 109 is not etched during the dry etching. Therefore, in the misalignment portion 112 in FIG. 8A, the first metal layer located under the interlayer connecting metal 109 remains without being etched by self-alignment, so that the shape as shown in FIG. A wiring 113 </ b> C having is formed. Thus, the first wiring 113A composed of the wiring 113B or the wiring 113C is necessarily formed on the entire lower surface of the interlayer connection metal 109. In addition, since the portion under the first wiring resist pattern 110 in FIG. 8A is not etched, the portion above the first wiring 113A where the interlayer connection metal 109 does not exist is the first portion. The interlayer insulating film 104 remains as it is. As a result, either the first interlayer insulating film 104 or the interlayer connection metal 109 always exists on the first wiring 113A.
[0077]
Next, as shown in FIG. 8B, the insulating film 102 is etched by about 0.5 μm by dry etching using a CF-based etching gas. As a result, the first wiring 113A having the upper and lower sides sandwiched between the insulating films is formed. An insulating film not engraved immediately below the first wiring 113A is defined as 112A. Therefore, the first metal layer 103 existing under the interlayer connection metal 109 or the first wiring resist pattern 110 forms the first wiring 113A.
[0078]
The total film thickness of the first wiring 113A formed from the first metal layer 103, the first interlayer insulating film 104, and the insulating film 112A is 1.5 μm. Therefore, the aspect ratio of the groove 115 formed in the portion having the minimum width of 0.3 μm in the wiring gap 114 which is a region between the adjacent first wirings 113A is about 5. A wiring dummy pattern may be formed in the field portion 116 where the first wiring does not exist.
[0079]
Next, as shown in FIG. 8C, the insulating film 102, the first interlayer insulating film 104, and the interlayer connecting metal 109 of the semiconductor substrate 101 after the first wiring resist pattern 110 is peeled off are removed. A second interlayer insulating film 117 is deposited thereon using a plasma CVD apparatus. A part or all of the region of the wiring gap 114 in the groove formed in the wiring gap 114 becomes a hole 118 without being filled with the second interlayer insulating film 117. In particular, in the groove having a high aspect ratio, the entire region of the wiring gap 114 becomes the hole 118. Next, as shown in FIG. 9A, the second interlayer insulation is performed using the CMP method so that the surfaces of the interlayer connecting metal 109 and the second interlayer insulating film 117 are flush with each other. The film 117 is planarized. Since the second interlayer insulating film 117 is buried to some extent in the upper part of the trench having a high aspect ratio, the void 118 forms an opening in the surface of the second interlayer insulating film 117 after CMP. There is no. Next, as shown in FIG. 9B, a metal layer having a laminated structure of aluminum and a titanium alloy is deposited, and a second wiring 119 is formed using photolithography and dry etching.
[0080]
Here, referring to FIGS. 10A and 10B and FIGS. 11A and 11B, how the shape of the holes formed by the deposition method of the second interlayer insulating film 117 changes. Explain what to do.
[0081]
First, reference is made to FIG. FIG. 10A shows an ideal form in which the second interlayer insulating film 117 does not enter the trench 115 at all, and the holes occupy all of the trench 115. In this case, since there is no insulating film between the adjacent wirings 113A, the capacitance C1 between the wirings becomes very small. In the case shown in FIG. 10A, the upper end of the hole does not extend above the upper surface of the first interlayer insulating film 104. For this reason, even if the second interlayer insulating film 117 is polished by the CMP method, there is little possibility that the holes are exposed. If the second interlayer insulating film 117 is polished by the CMP method and the vacancy leads to the outside through the polishing surface, the function as the interlayer insulating film is impaired, and there is a possibility that a short circuit between the wirings may occur. .
[0082]
FIG. 10B shows a form in which the second interlayer insulating film 117 is deposited on the bottom and side surfaces of the groove 115 and the vacancies occupy a small portion in the groove 115. Such a form can be obtained when the second interlayer insulating film 117 is deposited under conditions with good coverage. For example, in the case of a plasma CVD method using TEOS as a raw material, an insulating film having a certain thickness is deposited on the bottom and side surfaces of the trench 115 before the second interlayer insulating film 117 in the deposition process closes the top of the trench 115 To do. As a result, the capacitance C2 between the wirings 113A increases.
[0083]
FIG. 11A shows a form in which the second interlayer insulating film 117 does not enter the trench 115 at all, and the upper portion 118 of the hole extends above the upper surface of the first interlayer insulating film 104. Is shown. Such a form can be obtained when the second interlayer insulating film 117 is formed under conditions by a deposition method with poor coverage and high directivity. For example, when the second interlayer insulating film 117 is formed from a film called a high density plasma (HDP) film, holes having a form as shown in FIG. 11A are obtained. In this case, since the insulating film is not deposited inside the trench 115, the capacitance C3 between the wirings 113A is reduced.
[0084]
The high density plasma (HDP) film is formed using an HDP apparatus. In this HDP apparatus, if an HDP film is deposited while applying a bias voltage to the substrate, an etching phenomenon also occurs during the deposition so as to compete with the deposition. Of the first interlayer insulating film 104 does not spread above the upper surface of the first interlayer insulating film 104. Such a hole is shown in FIG. When the second interlayer insulating film is formed with the HDP film deposited while applying a bias voltage to the substrate, a slight amount of insulating material is deposited on the bottom surface of the groove, but the insulating film that is the lower layer of the first wiring layer is etched. In this case, since the deposited insulator is located below the level of the first wiring layer, the capacitance C4 between the wirings 113A is kept low.
[0085]
Therefore, as shown in FIG. 8B, when the step of etching the insulating film 102 is performed, the capacitance C4 between the wirings 113A is kept low even if an insulator is slightly deposited on the bottom surface of the groove. . This will be described with reference to FIGS. 12 (a) and 12 (b). FIG. 12A shows one form of a hole when the step of not etching the insulating film 102 is performed, and FIG. 12B shows one form of a hole when the step of etching the insulating film 102 is performed. Show. In the case of FIG. 12A, if an insulator is deposited on the bottom surface of the groove, an insulator exists between the wires, and the capacitance C5 becomes larger than the capacitance C4. For this reason, when the second interlayer insulating film is formed by a deposition method that forms holes of the form shown in FIGS. 10B and 11B, the step of etching the insulating film 102 is performed. It is preferable to make the bottom surface of the groove lower than the lower surface of the first wiring layer 113A.
[0086]
From the viewpoint of reducing the capacitance between wirings, it is most preferable to form a hole having a form as shown in FIG. 11A. However, when the second interlayer insulating film is planarized by CMP, the hole is not formed. There is a high possibility that the second interlayer insulating film is etched to a level where the upper end is located. However, if the interlayer connection metal 109 is protruded above the level of the upper surface of the first interlayer insulating film 104, polishing formed by CMP can be stopped at the level of the upper surface of the interlayer connection metal 109. Become. That is, the interlayer connection metal 109 functions as a kind of etching stop layer. In this case, since it becomes easy to control so that the polishing surface is positioned higher than the upper end of the hole, even if the hole having the form shown in FIG. Further, in the case of forming a hole having the form shown in FIG. 11A, the necessity for etching the insulating film 102 is low. However, the inter-wiring capacitance C3 when the insulating film 102 is etched is lower than the inter-wiring capacitance when the insulating film 102 is not etched at all. This is because the inter-wiring capacitance is determined by the physical properties of a space with a certain extent that is located between two adjacent wirings, so that it also affects the dielectric constant of the space above and below the space directly beside the wiring. To receive.
[0087]
From the above, partial etching of the insulating film 102 located in the region between the first wiring layers 113A is effective for reducing the wiring capacity when forming various vacancies. I understand that.
[0088]
As described above, according to the present embodiment, a part or all of the region of the wiring gap 114 becomes the air hole 118 made of air, so that the relative dielectric constant between the first wirings 113A sandwiching the wiring gap 114 is obtained. Can be reduced. In particular, when the groove 115 formed in the wiring gap 114 has a high aspect ratio, the entire area of the wiring gap 114 becomes a hole 118, so that the relative dielectric constant between the first wirings 113A is minimized. can do.
[0089]
Further, since the first wiring 113A is formed after the interlayer connection metal 109 is formed, the first wiring 113A is always formed on the entire lower surface of the interlayer connection metal 109. Accordingly, connection failure between the first wiring 113A and the interlayer connection metal 109 can be prevented.
[0090]
Further, after the interlayer connection metal 109 is formed in the interlayer connection hole 106 of the first interlayer insulating film 104, the first wiring 113A and the second interlayer insulating film 117 are sequentially formed. Thus, even if misalignment occurs during the formation of the first wiring, either the interlayer connection metal 109 or the first interlayer insulating film 104 is necessarily present on the upper surface of the first wiring 113A, and The interlayer connection metal 109 is not embedded in the hole 118 formed simultaneously with the second interlayer insulating film 117. Therefore, it is possible to prevent a short circuit failure between the first wirings 113A and a short circuit failure between the wiring and the semiconductor substrate 101 via the interlayer connection metal 109.
[0091]
(Fifth embodiment)
A fifth embodiment of the present invention will be described with reference to FIGS. 13 (a) to (d). FIGS. 13A to 13D are process flow diagrams showing a method for manufacturing a semiconductor device according to this embodiment. Since the steps up to FIG. 13A are the same as those in FIGS. 1A to 1D and FIGS. 8A and 8B, the same components as those in the first embodiment are the same. Reference numerals are assigned and explanations thereof are omitted. In this embodiment, instead of depositing the second interlayer insulating film 117 by the plasma CVD apparatus in the first embodiment, the second interlayer insulating film 212 is formed by a coating method. As the second interlayer insulating film 212, for example, an organic film made of a material such as organic polysiloxane or fluorine-containing organic material, an inorganic porous film, or the like can be considered. Many of these materials are fluid.
[0092]
First, as shown in FIG. 13A, the material is applied on the first interlayer insulating film 204, the interlayer connection metal 208, and the wiring gap 215 formed on the semiconductor substrate 201. As a result, the second interlayer insulating film 212 can be formed by embedding the fluid material in the grooves in the wiring gap 215 without generating voids. A material having a relative dielectric constant lower than that of the first interlayer insulating film 204 is selected as a material for the second interlayer insulating film 212. Therefore, the relative dielectric constant between the first wirings 203 sandwiching the wiring gap 215 can be reduced. Next, as shown in FIG. 13B, the surfaces of the first interlayer insulating film 204, the interlayer connecting metal 208, and the second interlayer insulating film 212 are flush with each other using the CMP method. Then, the second interlayer insulating film 212 is planarized. The first interlayer insulating film 204 and the second interlayer insulating film 212 are made of different materials, and the etching rate of the first interlayer insulating film 204 in CMP is lower than the etching rate of the second interlayer insulating film 212. Set as follows. Thus, the first interlayer insulating film 204 is used as an etching stopper.
[0093]
Further, as shown in FIG. 13C, after only the second interlayer insulating film 212 is selectively etched in the depth direction by about 0.3 μm, the third interlayer insulating film 214 is deposited by about 0.5 μm. . Again, the third interlayer insulating film 214 is planarized by using the CMP method so that the surfaces of the first interlayer insulating film 204, the interlayer connecting metal 208, and the third interlayer insulating film 214 are flush with each other. .
[0094]
Next, as shown in FIG. 13D, a metal layer having a laminated structure of aluminum and a titanium alloy is deposited, and a second wiring 216 is formed using photolithography and dry etching.
[0095]
As described above, according to the present embodiment, the entire region of the wiring gap 215 is filled with the second interlayer insulating film 212 using a material having a relative dielectric constant lower than that of the first interlayer insulating film 204. Therefore, the relative dielectric constant between the first wirings 203 sandwiching the wiring gap 215 can be reduced, and the relative dielectric constant can be determined by the material of the second interlayer insulating film 212.
[0096]
Further, since the first wiring 203 is formed after the interlayer connection metal 208 is formed, the first wiring 203 is always formed on the entire lower surface of the interlayer connection metal 208. Accordingly, connection failure between the first wiring 203 and the interlayer connection metal 208 can be prevented.
[0097]
In addition, after forming the interlayer connection metal 208 in the interlayer connection hole of the first interlayer insulating film 204, the first wiring 203 and the second interlayer insulating film 212 are sequentially formed. Thus, even if misalignment occurs during the formation of the first wiring, either the interlayer connection metal 208 or the first interlayer insulating film 204 is always present on the upper surface of the first wiring 203, and the wiring The second interlayer insulating film 212 always exists in the gap 215. Accordingly, it is possible to prevent a short circuit failure between the first wirings 203 and a short circuit failure between the wiring and the semiconductor substrate 201 via the interlayer connection metal 208.
[0098]
Also in this embodiment, the insulating film 202 located in the region between the first wirings 203 is partially etched. For this reason, the wiring capacitance is almost governed by the relative dielectric constant of the second interlayer insulating film. If the insulating film 202 located in the region between the first wirings 203 is not etched, the insulating film 202 located in the vicinity of the region between the first wirings 203 increases the capacitance between the wirings to some extent. Become.
[0099]
In the present embodiment, since the third interlayer insulating film 214 is provided, the second wiring is formed even if a film made of a material having low etching resistance or plasma resistance is used as the second interlayer insulating film 212. The second interlayer insulating film is not damaged by this process. As the third interlayer insulating film, a film made of a material having high etching resistance or plasma resistance is preferably used. Therefore, even if the relative dielectric constant of the third interlayer insulating film 214 is increased, the inter-wiring capacitance for the first wiring 203 is not increased.
[0100]
In the embodiment of FIGS. 13A to 13D, no hole is formed in the wiring gap 215, but a hole may be formed in the wiring gap 215.
[0101]
(Sixth embodiment)
In this embodiment, the process until the second interlayer insulating film is formed is the same as that of the fifth embodiment. This embodiment is characterized in the step of forming the second interlayer insulating film. Hereinafter, the step of forming the second interlayer insulating film will be described in detail with reference to FIGS. 14A, 14B, and 14C.
[0102]
14A to 14C show a relatively narrow groove (first gap) 115a having a width of 0.5 μm or less and a relatively wide groove having a width larger than 0.5 μm (for example, width 0). .8 μm or more, the second gap) 115b is formed. Here, 113 A of 1st wiring layers contain the 1st-3rd wiring, and it is 1st space | interval between the 1st wiring located in the center in the figure, and the 2nd wiring located in the left side. 115a is formed, and a second gap 115b is formed between the first wiring and the third wiring located on the right side.
[0103]
FIGS. 14A and 14B show a cross section when the second interlayer insulating film 117 is formed from the same type of insulating film. In the example of FIG. 14A, an insulating film, which is considered to have relatively poor coverage, is deposited. As such a film with poor coverage, for example, in a parallel plate type plasma CVD apparatus, silane / N ₂ A plasma oxide film formed using O-based gas plasma can be used. When such a film is used, voids are formed in both the groove 115a and the groove 115b. Large holes are formed in the relatively wide groove 115b. For this reason, the upper part of the void | hole in the groove | channel 115b may exceed the level shown by the polishing plan line by CMP. If such a large hole is formed, the hole may be exposed from the polished surface after polishing by CMP. If the holes are exposed by polishing, there is a risk of disconnection failure or short-circuit failure of the second layer wiring.
[0104]
On the other hand, in the example of FIG. 14B, an insulating film that has good filling performance is deposited as the second interlayer insulating film 117. As such a film with good embedding performance, for example, a plasma oxide film formed using high density plasma (HDP) can be used. When such a film is used, the second interlayer insulating film 117 is also deposited on the bottom and side surfaces of the relatively narrow groove 115a. As a result, a hole smaller than the size of the groove is formed in the groove 115a. The inside of the relatively wide groove 115b is filled with the second interlayer insulating film 117, and no vacancy is observed there. The HDP layer is formed using an HDP apparatus. In this HDP apparatus, when an HDP film is deposited while applying a bias voltage to the substrate, an etching phenomenon also occurs during the deposition so as to compete with the deposition. Get nervous. In this case, the upper end of the hole does not reach the level indicated by the CMP polishing line. However, since the holes in the groove 115a are small, the effect of reducing the capacitance between the wirings is small.
[0105]
In the present embodiment shown in FIG. 14C, the advantages of both are taken. That is, the second interlayer insulating film 117 is formed from an insulating layer formed by at least two different forming methods. More specifically, first, the upper portion of the relatively narrow groove 115a is covered with the first interlayer insulating layer 117a, and then another wider groove 115b is filled with the second interlayer insulating layer 117b. Specifically, silane / N in a parallel plate plasma CVD apparatus. ₂ After forming the first interlayer insulating layer 117a using O-based gas plasma, the second interlayer insulating layer 117b may be deposited while applying a bias voltage to the substrate in the HDP device.
[0106]
The first interlayer insulating layer 117a and the second interlayer insulating layer 117b can be typically formed from a silicon oxide film, but the second interlayer insulating layer 117b is formed from a low dielectric constant organic coating film such as polyallyl ether, for example. May be. The first interlayer insulating layer 117a can be deposited under a pressure of 5 mTorr using, for example, silane gas, oxygen gas, and argon gas.
[0107]
According to the embodiment of FIG. 14C, a large hole is formed in the first gap 115a, the second gap 115b is filled with the second interlayer insulating layer 117b, and the hole is exposed by polishing by CMP. There is nothing.
[0108]
Increasing the size of the vacancies (ratio to the wiring gap) increases the upper end of the vacancies. The size of the holes and the height of the holes can be optimized by adjusting the thicknesses of the first interlayer insulating film 117a and the second interlayer insulating film 117b.
[0109]
Next, the evaluation result of the multilayer wiring structure produced by this embodiment is shown.
[0110]
First, reference is made to FIGS. 15 (a), 15 (b) and 15 (c).
FIG. 15A shows the positional relationship between the wiring gap and the holes. Here, “H” indicates the distance from the upper surface of the first wiring layer to the top of the hole, and “D” indicates the distance from the lower surface of the first wiring layer to the bottom of the hole. The hole occupation ratio “R” indicates the ratio of the hole width W to the wiring gap S.
[0111]
FIG. 15B shows the dependency of the hole occupation ratio R on the wiring gap S. FIG. The occupancy ratio R of the holes shows a positive value exceeding 0 when S = 0.8 μm or less. The occupation ratio R increases as the wiring gap S decreases. When S = 0.3 μm, the occupation ratio R shows a value of about 0.9.
[0112]
FIG. 15C shows the wiring gap dependency of H and D. The value of H does not exceed 500 nm in any wiring gap, and does not reach the planned CMP polishing line (800 to 1000 nm on the wiring). That is, even after the interlayer insulating film 117 is planarized by CMP, the vacancies are not exposed. For this reason, the yield of the second layer wiring does not decrease.
[0113]
Next, the effect of reducing the inter-wiring capacitance of the multilayer wiring fabricated according to this embodiment will be described with reference to FIG. In FIG. 16, as a comparative example, data when no holes are formed between the wirings are indicated by ◯ marks. In the comparative example, the inter-wiring capacity per unit length increases as the wiring gap decreases, whereas the inter-wiring capacity of the present embodiment rather decreases as the wiring gap decreases. It is considered that the decrease in the inter-wiring capacitance is caused by the fact that the occupation ratio R of the holes to the wiring gap becomes higher as the wiring gap becomes smaller.
[0114]
Reference is now made to 17 (a) and (b).
[0115]
The effect of reducing the capacitance between wirings according to the present embodiment is compared with the effect of reducing the capacitance between wirings when a low dielectric constant interlayer film is used.
[0116]
FIG. 17A is a cross-sectional view showing a configuration of a model used for calculation (simulation). FIG. 17B shows the dependence of the effective relative permittivity on the wiring interval. This effective relative dielectric constant is obtained by calculating the capacitance (per unit length) between wirings when a uniform medium having a specific dielectric constant is used as an interlayer insulating film, and the capacitance is obtained by actual measurement. And was determined by comparison. As indicated by the squares in FIG. 17B, in this embodiment, the effective relative dielectric constant decreases as the wiring gap decreases. When the wiring gap is 0.8 μm or less, holes are formed in the wiring gap. When the vacancies are formed, the effective relative dielectric constant rapidly decreases. When the wiring gap is 0.3 μm, the effective relative dielectric constant is reduced to about 1.8.
[0117]
FIG. 18 shows the relationship between the resistance value of the interlayer connection metal (via) and the diameter of the interlayer connection metal (via diameter). Even if this embodiment is compared with a comparative example in which no holes are formed, there is no significant difference between the via resistance values of the two.
[0118]
FIG. 19 shows the dependency of the via resistance value on the alignment shift amount between the first wiring layer and the interlayer connection metal. The alignment shift amount indicates the amount of misalignment between the interlayer connection metal and the first wiring layer. In the pattern used for the measurement, since the width of the first wiring layer and the via diameter are the same size, there is no overlap margin between the first wiring layer and the interlayer connection metal. As can be seen from FIG. 19, in the conventional example, the via resistance value increases as the alignment shift amount increases. However, in this embodiment, the via resistance maintains a constant value regardless of the alignment shift. . This is because even if misalignment occurs, the contact area between the first wiring and the interlayer connection metal is always the maximum value because the interlayer connection metal is surely present on the upper surface of the first wiring layer. It is because it is maintained.
[0119]
Since the second interlayer insulating film 117 is deposited after the formation of the interlayer connecting metal 109, the holes formed simultaneously with the deposition of the second interlayer insulating film 117 are not in contact with the interlayer connecting metal 109. Absent. Therefore, neither a short circuit defect between the first wirings 113A via the interlayer connection metal 109 nor a short circuit defect between the wirings and the semiconductor substrate 101 occurs.
[0120]
Note that the material of the first wiring layer is not limited to Al. For example, Cu may be used. Instead of using a plasma oxide film as the second interlayer insulating layer 117b constituting the second interlayer insulating film 117, a coating insulating film with good embedding performance may be used. Further, the second interlayer insulating film forming method described with reference to FIG. 14C can be applied to other embodiments.
[0121]
In each of the above embodiments, the present invention has been described with respect to a semiconductor device using a normal silicon substrate, but the present invention is not limited to this. As long as the semiconductor device has a multilayer wiring structure, a semiconductor substrate other than silicon or an SOI substrate may be used, or an insulating substrate such as glass or plastic may be used.
[0122]
【The invention's effect】
According to the present invention, the first wiring is always formed on the entire lower surface of the interlayer connection metal. Therefore, even when the first wiring is misaligned, the first wiring is formed. And connection failure between the metal for interlayer connection can be surely prevented. Further, the interlayer connection metal is not buried in the holes formed simultaneously with the second interlayer insulating film. Therefore, it is possible to prevent a short circuit failure between the first wirings via the interlayer connection metal and a short circuit failure between the wirings and the semiconductor substrate.
[0123]
Further, if a part or all of the wiring gap is formed with air holes, or if the whole wiring gap is filled with a material having a low relative dielectric constant, the relative dielectric constant between the first wirings sandwiching the wiring gap is increased. Can be reduced. Accordingly, a signal delay between the first wirings can be suppressed, and a semiconductor device with a wide operation margin and hardly malfunctioning can be realized.
[0124]
In addition, since most of the side surfaces of the interlayer connection metal are in contact with the second wiring, even when the second wiring is misaligned, the second wiring and the interlayer connection metal Reliability can be improved in connection.
[0125]
Even if misalignment occurs during the formation of the first wiring, either the interlayer connection metal or the first interlayer insulating film always exists on the upper surface of the first wiring, and the second interlayer insulating film is present. The interlayer connection metal is not embedded in the holes formed simultaneously with the film. Therefore, it is possible to prevent a short circuit failure between the first wirings via the interlayer connection metal and a short circuit failure between the wirings and the semiconductor substrate.
[Brief description of the drawings]
FIGS. 1A to 1D are process flow diagrams illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention. FIGS.
FIGS. 2A to 2C are process flow diagrams illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention. FIGS.
FIG. 3A is a plan view showing a positional relationship between a first wiring and an interlayer connection metal corresponding to the presence or absence of misalignment in the semiconductor device according to the first embodiment of the present invention; ) Is a perspective view thereof.
FIGS. 4A to 4C are process flow diagrams illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention. FIGS.
FIGS. 5A to 5D are process flow diagrams illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention. FIGS.
FIG. 6 is a perspective view showing a positional relationship between a wiring groove corresponding to the presence / absence of misalignment and an interlayer connection metal in a semiconductor device according to a third embodiment of the present invention.
7A to 7D are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.
FIGS. 8A to 8C are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention. FIGS.
FIGS. 9A and 9B are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention. FIGS.
FIGS. 10A and 10B are cross-sectional views showing the form of holes. FIGS.
FIGS. 11A and 11B are cross-sectional views showing other forms of holes. FIGS.
FIGS. 12A and 12B are cross-sectional views showing still other forms of holes. FIGS.
FIGS. 13A to 13D are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention. FIGS.
14A to 14C are process cross-sectional views illustrating a sixth embodiment of a method for manufacturing a semiconductor device according to the present invention.
FIGS. 15A to 15C are diagrams showing the dimensions of holes in another embodiment of the semiconductor device according to the present invention. FIGS.
FIG. 16 is a diagram showing the relationship between the wiring interval and the inter-wiring capacitance per unit length in an embodiment of the semiconductor device according to the present invention.
17A is a cross-sectional view of a wiring structure for calculating the inter-wiring capacitance of a semiconductor device, and FIG. 17B is a graph showing the relationship between the wiring gap and the effective relative dielectric constant.
FIG. 18 is a graph showing the relationship between via diameter and via resistance in an embodiment of the semiconductor device of the present invention.
FIG. 19 is a graph showing a relationship between an alignment shift amount between a first wiring layer and a via and via resistance in an embodiment of the semiconductor device of the present invention;
FIG. 20 is a cross-sectional view showing the structure of a conventional semiconductor device.
FIGS. 21A and 21B are process flow diagrams illustrating a conventional method for manufacturing a semiconductor device. FIGS.
FIGS. 22A to 22C are process flow diagrams showing a conventional method for manufacturing a semiconductor device. FIGS.
[Explanation of symbols]
101 Semiconductor substrate
102 Insulating film
103 first metal layer
104 First interlayer insulating film
105 Interlayer connection resist pattern
106 Interlayer connection hole
107 Adhesion Layer
108 Interlayer connection material
208 Metal for interlayer connection
110 First wiring resist pattern (first wiring pattern)
111 Deviation dimension
112 Misalignment
114 Wiring gap
115 groove
116 Field portion without first wiring
117 Second interlayer insulating film
118 holes
119 Second wiring

Claims (6)

Forming an insulating film on the substrate (a);
Forming a metal film on the substrate (b);
Forming a first interlayer insulating film on the metal film (c);
Forming an interlayer connection hole reaching the metal film in the first interlayer insulating film (d);
A step (e) of embedding an interlayer connection metal in the interlayer connection hole;
A step (f) of forming a resist pattern on at least a part of the metal for interlayer connection and on the first interlayer insulating film;
Etching the first interlayer insulating film using the resist pattern as a mask (g);
After the step (g), a step (h) of forming a wiring layer by etching the metal layer using the resist pattern and the interlayer connection metal as a mask;
After the step (h), the step (i) of removing the resist pattern;
After the step (i), a step (j) of forming a second interlayer insulating film first layer;
After the step (j), a step (k) of forming a second interlayer insulating film second layer,
The wiring layer is composed of a plurality of wirings formed with gaps therebetween,
The gap includes a first gap and a second gap wider than the first gap;
In the step (j), the first layer of the second interlayer insulating film closes the upper part of the first gap and exposes the lower part of the side wall to provide a hole in the first gap. Formed so as to open above the gap of
In the step (k), the second layer insulating film second layer is formed so as to be buried in the second gap . A method of manufacturing a semiconductor device according to claim 1 ,
Method of manufacturing a semiconductor device for forming the second interlayer insulating film a second layer from the second interlayer insulating film lower organic film having a dielectric constant than the first layer. A method of manufacturing a semiconductor device according to claim 1 or 2,
Wherein the second interlayer insulating film a second layer, a method of manufacturing a semiconductor device which is a plasma oxide film formed using a High Density Plasma. A method of manufacturing a semiconductor device according to claim 1 or 2,
The method of manufacturing a semiconductor device, wherein the second interlayer insulating film second layer is formed in a high density plasma device while applying a bias to the substrate. A method of manufacturing a semiconductor device according to claim 1 or 2,
  The method of manufacturing a semiconductor device, wherein the second interlayer insulating film second layer is a low dielectric constant organic coating film containing polyallyl ether. A method of manufacturing a semiconductor device according to any one of claims 1 to 5
The method of manufacturing a semiconductor device, wherein the first layer of the second interlayer insulating film is a plasma oxide film formed using silane / N ₂ O-based gas plasma in a plasma CVD apparatus.

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