JPH02113553A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To satisfy high speed operation and high density integration by a method wherein an interlayer insulating film is deposited on the whole surface, etching is performed until the upper surface of a metal protrusion is exposed, and an upper wiring layer having a required pattern is formed thereon. CONSTITUTION:After polyimide precursor, as an interlayer insulating film, is spread on the whole surface, it is transformed into polyimide by heat treatment; by uniformly etching the polyimide surface, only the upper part of a gold protrusion 5 is exposed, and an interlayer insulating film 7 is formed; a titanium tungusten film 8 as a barrier layer and a second aluminum film 9 are selectively etched in order, and an upper wiring layer 10 is formed. As a result, a lower wiring layer 6 and the upper wiring layer 10 can be electrically connected by a gold protrusion 5, so that the interlayer insulating film 7 can be sufficiently thickened, and the capacitance of each of the upper and the lower wiring layers can be reduced. Thereby, a semiconductor integrated circuit capable of high density integration and high speed operation can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit having multilayer wiring, and particularly to a method for manufacturing a semiconductor integrated circuit that aims to increase the density of wiring and reduce the capacitance between wirings.

[Conventional technology]

Conventionally, in semiconductor integrated circuits having multilayer wiring, when upper and lower wiring layers are electrically connected through an interlayer insulating film, a structure is adopted in which the interlayer insulating film is selectively etched to provide through holes.

That is, after forming a lower layer wiring and further forming an interlayer insulating film thereon, the interlayer insulating film on the lower layer wiring is selectively etched to form a through hole, and the upper layer wiring is formed in the area containing the through hole. By forming this, electrical connection between the upper and lower wiring layers is achieved.

However, with this through-hole connection structure,
Since the through-hole is formed using isotropic etching to prevent the shape of the through-hole from becoming steep, the dimensions at the top of the through-hole tend to expand.In particular, if the thickness of the interlayer insulating film is increased, Then, this dimensional expansion becomes even larger, and becomes an obstacle to increasing the density of semiconductor integrated circuits. For this reason, the thickness of the interlayer insulating film is limited by the expansion of the dimensions of the through hole, making it impossible to make the interlayer insulating film thicker, increasing the capacitance between upper and lower interconnections, and hindering the speeding up of semiconductor integrated circuits. Become.

For this reason, in the past, convex protrusions were provided on the lower wiring layer.
A structure has been proposed in which the upper and lower wirings are connected using this protrusion. That is, as shown in FIG. 4(a), an aluminum film 22 and a titanium-tungsten film 23 are sequentially deposited on an insulating film 21 of a semiconductor substrate, and then etched by anisotropic etching using a photoresist 24 formed into a desired pattern. The aluminum film 22 and titanium tungsten film 23 are etched at the same time. At this time, the wiring pattern is formed so that the wiring width of the portions 22a and 23a that are connected to the upper layer wiring is twice that of the portions 22b and 23b that are not connected.

Thereafter, as shown in FIG. 4(b), a titanium-tungsten film 23a is formed using the photoresist 24 as a mask.

Only the titanium tungsten film 23b is selectively side-etched using isotropic etching. At this time, the portions of the titanium-tungsten film 23b that are not connected to the upper layer are completely removed because the side etching covers the entire width, and the titanium tungsten film 23b that is not connected to the upper layer is completely removed. The central portion of the tungsten film 23a remains. For this reason,
This remaining titanium tungsten film 23a is configured as a protrusion and can be connected to an upper wiring layer to be formed later on the interlayer insulating film.

This method allows the interlayer insulating film to be formed thickly, reduces the capacitance between wiring layers, and is advantageous for increasing speed.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuit manufacturing method described above, especially in the method using side etching to form convex protrusions in the lower wiring layer, the lower wiring layer is used to form a part where electrical connections are made between the upper and lower wiring layers. It is necessary to form a large pattern in advance by an amount equivalent to the side etching by isotropic etching.

Therefore, the degree of wiring integration, which is how much wiring can be placed in a certain area, is determined by the wiring width of the part that electrically connects the upper and lower wiring layers. This is an obstacle to manufacturing high-density semiconductor integrated circuits.

An object of the present invention is to provide a manufacturing method capable of constructing a semiconductor integrated circuit that can satisfy both high speed and high density.

[Means to solve the problem]

A method for manufacturing a semiconductor integrated circuit according to the present invention includes the steps of forming a lower wiring layer with a desired pattern on an insulating film of a semiconductor substrate;
A step of applying a photoresist on the lower wiring layer and opening a window to expose a part of the lower wiring layer, and using the photoresist as a mask, electroplating is applied to the exposed portion of the lower wiring layer to a required thickness. a step of forming metal protrusions;
The method includes a step of depositing an interlayer insulating film over the entire surface and etching the interlayer insulating film until the upper surface of the metal protrusion is exposed, and a step of forming an upper wiring layer with a desired pattern on the interlayer insulating film including the metal protrusion. There is.

[Effect]

The above-mentioned manufacturing method does not require the step of opening through holes in the interlayer insulating film, and even if the interlayer insulating film is formed sufficiently thick, it is possible to construct a fine connection structure. Achieve capacity reduction.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(e) are cross-sectional views showing a first embodiment of the present invention in the order of manufacturing steps.

First, as shown in FIG. 1(a), a first aluminum film 2 is deposited on the entire surface of an insulating film 1 of a semiconductor substrate with a thickness of 0.8 μm using a sputtering method. A first titanium-tungsten film 3 is deposited over the entire surface as a barrier layer to a thickness of 0.3 μm using a sputtering method so that gold and aluminum do not come into direct contact.

Next, as shown in FIG. 1(b), a photoresist 4 is coated on the first titanium-tungsten film 3 and patterned to form windows at locations where the upper and lower wiring layers will be connected.

Then, by selective electroplating using this photoresist as a mask, gold is grown to a thickness of 2.0 μm only on the portions where electrical connection between the upper and lower wiring layers is made, thereby forming all the protrusions 5. The first aluminum is the current path during electroplating! 2 and the first titanium tungsten film 3 are used.

Next, as shown in FIG. 1(C), after removing the photoresist 4, the first aluminum film 2 and the first titanium-tungsten film 3 are etched using another photoresist, so that some parts are completely etched. A lower wiring layer 6 having protrusions 5 is formed.

Subsequently, as shown in FIG. 1(d), a polyimide precursor material is applied as an interlayer insulating film over the entire surface and heat-treated to convert it into polyimide. Furthermore, the surface of the polyimide is uniformly etched to expose only the upper portions of all the protrusions 5, thereby forming an interlayer vA film 7.

Then, as shown in FIG. 1(e), a second titanium-tungsten film 8 and a second aluminum film 9 as a barrier layer are sequentially deposited by sputtering and selectively etched using a photoresist. Upper layer wiring 1to is formed.

By doing this, the lower wiring layer 6 and the upper wiring layer 1
0 through all the protrusions 5, and the dimensional variation in this part can be kept extremely small regardless of the thickness of the interlayer insulating film. There is no need to increase the width of the lower wiring layer 6 in advance, making it possible to form a fine wiring layer. Also, it is possible to improve the step coverage of the upper wiring at the connection part. The film 7 can be made sufficiently thick, and the capacitance between the upper and lower wiring layers can be reduced to increase the speed.

Although this embodiment describes a two-layer wiring, the present invention can be similarly applied to a multi-layer wiring having three or more layers. Further, an insulating material other than polyimide may be used as the interlayer film, or a protrusion may be formed using a plating material other than gold. Furthermore, by increasing the thickness of the plating used to form the protrusions, it becomes possible to form the interlayer insulating film even thicker.

FIG. 2 shows a modification of the present invention, in which the first aluminum film 2. First titanium tungsten film 3. A nitride film 11 is formed on the surface of the lower wiring layer 6 composed of all the protrusions 5, and a polyimide film 7 is formed on this nitride film 11.
is formed to form an interlayer insulating film. This nitride film 11
It goes without saying that the upper surface of all the protrusions 5 must be removed.

According to this configuration, the moisture resistance of the semiconductor integrated circuit can be improved by providing the nitride film 11 having good moisture resistance under the polyimide 7 having poor moisture resistance.

FIGS. 3(a) to 3(c) are cross-sectional views showing the second embodiment of the present invention in the order of manufacturing steps.

FIG. 3(a) shows, as in FIGS. 1(a) and (b), after depositing the first aluminum film 2 and the first titanium-tungsten film 3, all the protrusions 5 are formed using electroplating. This shows the state in which the

Thereafter, as shown in FIG. 3(b), when forming a photoresist for forming a lower wiring layer, buttering is performed so that all the protrusions 5 protrude from the photoresist 12.

Then, using this photoresist 12 as a mask, the first titanium tungsten film 3 and the first aluminum film 2 are etched by ion etching. This results in
As shown in FIG. 3(C), the films 3 and 2 directly under all the protrusions 5 are not etched because the entire protrusions 5 act as a mask, so the width of the lower wiring layer 6 to be formed is the width of all the protrusions 5. It is possible to make it as thin as possible. Therefore, it is not necessary to widen the spacing between the wirings in accordance with the width dimension of all the protrusions 5, and the wiring pitch can be narrowed to reduce the area occupied by the wiring region, and it is possible to increase the density of the semiconductor integrated circuit.

〔Effect of the invention〕

As described above, the present invention does not require the step of opening through holes in the interlayer insulating film, so even if the interlayer insulating film is thick, high integration of wiring can be achieved, and the capacitance between upper and lower wiring layers can be reduced. This has the effect of manufacturing high-density and high-speed semiconductor integrated circuits. Further, since no through-hole is required, flatness can be maintained at the connection portion, and step coverage of the upper wiring layer is not deteriorated.

[Brief explanation of drawings]

FIGS. 1(a) to (e) are cross-sectional views showing the first embodiment of the present invention in the order of manufacturing steps, FIG. 2 is a cross-sectional view of a modified example, and FIG.
A) to (C) are cross-sectional views showing the second embodiment of the present invention in the order of manufacturing steps, and FIGS. 4(a) and (b) are cross-sectional views showing the conventional manufacturing method in the order of the steps. DESCRIPTION OF SYMBOLS 1... Insulating film on semiconductor substrate, 2... First aluminum film, 3... First titanium tungsten film, 4...
... Photoresist, 5 ... All projections, 6 ... Lower wiring layer, 7 ... Interlayer insulating film (polyimide), 8 ... Second titanium tungsten film, 9 ... Second aluminum Film, 10... Upper wiring layer, 11... Nitride film, 12
... Photoresist, 21 ... Insulating film, 22.2
2a, 22b...aluminum film, 23.23a, 2
3b...Titanium tungsten film. Figure 2 Figure 3

Claims (1)

[Claims] 1. A step of forming a lower wiring layer with a desired pattern on an insulating film of a semiconductor substrate, a step of applying a photoresist on the lower wiring layer and opening a window to expose a part of the lower wiring layer, and the steps described above. A step of forming a metal protrusion of a required thickness on the exposed portion of the lower wiring layer by electroplating using a photoresist as a mask, and depositing an interlayer insulating film on the entire surface, and depositing this interlayer insulating film so that the upper surface of the metal protrusion is exposed. 1. A method of manufacturing a semiconductor integrated circuit, comprising the steps of: etching until the metal protrusions are etched; and forming an upper wiring layer with a desired pattern on an interlayer insulating film including metal protrusions.