JP2896978B2 - Method for forming multilayer wiring of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and, more particularly, to a multilayer wiring and a method of forming a semiconductor device suitable for highly integrated devices, which can reduce contact resistance and improve reliability.

[0002]

2. Description of the Related Art As the degree of integration of semiconductor devices increases, the minimum line width of semiconductor devices decreases. When the thickness is reduced to 0.5 μm or less, the size of the contact hole in which a plug for connecting the upper and lower wiring layers is to be formed is also reduced, and the ratio of the depth to the width of the contact hole increases. Therefore, when a wiring layer is formed in a contact hole by using a sputtering method which is a normal physical vapor deposition method, step coverage deteriorates, so that a problem of increasing contact resistance, electromigration and stress. Migration (stress migration)
There is a problem that reliability is reduced due to n) and the like.

A plug is formed in the contact hole in order to improve the step coverage in the contact hole. As a method of forming the plug, tungsten is deposited on an insulating film including the contact hole, and the thickness of the deposited film is equal to or larger than the thickness of the deposited film. There is a technique of forming a plug in a contact hole by etching back tungsten, and a technique of selectively growing tungsten or aluminum in which a plug is selectively grown only in a contact hole.

FIG. 1 is a structural view of a conventional multilayer wiring using plugs. FIG. 1A is a sectional view, FIG. 1B is a plan view, and FIG. 1C is an upper wiring in a contact hole. It is a figure which shows the contact state of a layer and a plug, respectively. FIG.
Referring to (A) to (C), the lower wiring layer 13 is formed so as to be connected to the upper wiring layer 18 via the plug 17 formed in the contact hole. Upper and lower wiring layers 1
An interlayer insulating film 1 for insulating them between 3 and 18
4 was formed, and an insulating film 12 was formed between the substrate 1 and the lower wiring layer 13 to insulate them. 15 '
Is a contact hole. In the multilayer wiring structure, upper and lower wiring layers 13 and 18 are electrically connected via a plug 17 formed in a contact hole. At this time, since the upper wiring layer 18 is in contact with the upper surface of the plug 17, the contact area between the upper wiring layer 18 and the plug 17 is related to the size of the contact hole. Assuming that the contact hole is an a × a square, the contact area A ₀ is A ₀ = a × a.

FIGS. 2A to 2E are cross-sectional views showing a process for forming a multilayer wiring of the semiconductor device shown in FIG. As shown in FIG. 2A, a lower insulating film 12 is formed on a semiconductor substrate 11 and a lower insulating film 1 is formed.
2 is deposited on a metal layer and patterned to form a lower wiring layer 1
Form 3 As shown in FIG. 2B, an interlayer insulating film 14 is formed on the lower insulating film 12 including the lower wiring layer 13.
The contact hole 15 is formed by etching the interlayer insulating film 14 above the lower wiring layer 13 by a photo etching process. As shown in FIG. 2C, the conductive material 1 is filled by a blanket deposition method so as to fill the contact hole 15.
6 is deposited, and the conductive material 16 is etched back as shown in FIG. 2C and 2D, a plug may be formed by selectively growing a conductive material in the contact hole instead of the above method. As shown in FIG. 2E, a metal layer is formed on the plug 17 and the interlayer insulating film 14 and patterned to form the upper wiring layer 18. Therefore,
The upper wiring layer 18 and the lower wiring layer 13 are electrically connected via the plug 17.

[0006]

However, the above-mentioned multilayer wiring structure has the following problems. 1. In the conventional multilayer wiring structure, only the upper surface of the plug is in contact with the upper wiring layer. Therefore, as the size of the contact hole decreases, the contact area between the upper wiring layer and the plug decreases. Therefore, the conventional multi-layer wiring structure has a problem in that the provision of the contact increases due to the decrease in the contact area. 2. If misalignment of the contact mask for forming the contact hole and misalignment of the mask for forming the upper wiring layer occur, the upper wiring layer cannot completely contact the upper surface of the plug, and the contact area is further reduced. There is a problem that the resistance further increases. In addition, due to imperfect contact between the upper wiring layer and the plug, not only the electrical connection between the upper wiring layer and the lower wiring layer becomes unstable, but in severe cases, the upper wiring layer and the plug are disconnected and the element is disconnected. This causes a problem that the reliability of the device is greatly reduced. 3. In the case of forming a plug in a fine contact hole by a blanket deposition process and an etch back process, when depositing a conductive material by a blanket deposition method,
As shown in FIG. 3A, the conductive material is not completely filled in the contact hole, and an etch back process is performed. Then, as shown in FIG. 3B, seam-opening is performed.
The phenomenon occurs.

In order to solve the problems of the prior art, the present invention provides a multilayer wiring structure and a method of forming a multilayer wiring of a semiconductor device, which can increase a contact area between an upper wiring layer and a plug to reduce a contact resistance. The purpose is to do. It is another object of the present invention to provide a multilayer wiring structure and a method of forming a multilayer wiring of a semiconductor element, which can prevent a failure of the element due to misalignment of a mask and improve reliability. Another object of the present invention is to provide a multilayer wiring structure of a semiconductor device and a method of forming a multilayer wiring which can prevent a break phenomenon at the time of wiring formation using a blanket deposition step and an etch back step. Yet another object of the invention is to provide
An object of the present invention is to provide a multilayer wiring structure of a semiconductor device and a method of forming a multilayer wiring suitable for a highly integrated device.

[0008]

In order to achieve the above object, a multi-layer wiring of a semiconductor device according to the present invention comprises a substrate, a lower wiring layer formed on the substrate, and an interlayer formed on the lower wiring layer. An insulating film, an upper wiring layer formed on the interlayer insulating film, a contact hole formed in the upper wiring layer and the interlayer insulating film, and a contact so as to contact an upper surface of the lower wiring layer and a side surface of the upper wiring layer. And a plug formed in the hole.

In the multilayer wiring structure, when the contact hole is square, the side where the upper wiring and the plug come into contact in the contact hole is rectangular, and the area where the upper wiring layer and the plug are in contact is the width of the contact hole and the upper wiring. It is related to the thickness of the layer. If the side surface of the contact hole where the upper wiring layer and the plug come into contact is a trapezoid whose size on the upper surface of the upper wiring layer is larger than the size on the lower surface of the upper wiring layer, the area where the upper wiring layer and the plug are in contact with each other becomes larger. It relates to the size of the contact hole on the bottom surface of the wiring layer, the size of the contact hole on the upper surface of the upper wiring layer, and the thickness of the upper wiring layer.

The present invention provides a step of forming a lower wiring layer on a substrate, a step of forming an insulating film on the substrate including the lower wiring layer, and a step of forming an upper wiring layer on the insulating film.
A step of forming a contact hole by etching the upper wiring layer and the insulating film; and a step of forming a connection plug of the upper and lower wiring layers in contact with the upper surface of the wiring layer and the side surface of the upper wiring layer in the contact hole. And a method for forming a multilayer wiring of a semiconductor device, comprising: In the method for forming a multilayer wiring, an upper wiring layer and an insulating film are anisotropically etched to form contact holes having the same size on the lower surface and the upper surface of the upper wiring layer. After the upper wiring layer is isotropically etched, the insulating film is anisotropically etched to form contact holes having inclined side surfaces.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 4 is a semiconductor multilayer wiring structure diagram according to the first embodiment of the present invention, FIG. 4 (A) is a cross-sectional view, and FIG.
FIG. 4C is a plan view, and FIG. 4C is a drawing showing a contact state between an upper wiring layer and a plug in a contact hole. FIG.
Referring to (A) to (C), the lower wiring layer 33 is formed so as to be connected to the upper wiring layer 36 via the plug 40 formed in the contact hole. An interlayer insulating film 34 for insulating them is formed between the upper and lower wiring layers 33 and 36, and a lower insulating film 32 for insulating them is also formed between the substrate 31 and the lower wiring layer 33. I have. In the multilayer wiring structure according to the first embodiment, contact holes are formed not only in the interlayer insulating film 34 but also in the upper wiring 36, and as can be seen from the plan view of FIG. Formed up to. Therefore,
The upper wiring layer 36 comes into contact with the four side surfaces of the plug 40. If the contact hole is square, the contact surface between the upper wiring layer and the plug is four squares, and the contact area is related not only to the size of the contact hole but also to the deposition thickness of the upper wiring layer 36. Therefore, assuming that the contact hole is a square having a size a × a and the deposition thickness of the upper wiring layer 36 is h as shown in FIG. 4C, the contact area A ₁ is A ₁ = 4 × a. × h. In the multilayer wiring structure according to the first embodiment, the contact area increases due to the contact between the upper wiring layer 36 and the side surface of the plug 40, so that the contact resistance can be reduced.

FIGS. 5A to 5H show 4A to 4A 'in FIG.
FIG.
FIGS. 4A to 4H are views showing a process of forming a multi-layer wiring of a semiconductor device along lines 4B-4B 'in FIG. FIGS. 5A and 6
1A, a lower insulating film 32 made of an oxide film is formed on a semiconductor substrate 31 by using a chemical vapor deposition method or a spin coating method, and a metal layer such as Al is formed on the lower insulating film 32 by a sputtering method. And patterning the lower wiring layer 33
To form As shown in FIGS. 5B and 6B, the interlayer insulating film 34 is formed on the lower insulating film 32 including the lower wiring layer 33.
An oxide film is formed by a chemical vapor deposition method or a spin coating method. As shown in FIGS. 5C and 6C, the interlayer insulating film 3
A metal layer 35 such as Al or the like is deposited on the substrate 4 by a sputtering method, and is patterned to form an upper wiring layer 36 as shown in FIGS. 5D and 6D. FIGS. 5E and 6
(E), the interlayer insulating film 34 including the upper wiring layer 36
The upper wiring layer 3 is formed by applying and patterning a photosensitive film 37 thereon.
6 is exposed. As shown in FIGS. 5F and 6F, the exposed upper wiring layer 36 is etched using the photosensitive film 37 as a mask, and then the lower interlayer insulating film 34 is etched to form a contact hole 38. . Thereby, the lower wiring layer 33 in the contact hole 38 is exposed. After removing the photosensitive film 37 as shown in FIGS. 5 (G) and 6 (G), a conductive material 39 such as tungsten, aluminum or the like is filled with an upper wiring by blanket deposition so that the inside of the contact hole 38 is filled. The conductive material 3 is deposited on the layer 36 as shown in FIGS.
9 is etched back to form a plug 40 in the contact hole 38. The lower wiring layer 33 is formed by forming the plug.
And the upper wiring layer 36 are electrically connected. When a plug is formed in the contact hole, a conductive material is selectively grown in the contact hole to form a contact hole.
It is also possible to form the plug 40 only inside 8.

FIGS. 7 and 8 are views showing a process of forming a multilayer wiring of another semiconductor device. FIG. 7 is a view taken along the line 4A-4A 'in FIG. 4, and FIG. 8 is a view taken along the line 4B-4B' in FIG. is there. FIG. 7A shows another method for forming a multilayer wiring of a semiconductor device according to the first embodiment.
8A to 7D and 8D, a lower insulating film 32 made of an oxide film is formed on a semiconductor substrate 31.
Is formed by using a chemical vapor deposition method or a spin coating method, and a lower wiring layer 33 is formed thereon. An interlayer insulating film 34 made of an oxide film is formed on the lower insulating film 32 including the lower wiring layer 33 by using a chemical vapor deposition method or a spin coating method, and a metal layer 35 is deposited thereon and then patterned. The upper wiring layer 36 is formed. Next, as shown in FIGS. 7E and 8E, an upper insulating layer 41 is formed on the interlayer insulating film 34 including the upper wiring layer 36 by using a chemical vapor deposition method or a spin coating method. Then, as shown in FIGS. 7F and 8F, a photosensitive film 37 is applied on the upper insulating film 41 and is patterned to expose a part of the upper insulating film 41. FIG. 7 (G) and FIG.
As shown in (G), the exposed upper insulating film 41 is etched using the photosensitive film 37 as a mask, and then the upper wiring layer 36 and the interlayer insulating film 34 thereunder are etched to form a contact hole 38. This makes contact hole 3
8, the lower wiring layer 33 is exposed. As shown in FIGS. 7H and 8H, a conductive material 39 is deposited on the upper insulating film 41 by a blanket deposition method so that the inside of the contact hole 38 is filled. FIG.
As shown in (I), the conductive material 39 is etched back to form a plug 40 in the contact hole 38. By forming the plug, the lower wiring layer 33 and the upper wiring layer 36 are electrically connected. At this time, the upper insulating film 41 plays a role of preventing the upper wiring layer 36 from being damaged during the conductive material etch-back process. When a plug is formed in the contact hole, a conductive material is selectively grown in the contact hole and the plug 40 is formed only in the contact hole 38.
Can also be formed.

FIG. 9 is a diagram showing a semiconductor multilayer wiring structure according to a second embodiment of the present invention. FIG. 9A is a sectional view, and FIG.
FIG. 9C is a plan view, and FIG. 9C is a view showing a contact state between the upper wiring layer and the plug in the contact hole. FIG.
Referring to (A) to (C), the lower wiring layer 73 is formed so as to be connected to the upper wiring layer 76 via the plug 80 formed in the contact hole. Between the upper and lower wiring layers 73 and 76, an interlayer insulating film 74 for insulating them is provided.
Is formed, and a lower insulating film 72 is formed between the substrate 71 and the lower wiring layer 73 to insulate them. In the multilayer wiring structure according to the second embodiment, the contact hole is formed up to the upper surface of the upper wiring layer 76. At that time, the contact hole in the portion where the upper wiring layer 76 and the plug 80 are in contact has an inclined side surface. That is, since the size of the contact hole on the upper surface of the upper wiring layer 76 is larger than that on the lower surface of the upper wiring layer 76, the contact surface between the upper wiring layer 76 and the plug 80 is formed as shown in FIG.
As can be seen from the plan view of (B), the shape is not a square but a trapezoid. Therefore, the contact area between the upper wiring layer 76 and the plug 80 depends on the size of the contact hole on the upper and lower surfaces of the upper wiring layer 76 and the deposition thickness of the upper wiring layer 76. Accordingly, as shown in FIG. 9C, the contact hole is a square having a size of a × a on the lower surface of the upper wiring layer 76,
The upper surface is a square having a size of b × b, and if the deposition thickness of the upper wiring layer 76 is h, the contact area A ₂
Is A ₂ = 4 (a + b) × h / 2 = 2 (a + b) × h.

When comparing the size of the contact area between the conventional multilayer wiring structure and the multilayer wiring structures according to the first and second embodiments of the present invention, the width of the contact hole (a or Since b) tends to be gradually smaller than the deposition thickness h of the upper wiring layer, the contact area in the first embodiment is larger than in the related art, and the contact area in the second embodiment is larger than in the first embodiment. You can see that.

FIGS. 10A to 10I show 9A to 9 in FIG.
11 (A) to 11 (I) are views showing the steps of forming a multilayer wiring of the semiconductor element along the lines 9B to 9B 'in FIG. FIG.
(A) and FIGS. 11 (A) to 10 (D) and FIG.
As shown in (D), a lower insulating film 72 made of an oxide film is formed on a semiconductor substrate 71 by a chemical vapor deposition method or a spin coating method, and a metal layer of Al or the like is formed thereon by a sputtering method. The lower wiring layer 73 is formed by vapor deposition and patterning. An interlayer insulating film 74 made of an oxide film is formed on the lower insulating film 72 including the lower wiring layer 73 by using a chemical vapor deposition method or a spin coating method, and a metal layer 75 of Al or the like is formed thereon by a sputtering method. Then, the upper wiring layer 76 is formed by patterning. As shown in FIGS. 10E and 11E, the photosensitive film 7 is formed on the interlayer insulating film 74 including the upper wiring layer 76.
7 is applied and patterned to expose a part of the upper wiring layer 76. Next, as shown in FIGS. 10F and 11F, the exposed upper wiring layer 76 is isotropically etched using the photosensitive film 77 as a mask to expose the interlayer insulating film 74 therebelow. At this time, the upper wiring layer 76 has an etched surface inclined by isotropic etching. continue,
The exposed interlayer insulating film 74 is anisotropically etched using the photosensitive film 77 as a mask to form a contact hole 78 as shown in FIGS. 10 (G) and 11 (G). This allows
The lower wiring layer 73 in the contact hole 78 is exposed. The contact hole 78 is formed up to the upper surface of the upper wiring layer 76, and the upper wiring layer 76 has a trapezoidal side surface whose size on the upper surface is larger than that on the bottom surface. As shown in FIGS. 10H and 11H, tungsten is filled so that the inside of the contact hole 78 is filled.
A conductive material 79 such as aluminum or the like is deposited on the upper wiring layer 76 by a blanket deposition method, and FIG.
Then, as shown in FIG. 11I, the conductive material 79 is etched back to form the plug 80 in the contact hole. Here, when a plug is formed in the contact hole, a conductive material may be selectively grown in the contact hole to form the plug 80 only in the contact hole 78.

FIGS. 12 and 13 show another multi-layer wiring forming process of the embodiment shown in FIG. 9. FIG. 12 is a sectional view taken along the line 9A-9A 'of FIG.
FIG. 10 is a process drawing of a line 9B-9B 'in FIG. A method for forming a multilayer wiring of another semiconductor device according to the second embodiment is shown in FIG.
(A) and FIGS. 13 (A) to 12 (C) and FIG.
As shown in (C), a lower insulating film 72 made of an oxide film is formed on a semiconductor substrate 71 by using a chemical vapor deposition method or a spin coating method, and a lower wiring layer 73 is formed thereon. An interlayer insulating film 74 made of an oxide film or the like is formed on the lower insulating film 72 including the lower wiring layer 73 by a chemical vapor deposition method or a spin coating method, and a metal layer 75 is deposited thereon and then patterned to form an upper layer. The wiring layer 76 is formed. FIG. 12 (D) and FIG. 13
(D), the interlayer insulating film 74 including the upper wiring layer 76
An upper insulating film 81 made of an oxide film or the like is formed thereon by a chemical vapor deposition method or a spin coating method.
As shown in (E), a photosensitive film 77 is applied on the upper insulating layer 81 and patterned to expose a part of the upper insulating layer 81. Next, the exposed upper insulating layer 81 is etched using the photosensitive film 77 as a mask to form an upper wiring layer 76 thereunder.
To expose. At this time, the upper insulating layer 81 is made larger than the size determined by the photosensitive film so that the contact hole part to be formed in the upper insulating layer 81 is larger than the contact hole part to be formed on the lower wiring layer 73. Excessive etching beyond the deposition thickness. FIG.
13 (F) and FIG. 13 (F), after the exposed upper wiring layer 76 is anisotropically etched using the photosensitive film 77 as a mask, as shown in FIG. 12 (G) and FIG. A
The exposed edge of the upper wiring layer 76 is further etched so as to be inclined by a physical etching method such as an r ⁺ sputtering etching method. In the above, when Al is used as the material of the upper wiring layer 76, Cl ₂ or B
Anisotropic etching is performed using a gas such as Cl ₃ . next,
As shown in FIGS. 12H and 13H, the interlayer insulating film 74 is etched using the photosensitive film 77 as a mask to form a contact hole 78. In the above step, the upper wiring layer 76
12 (F) and FIG. 13 (F) during the etching step of FIG. 12 (G) and FIG. 13 (G).
Although the two etching steps of the inclined etching step are performed, after the upper insulating film 81 is excessively etched, the upper wiring layer 76 may be etched so as to be inclined by one isotropic etching step. After the formation of the contact hole, as shown in FIGS. 12I and 13I, a conductive material 79 is deposited on the upper insulating film 81 by a blanket deposition method so as to fill the inside of the contact hole 78. As shown in FIG. 12 (J) and FIG. 12 (J), a conductive material 79 is etched back to form a plug 80 in the contact hole 78. Here, the upper insulating film 81 plays a role of preventing the upper wiring layer 76 from being damaged during the etch-back process of the conductive material 79. When the plug 80 is formed in the contact hole 78, a conductive material 79 is selectively grown in the contact hole 78 to form the contact hole 7.
The plug 80 can also be formed only inside the inside 8.

[0018]

According to the present invention described above, the following effects can be obtained. 1. According to the multilayer wiring structure of the present invention, since the plug and the upper wiring layer are brought into contact with each other on the side surface of the contact hole to increase the contact area, it is possible to reduce the contact resistance despite the decrease in the size of the contact hole. Thus, a multilayer wiring structure suitable for a highly integrated device can be provided. 2. When the contact mask for forming the contact hole and the mask for forming the upper wiring layer are misaligned, not only the contact area can be prevented from being reduced and the contact resistance can be prevented from increasing, but also the upper wiring layer and the lower wiring layer can be incompatible. Complete electrical connection can also be prevented, and the reliability of the device can be greatly improved. 3. By forming the side surface of the contact hole in a portion where the plug and the upper wiring layer are in contact with each other so as to be inclined, a break phenomenon can be prevented when forming a multilayer wiring using a blanket deposition method and an etch-back process.

[Brief description of the drawings]

FIG. 1 is a diagram showing a multilayer wiring structure of a conventional semiconductor device.

FIG. 2 is a view showing a conventional multi-layer wiring forming process.

FIG. 3 is a diagram illustrating a problem that occurs when a conventional multilayer wiring is formed.

FIG. 4 is a diagram illustrating a multilayer wiring structure of a semiconductor device according to a first embodiment of the present invention;

FIG. 5 is a view showing a process of forming a multilayer wiring of the semiconductor element along lines 4A to 4A 'in FIG.

6 is a process chart of forming a multi-layer wiring of the semiconductor device along the line 4B-4B 'in FIG. 4;

FIG. 7 is a view showing a step of forming a multi-layer wiring of another semiconductor element along the line 4A-4A 'in FIG. 4;

8 is a view showing a step of forming a multi-layer wiring of another semiconductor element along the line 4B-4B 'in FIG. 4;

FIG. 9 is a diagram showing a multilayer wiring structure of a semiconductor device according to a second embodiment of the present invention.

10 is a view showing a step of forming a multilayer wiring of the semiconductor element taken along lines 9A to 9A 'in FIG. 9;

11 is a view showing a step of forming a multilayer wiring of the semiconductor element taken along lines 9B to 9B 'in FIG. 9;

FIG. 12 is a view showing a step of forming a multilayer wiring of another semiconductor element along the line 9A-9A 'in FIG. 9;

13 is a view showing a step of forming a multilayer wiring of another semiconductor element, taken along lines 9B-9B 'of FIG.

[Explanation of symbols]

31, 51: semiconductor substrate, 32, 52: lower insulating film, 3
3, 53 ... lower wiring layer, 34, 54 ... interlayer insulating film, 3
5, 55: metal layer, 36, 56: upper wiring layer, 41, 8
DESCRIPTION OF SYMBOLS 1 ... Upper insulating film, 37, 77 ... Photosensitive film, 38, 58 ... Contact hole, 39, 59 ... Conductive substance, 40, 60
…plug.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-310606 (JP, A) JP-A-4-3961 (JP, A) JP-A-5-29479 (JP, A) JP-A-7- 321204 (JP, A) Hikaru Hei 2-63542 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/3205 H01L 21/3213 H01L 21/768

Claims (1)

(57) [Claims] A step of forming a lower wiring on the substrate; a step of forming an insulating film on the substrate including the lower wiring; a step of forming an upper wiring on the insulating film; Forming a photosensitive film on the substrate, removing a part of the photosensitive film in a region corresponding to the lower wiring to expose the upper wiring, and forming an upper surface of the exposed upper wiring from an opening of the photosensitive film.
Remote widely, isotropic etching as the etching, the upper surface than the opening area of the lower surface of the upper wiring
As the opening area becomes larger, open with inclined oblique side surfaces
Forming an opening in an upper wiring , forming a contact hole by anisotropically etching the insulating film so that the lower wiring is exposed using the photosensitive film as a mask, and forming a contact hole in the contact hole. Forming a plug for connecting the upper and lower wirings.