JP7287181B2 - semiconductor equipment - Google Patents

Description

The technology disclosed in this specification relates to a semiconductor device.

A semiconductor device often includes a semiconductor substrate and a protective film provided on the surface of the semiconductor substrate. The protective film is arranged to extend in a frame shape along the outer peripheral edge of the semiconductor substrate.

When the semiconductor device operates, Joule heat causes thermal deformation in each component, and thermal stress is applied to the protective film. Patent Literature 1 proposes a technique for relieving such thermal stress by dividing the protective film into a plurality of parts.

Japanese Patent Application Laid-Open No. 2006-318989

The protective film is provided in order to prevent the breakdown of the electric lines of force in the semiconductor substrate due to disturbance ions such as sodium ions (Na ⁺ ) and the reduction in the breakdown voltage of the semiconductor device. Therefore, it is desirable that the protective film has a sufficient thickness so that the disturbance ions adhering to the surface do not affect the semiconductor substrate. However, when the protective film is divided into a plurality of pieces as in Patent Document 1, part of the surface of the semiconductor substrate is exposed at the divided portions. As a result, part of the surface of the semiconductor substrate is exposed to the disturbance ions. For this reason, in the technique of Patent Document 1, there is concern that the electric lines of force within the semiconductor substrate will collapse and the breakdown voltage of the semiconductor device will decrease. An object of the present specification is to provide a semiconductor device having a protective film capable of relieving thermal stress while maintaining the function of suppressing the influence of disturbance ions.

A semiconductor device disclosed in this specification can include a semiconductor substrate and a protective film provided on the semiconductor substrate and extending in a frame shape along the outer peripheral edge of the semiconductor substrate. The protective film is formed with a plurality of cavities arranged dispersedly in the plane of the protective film. When the plurality of cavities are provided dispersedly within the surface of the protective film, the protective film is divided along the surface direction, and the thermal stress of the protective film is alleviated. Furthermore, since the plurality of cavities are formed so as to be embedded in the protective film, the protective film covers the surface of the semiconductor substrate so that the surface of the semiconductor substrate is not exposed. Therefore, the influence of disturbance ions on the semiconductor substrate is suppressed. Thus, the technique of forming the plurality of cavities in the protective film can relax the thermal stress of the protective film while maintaining the original function of the protective film to suppress the influence of disturbance ions. .

FIG. 2 is a plan view showing the appearance of the semiconductor module 10 of the embodiment; Sectional drawing in the II-II line in FIG. The enlarged view of the III section in FIG. 2 is a plan view of the semiconductor device 30; FIG. FIG. 3 is an enlarged view of part III in FIG. 2, which is an enlarged view of the step of forming a protective film 40 having cavities 42 formed therein by using a spin coating method. FIG. 3 is an enlarged view of part III in FIG. 2, which is an enlarged view of the step of forming a protective film 40 having cavities 42 formed therein by using a spin coating method. FIG. 3 is an enlarged view of part III in FIG. 2, which is an enlarged view of the step of forming a protective film 40 having cavities 42 formed therein by using a spin coating method. FIG. 3 is an enlarged view of part III in FIG. 2, which is an enlarged view of the step of forming a protective film 40 having cavities 42 formed therein by using a spin coating method.

A semiconductor module 10 of the present embodiment will be described with reference to FIGS. 1 to 4. FIG. The semiconductor module 10 of the present embodiment is employed, for example, in a power control device for an electric vehicle, and can form part of a power conversion circuit such as a converter or an inverter. An electric vehicle in this specification broadly means a vehicle having a motor for driving the wheels. Including fuel cell vehicles, etc.

As shown in FIGS. 1 and 2, the semiconductor module 10 includes a semiconductor device 30 and a sealing body 14 that seals the semiconductor device 30 . The sealing body 14 is made of an insulating material. Although not particularly limited, the sealing body 14 in this embodiment is made of a sealing material such as epoxy resin, which contains an additive such as silica. The sealing body 14 generally has a plate shape and has an upper surface 14a, a lower surface 14b, a first end surface 14c, a second end surface 14d, a first side surface 14e and a second side surface 14f.

The semiconductor device 30 is a power semiconductor element and has a semiconductor substrate 32 , an upper electrode 34 and a lower electrode 36 . The top electrode 34 is located on the top surface of the semiconductor substrate 32 and the bottom electrode 36 is located on the bottom surface of the semiconductor substrate 32 . The upper electrode 34 and the lower electrode 36 are electrically connected to each other through the semiconductor substrate 32 . Although not particularly limited, the semiconductor device 30 in this embodiment is a switching element, and can selectively turn on and off between the upper surface electrode 34 and the lower surface electrode 36 . The type of semiconductor substrate 32 is not particularly limited. The semiconductor substrate 32 may be, for example, a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate. The top electrode 34 and the bottom electrode 36 can be constructed using one or more metals, such as aluminum, nickel, or gold. As an example, the upper electrode 34 and the lower electrode 36 in this embodiment have a laminated structure in which a nickel layer is provided on an aluminum alloy (eg, aluminum-silicon alloy) layer.

As an example, the semiconductor device 30 in this embodiment is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), and a silicon carbide (SiC) substrate is adopted as the semiconductor substrate 32 thereof. Top electrode 34 is connected to the source of a MOSFET structure constructed in semiconductor substrate 32, and bottom electrode 36 is connected to the drain of the MOSFET structure. The semiconductor device 30 may be an IGBT (Insulated Gate Bipolar Transistor) or an RC (Reverse Conducting)-IGBT. In this case, the top electrode 34 is connected to the emitter of an IGBT constructed in the semiconductor substrate 32 and the bottom electrode 36 is connected to the collector of the IGBT structure. The type and specific structure of the semiconductor device 30 are not limited to those exemplified here, and can be changed in various ways. The semiconductor module 10 may also have two or more semiconductor elements, such as a combination of MOSFETs (or IGBTs) and diodes.

The semiconductor module 10 further includes a first conductor plate 16 and a second conductor plate 18 . The first conductor plate 16 and the second conductor plate 18 face each other with the semiconductor device 30 interposed therebetween. The first conductor plate 16 and the second conductor plate 18 are made of a conductor such as metal. The first conductor plate 16 and the second conductor plate 18 are integrally held by the sealing body 14 . The upper surface 16 a of the first conductor plate 16 is located inside the sealing body 14 and is joined to the lower surface electrode 36 of the semiconductor device 30 via the solder layer 13 . On the other hand, the lower surface 16b of the first conductor plate 16 is exposed to the lower surface 14b of the sealing body 14. As shown in FIG. As a result, the first conductor plate 16 constitutes a part of a circuit electrically connected to the semiconductor device 30 and also functions as a radiator plate for releasing the heat of the semiconductor device 30 to the outside.

A lower surface 18 b of the second conductor plate 18 is located inside the sealing body 14 and connected to the upper electrode 34 of the semiconductor device 30 via the conductor spacer 20 . The lower surface 18b of the second conductor plate 18 is joined to the conductor spacer 20 through the solder layer 17, and the conductor spacer 20 is joined to the upper electrode 34 of the semiconductor device 30 through the solder layer 15. . On the other hand, the upper surface 18a of the second conductor plate 18 is exposed to the upper surface 14a of the sealing body 14. As shown in FIG. Like the first conductor plate 16, the second conductor plate 18 constitutes a part of the circuit electrically connected to the semiconductor device 30, and also functions as a heat sink for releasing the heat of the semiconductor device 30 to the outside. do.

Semiconductor module 10 includes a first power terminal 22 , a second power terminal 24 , and a plurality of signal terminals 26 . The first power terminal 22 and the second power terminal 24 protrude from the first end surface 14 c of the encapsulant 14 . The first power terminal 22 is electrically connected to the first conductor plate 16 inside the sealing body 14 , and the second power terminal 24 is electrically connected to the second conductor plate 18 inside the sealing body 14 . It is connected to the. Thereby, the first power terminal 22 and the second power terminal 24 are electrically connected via the semiconductor device 30 . A plurality of signal terminals 26 protrude from the second end face 14 d of the sealing body 14 . Each signal terminal 26 is electrically connected to a signal pad 38 (see FIG. 4) of the semiconductor device 30 by wire bonding, for example.

Next, details of the semiconductor device 30 will be described with reference to FIGS. 3 and 4. FIG. As shown in FIGS. 3 and 4, the semiconductor device 30 includes an interlayer insulating film 46 provided on a surface 32f of a semiconductor substrate 32, and a protective film 40 provided on a surface 46f of the interlayer insulating film 46. . The interlayer insulating film 46 is composed of an insulator, and although it is an example, silicon oxide is adopted in this embodiment. The interlayer insulating film 46 is provided to electrically insulate the semiconductor substrate 32 and various electrodes. The protective film 40 is made of an insulator, and as an example, polyimide resin is used in this embodiment. The protective film 40 is provided in a frame shape along the outer peripheral edge 32e of the semiconductor substrate 32 and defines an opening 40w through which the upper surface electrode 34 is exposed. An outer peripheral edge 40 e of the protective film 40 covers an outer peripheral edge 46 e of the interlayer insulating film 46 , and a portion of the protective film 40 is in contact with the surface 32 f of the semiconductor substrate 32 . The protective film 40 is provided to prevent the breakdown of the electric lines of force in the semiconductor substrate 32 due to disturbance ions such as sodium ions (Na ⁺ ) and the reduction in the breakdown voltage of the semiconductor device 30 .

As shown in FIG. 3, a plurality of cavities 42 are formed in the protective film 40 . A plurality of cavities 42 are formed as grooves in the back surface of the protective film 40 , that is, the surface in contact with the front surface 46 f of the interlayer insulating film 46 , and are distributed within the surface of the protective film 40 . The shape and size of the cavity 42 are not particularly limited. As an example, the cavity 42 has a rectangular or circular horizontal cross-sectional shape with a diameter of about 10 μm. Moreover, the plurality of cavities 42 may be arranged regularly or may be arranged irregularly. As an example, the plurality of cavities 42 may be arranged regularly with a pitch of about 20 μm.

A hydrophilic film 44 is provided on the surface 46 f of the interlayer insulating film 46 exposed to each of the plurality of cavities 42 . The hydrophilic film 44 is made of a hydrophilic material, and as an example, titanium oxide (TiO ₂ ) is used in this embodiment.

A method of forming a plurality of cavities 42 within the protective film 40 will now be described with reference to FIGS. First, as shown in FIG. 5, a plurality of hydrophilic films 44 are formed on the surface 46 f of the interlayer insulating film 46 . As an example, the radius of hydrophilic membrane 44 is approximately 0.42 μm. After forming the hydrophilic film 44, the hydrophilic film 44 is irradiated with UV. This UV irradiation enables the hydrophilic film 44 made of titanium oxide (TiO ₂ ) to exhibit hydrophilicity.

Next, as shown in FIG. 6, water 52 is deposited on the hydrophilic film 44 using a spin coating method.

Next, as shown in FIG. 7, a solvent in which polyimide is dissolved is applied onto the semiconductor substrate 32 by spin coating to form a protective film 40 . At this time, by adjusting the rotation speed of the spin coating to a low speed (lower than the rotation speed of the spin coating when the water 52 is applied), the water 52 can remain attached to the hydrophilic film 44. . Moreover, by adopting a non-polar solvent as the solvent for dissolving polyimide, the water 52 can be left attached to the hydrophilic film 44 without being dissolved in the solvent. Toluene and hexane, for example, are used as the solvent.

Next, an annealing process is performed to harden the protective film 40 . Although this annealing treatment is an example, it is performed in two stages with different temperatures. The first-stage annealing process is set at a temperature of less than 100° C. and is performed so as to harden the protective film 40 by about half. The second-stage annealing treatment is set at a temperature of 100° C. or higher and is performed so as to completely harden the protective film 40 . As shown in FIG. 8, when the second-stage annealing treatment is performed, the water 52 adhering to the hydrophilic film 44 is vaporized, and the expanded water vapor forms cavities 42 . Since the protective film 40 is about half cured by the first-stage annealing treatment, the water vapor vaporized by the second-stage annealing treatment can remain in the protective film 40, thereby improving hydrophilicity. A cavity 42 is formed at a position corresponding to the membrane 44 . When the water 52 evaporates, its volume increases 1700 times. Therefore, when the water 52 adhering to the hydrophilic film 44 with a radius of about 0.42 μm evaporates, a cavity 42 with a radius of about 5.0 μm is formed. . Since polyimide does not have the ability to completely shut off water and air, the moisture in the cavity 42 is removed and the cavity 42 is replaced with air over time.

Thus, in this embodiment, a plurality of cavities 42 are arranged within the same plane of the protective film 40 . Furthermore, in this embodiment, a sufficient number of cavities 42 are arranged within the protective film 40 . Therefore, the protective film 40 is divided by the cavities 42 when observed in the surface direction of the protective film 40 .

In the semiconductor module 10, Joule heat generated by the operation of the semiconductor device 30 causes thermal deformation in each component. At this time, a large thermal stress is likely to occur in the protective film 40 . Such thermal stress is conspicuous in the semiconductor module 10 of the present embodiment that employs silicon carbide (SiC) having a relatively high Young's modulus.

In the semiconductor module 10 of the present embodiment, since the protective film 40 is divided along the surface direction by the plurality of cavities 42, the thermal stress of the protective film 40 is alleviated. Furthermore, since the cavity 42 is formed so as to be embedded in the protective film 40, the surface of the protective film 40 extends continuously. That is, the protective film 40 covers the surface of the semiconductor substrate 32 so that the surface of the semiconductor substrate 32 is not exposed. Therefore, even if disturbance ions such as sodium ions (Na ⁺ ) adhere to the surface of the protective film 40 , since the distance from the surface of the protective film 40 to the semiconductor substrate 32 is sufficiently secured, the disturbance ions do not reach the semiconductor substrate 32 . The semiconductor substrate 32 is suppressed from being affected. Thus, the technique of forming a plurality of cavities 42 in the protective film 40 can relax the thermal stress of the protective film 40 while maintaining the original function of the protective film 40 of suppressing the influence of disturbance ions. .

Although specific examples of the technology disclosed in this specification have been described above in detail, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims as filed. The techniques exemplified in this specification or drawings can achieve a plurality of purposes at the same time, and achieving one of them has technical utility in itself.

10: semiconductor module 30: semiconductor device 32: semiconductor substrate 40: protective film 42: cavity 44: hydrophilic film 46: interlayer insulating film

Claims (1)

a semiconductor substrate;
an interlayer insulating film provided on the semiconductor substrate;
a polyimide resin protective film provided on the interlayer insulating film and extending in a frame shape along the outer peripheral edge of the semiconductor substrate,
The semiconductor device according to claim 1, wherein the protective film is formed with a plurality of cavities arranged dispersedly in a plane of the protective film.

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