JP7120150B2 - semiconductor module - Google Patents

Description

The technology disclosed in this specification relates to a semiconductor module.

A semiconductor device is disclosed in Japanese Patent Laid-Open No. 2002-200013. In this semiconductor element, a surface structure such as a plurality of metal films and a protective film covering them is provided on a semiconductor substrate. The plurality of metal films include, for example, main electrodes and signal wirings, which are provided adjacent to each other.

JP 2017-152655 A

A semiconductor element is incorporated into a semiconductor module and sealed inside a sealing body. In a semiconductor module, thermal deformation occurs in each component according to temperature. At this time, a large shear stress is likely to occur between the semiconductor substrate and the surface structure, and large deformation (that is, plastic deformation) exceeding the elastic region may occur in the metal films such as the electrodes and signal wiring. If such deformation is repeated, peeling may occur between the semiconductor substrate and the surface structure, or a short circuit or insulation failure may occur between a plurality of metal films. Such problems are conspicuous in semiconductor modules employing silicon carbide (SiC), which has a relatively high Young's modulus, and countermeasures are required.

A semiconductor module disclosed in this specification includes a semiconductor element and a sealing body that seals the semiconductor element. A semiconductor element has a semiconductor substrate, a protective film provided in a frame shape along the outer periphery of the semiconductor substrate on the surface of the semiconductor substrate, and a metal film provided between the semiconductor substrate and the protective film. In this semiconductor module, the adhesion between the protective film and the sealing body is smaller in the range including the outer edge of the protective film than in the other range.

Usually, peeling between a semiconductor substrate and a surface structure (a protective film or a metal film) starts from peeling occurring at the outer edge of a semiconductor element. That is, the delamination that occurs at the outer peripheral edge of the semiconductor element progresses inward along the surface of the semiconductor substrate. As the peeling progresses between the semiconductor substrate and the surface structure, peeling occurs between the semiconductor substrate and the surface structure (metal film or protective film). Based on this finding, in the semiconductor module described above, the adhesion between the protective film and the sealing body is intentionally lowered in a part of the range including the outer peripheral edge of the protective film. According to such a configuration, peeling that occurs at the outer peripheral edge of the semiconductor element and progresses along the surface of the semiconductor substrate can be guided between the protective film and the sealing body (that is, outside the protective film). can be done. This significantly suppresses peeling between the semiconductor substrate and the surface structure (metal film or protective film).

FIG. 2 is a plan view showing the appearance of the semiconductor module 10 of the embodiment; Sectional drawing in the II-II line in FIG. The enlarged view of the III section in FIG. 2 is a plan view of the semiconductor element 12; FIG. FIG. 4 is a diagram showing an example of peeling S that occurs in the semiconductor module 10; Sectional drawing which shows the principal part (corresponding|compatible to FIG. 3) of the semiconductor module 10X of a modification. Sectional drawing which shows the principal part (corresponding|compatible to FIG. 3) of the semiconductor module 10Y of a modified example. Sectional drawing which shows the principal part (corresponding|compatible to FIG. 3) of the semiconductor module 10Z of a modified example.

A semiconductor module 10 of an embodiment will be described with reference to FIGS. 1 to 4. FIG. The semiconductor module 10 of the present embodiment is employed, for example, in a power control device for an electric vehicle, and can form part of a power conversion circuit such as a converter or an inverter. An electric vehicle in this specification broadly means a vehicle having a motor for driving the wheels. Including fuel cell vehicles, etc.

As shown in FIGS. 1 and 2, the semiconductor module 10 includes a semiconductor element 12 and a sealing body 14 that seals the semiconductor element 12 . The sealing body 14 is made of an insulating material. Although not particularly limited, the sealing body 14 in this embodiment is made of a sealing material such as epoxy resin, which contains an additive such as silica. The sealing body 14 generally has a plate shape and has an upper surface 14a, a lower surface 14b, a first end surface 14c, a second end surface 14d, a first side surface 14e and a second side surface 14f.

The semiconductor element 12 is a power semiconductor element and has a semiconductor substrate 12a, an upper surface electrode 12b and a lower surface electrode 12c. The upper electrode 12b is located on the upper surface of the semiconductor substrate 12a, and the lower electrode 12c is located on the lower surface of the semiconductor substrate 12a. The upper surface electrode 12b and the lower surface electrode 12c are electrically connected to each other through the semiconductor substrate 12a. Although not particularly limited, the semiconductor element 12 in this embodiment is a switching element, and can selectively turn on and off between the upper surface electrode 12b and the lower surface electrode 12c. The type of semiconductor substrate 12a is not particularly limited. The semiconductor substrate 12a may be, for example, a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate. The upper electrode 12b and the lower electrode 12c can be made of one or more kinds of metals such as aluminum, nickel, or gold.

As an example, the semiconductor element 12 in this embodiment is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), and a silicon carbide (SiC) substrate is adopted as the semiconductor substrate 12a. The top electrode 12b is connected to the source of a MOSFET structure constructed in a semiconductor substrate 12a, and the bottom electrode 12c is connected to the drain of the MOSFET structure. The semiconductor element 12 may be an IGBT (Insulated Gate Bipolar Transistor) or an RC (Reverse Conducting)-IGBT. In this case, the top electrode 12b is connected to the emitter of the IGBT constructed in the semiconductor substrate 12a, and the bottom electrode 12c is connected to the collector of the IGBT structure. The type and specific structure of the semiconductor element 12 are not limited to those exemplified here, and can be changed in various ways. The semiconductor module 10 may also have two or more semiconductor elements, for example a combination of MOSFETs and diodes.

The semiconductor module 10 further includes a first conductor plate 16 and a second conductor plate 18 . The first conductor plate 16 and the second conductor plate 18 face each other with the semiconductor element 12 interposed therebetween. The first conductor plate 16 and the second conductor plate 18 are made of a conductor such as metal. The first conductor plate 16 and the second conductor plate 18 are held by the sealing body 14 and face each other with the semiconductor element 12 interposed therebetween. The upper surface 16 a of the first conductor plate 16 is located inside the sealing body 14 and is joined to the lower surface electrode 12 c of the semiconductor element 12 via the solder layer 13 . The lower surface 16b of the first conductor plate 16 is exposed to the lower surface 14b of the sealing body 14. As shown in FIG. As a result, the first conductor plate 16 constitutes a part of a circuit electrically connected to the semiconductor element 12 and also functions as a radiator plate for releasing the heat of the semiconductor element 12 to the outside.

A lower surface 18 b of the second conductor plate 18 is located inside the sealing body 14 and connected to the upper electrode 12 b of the semiconductor element 12 via the conductor spacer 20 . The lower surface 18b of the second conductor plate 18 is joined to the conductor spacer 20 through the solder layer 17, and the conductor spacer 20 is joined to the upper electrode 12b of the semiconductor element 12 through the solder layer 15. . The upper surface 18 a of the second conductor plate 18 is exposed on the upper surface 14 a of the sealing body 14 . Like the first conductor plate 16, the second conductor plate 18 constitutes a part of the circuit electrically connected to the semiconductor element 12, and also functions as a heat sink for releasing the heat of the semiconductor element 12 to the outside. do.

Semiconductor module 10 includes a first power terminal 22 , a second power terminal 24 , and a plurality of signal terminals 26 . The first power terminal 22 and the second power terminal 24 protrude from the first end surface 14 c of the encapsulant 14 . The first power terminal 22 is electrically connected to the first conductor plate 16 inside the sealing body 14 , and the second power terminal 24 is electrically connected to the second conductor plate 18 inside the sealing body 14 . It is connected to the. Thereby, the first power terminal 22 and the second power terminal 24 are electrically connected via the semiconductor element 12 . A plurality of signal terminals 26 protrude from the second end face 14 d of the sealing body 14 . Each signal terminal 26 is electrically connected to the signal pad 12d (see FIG. 4) of the semiconductor element 12 by wire bonding, for example.

Next, details of the semiconductor element 12 will be described with reference to FIGS. 3 and 4. FIG. As shown in FIGS. 3 and 4, the semiconductor element 12 includes a protective film 30 provided on a semiconductor substrate 12a and a plurality of metal films 32 provided between the semiconductor substrate 12a and the protective film 30. . The protective film 30 is made of an insulator, and polyimide resin is used in this embodiment, as an example. The protective film 30 is provided in a frame shape along the outer periphery of the semiconductor substrate 12a, and defines an opening 30w that exposes the upper surface electrode 12b.

The plurality of metal films 32 include the gate wiring 12g and the like in addition to the upper electrode 12b described above. The gate wiring 12g is a transmission line for a gate signal input from the outside, and is connected to the gate of the MOSFET structure provided on the semiconductor substrate 12a. 12 g of gate wirings are provided along the periphery of the upper surface electrode 12b, and surround the upper surface electrode 12b in planar view. Each metal film 32 is at least partially located between the semiconductor substrate 12 a and the protective film 30 . These metal films 32 are made of aluminum. However, the material forming the metal film 32 is not limited to aluminum. The metal film 32 may be composed of other metals instead of or in addition to aluminum. An insulating film 34 (for example, a silicon oxide film) is formed between the semiconductor substrate 12a and the metal film 32, and the metal film 32 (excluding the upper electrode 12b) is electrically connected to the semiconductor substrate 12a. insulated.

A primer layer 36 is provided between the semiconductor element 12 and the sealing body 14 . The primer layer 36 is made of, for example, a resin material, and increases adhesion between the semiconductor element 12 and the sealing body 14 . The primer layer 36 is provided on the surfaces of the semiconductor element 12 and the conductor plates 16 and 18 when molding the sealing body 14 in the manufacturing process of the semiconductor module 10 . However, in the semiconductor module 10 of this embodiment, the formation of the primer layer 36 is omitted in the range A extending from the outer peripheral edge 12e of the semiconductor substrate 12a to a part of the protective film 30. FIG. Accordingly, the adhesion between the protective film 30 and the sealing body 14 is smaller in a partial range A including the outer peripheral edge 30e of the protective film 30 than in other ranges.

In the semiconductor module 10, thermal deformation occurs in each component according to temperature. At this time, a large shear stress is likely to occur between the semiconductor substrate 12a and the surface structure (the protective film 30 and the metal film 32). Deformation (ie, plastic deformation) can occur. If such deformation is repeated, peeling may occur between the semiconductor substrate 12 a and the surface structure, or a short circuit or insulation failure may occur between the plurality of metal films 32 . Such a problem remarkably appears in the semiconductor module 10 of this embodiment that employs silicon carbide (SiC) having a relatively high Young's modulus.

Normally, peeling between the semiconductor substrate 12a and the surface structure (the protective film 30 and the metal film 32) starts from the peeling occurring at the outer peripheral edge 12e of the semiconductor element 12. FIG. That is, as shown in FIG. 5, the peeling S generated at the outer peripheral edge 12e of the semiconductor element 12 progresses inward along the surface 12f of the semiconductor substrate 12a. If the delamination S progresses between the semiconductor substrate 12a and the surface structure (that is, between the semiconductor substrate 12a and the protective film 30), delamination will occur between the semiconductor substrate 12a and the surface structure. Become.

Based on the above knowledge, in the semiconductor module 10 of the present embodiment, the adhesive force between the protective film 30 and the sealing body 14 is intentionally is reduced to According to such a configuration, peeling S that occurs at the outer peripheral edge 12e of the semiconductor element 12 and progresses along the surface 12f of the semiconductor substrate 12a is separated from the protective film 30 and the sealing body 14 as shown in FIG. (that is, outside the protective film 30). This makes it difficult for the peeling S to progress into the surface structure, thereby significantly suppressing the peeling between the semiconductor substrate 12a and the surface structure.

In the semiconductor module 10 of this embodiment, the formation of the primer layer 36 in the range A is omitted in order to reduce the adhesive strength in the range A described above. However, as shown in FIG. 6, the primer layer 36a may be provided also in the range A in the semiconductor module 10X of the modified example. In this case, for the primer layer 36a in the area A, it is preferable to use a primer material with lower adhesion than the primer layer 36 in other areas. With such a configuration as well, the adhesion between the protective film 30 and the sealing body 14 can be made smaller in a partial range A including the outer peripheral edge 30e of the protective film 30 than in other ranges.

In the semiconductor module 10X of the modified example shown in FIG. 6, it is necessary to selectively form the two types of primer layers 36 and 36a using a mask or the like. In this regard, as shown in FIG. 7, in another modification of the semiconductor module 10Y, one primer layer 36 may be provided over the semiconductor element 12 entirely. Then, the other primer layer 36a may be superimposedly provided in the range A described above. According to such a configuration, since it is not necessary to provide a mask or the like when forming one primer layer 36, the formation of the primer layer 36 can be easily performed.

Alternatively, as shown in FIG. 8, in another modification of the semiconductor module 10Z, the primer layer 36 is provided on the entire semiconductor element 12, and foreign matter 38 such as siloxane is applied to the range A described above. may be attached to reduce the adhesion to the sealing body 14 . With such a configuration as well, the adhesion between the protective film 30 and the sealing body 14 can be made smaller in a partial range A including the outer peripheral edge 30e of the protective film 30 than in other ranges. It should be noted that there are various other methods for partially adjusting the adhesive strength between the protective film 30 and the sealing body 14, without being limited to the modes of some of the semiconductor modules 10, 10X, 10Y, and 10Z described above. can be adopted.

Although specific examples of the technology disclosed in this specification have been described above in detail, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.

The technical elements described in this specification or in the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims as filed. The techniques exemplified in this specification or drawings can achieve a plurality of purposes at the same time, and achieving one of them has technical utility in itself.

10, 10X, 10Y, 10Z: semiconductor module 12: semiconductor element 14: sealing body 16: first conductor plate 18: second conductor plate 22: first power terminal 24: second power terminal 26: signal terminal 30: protection Film 32: Metal films 36, 36a: Primer layer 38: Foreign matter that reduces adhesion

Claims (1)

a semiconductor element;
a sealing body that seals the semiconductor element;
with
The semiconductor element is
a semiconductor substrate;
a protective film provided in a frame shape along the outer peripheral edge of the semiconductor substrate on the surface of the semiconductor substrate;
a metal film provided between the semiconductor substrate and the protective film;
has
The adhesion force between the protective film and the sealing body is smaller in a part of the range including the outer peripheral edge of the protective film than in the other range.
semiconductor module.

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