JPH06283864A - Forming method for multilayer interconnection structure - Google Patents

Forming method for multilayer interconnection structure

Info

Publication number
JPH06283864A
JPH06283864A JP6861793A JP6861793A JPH06283864A JP H06283864 A JPH06283864 A JP H06283864A JP 6861793 A JP6861793 A JP 6861793A JP 6861793 A JP6861793 A JP 6861793A JP H06283864 A JPH06283864 A JP H06283864A
Authority
JP
Japan
Prior art keywords
resin
insulating film
interlayer insulating
film
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6861793A
Other languages
Japanese (ja)
Inventor
Yukio Kasuya
行男 糟谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP6861793A priority Critical patent/JPH06283864A/en
Publication of JPH06283864A publication Critical patent/JPH06283864A/en
Withdrawn legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To provide a method for controlling a relative permittivity of an layer insulating film formed of resin in the case of forming a multilayer interconnection structure. CONSTITUTION:A film 35 in which naphthoquinone azide compound 33 is mixed in polyimide resin is formed on a board 31. This sample is heated at 250-400 deg.C, and the layer 35 of the resin is cured. Thus, the compound is decomposed by heat treating for curing the film 35 of the resin to generate nitrogen gas, and hence the film 35 of the resin is foamed. As a result, an layer insulating film 37 having an air gap 37a is obtained, and an adding amount of the compound 33 is controlled to control number of the gaps 37a, thereby controlling a relative permittivity of the film 37.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、多層配線構造の形成
方法に関するものであり、特に層間絶縁膜の比誘電率の
制御を行い得る方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multilayer wiring structure, and more particularly to a method for controlling the relative dielectric constant of an interlayer insulating film.

【0002】[0002]

【従来の技術】例えば、半導体集積回路(IC)をはじ
めとする種々の電子部品が実装されるプリント基板や、
このようなプリント基板に実装されるICにおいては、
配線を層間絶縁膜を介し何層にも重ね、これら配線間は
層間絶縁膜に設けた貫通孔を利用して接続する、いわゆ
る多層配線構造が多用される。そうすることにより、プ
リント基板や半導体基板に所望の構成成分を高密度に実
装若しくは形成でき、また、電子装置やICの動作速度
の向上が図れるからである。
2. Description of the Related Art For example, a printed circuit board on which various electronic parts such as a semiconductor integrated circuit (IC) are mounted,
In an IC mounted on such a printed circuit board,
A so-called multi-layer wiring structure is often used in which wirings are stacked in multiple layers via an interlayer insulating film, and these wirings are connected using a through hole provided in the interlayer insulating film. This is because by doing so, desired constituent components can be mounted or formed on the printed circuit board or the semiconductor substrate with high density, and the operating speed of the electronic device or IC can be improved.

【0003】このような多層配線構造を利用する分野に
おいて、近年、層間絶縁膜を樹脂、特に耐熱性熱硬化性
樹脂で構成することが行われている。それは、層間絶縁
膜を真空装置などを利用して形成する方法に比べ層間絶
縁膜の形成が簡易であるなどの利点が得られるからであ
る。
In the field of utilizing such a multilayer wiring structure, in recent years, an interlayer insulating film has been made of a resin, particularly a heat resistant thermosetting resin. This is because advantages such as easier formation of the interlayer insulating film can be obtained as compared with the method of forming the interlayer insulating film using a vacuum device or the like.

【0004】樹脂で構成された層間絶縁膜を有する多層
配線構造を形成する場合、従来は一般に以下に説明する
ような方法がとられていた。図4及び図5はその説明に
供する工程図である。いずれの図も多層配線構造を形成
する工程中の主な工程での試料をその厚さ方向と平行な
方向に沿って切った断面で示したものである。
In the case of forming a multi-layer wiring structure having an interlayer insulating film made of resin, conventionally, a method generally described below has been generally used. 4 and 5 are process diagrams used for the description. Each drawing shows a cross section of the sample in the main step of forming the multilayer wiring structure taken along a direction parallel to the thickness direction.

【0005】先ず、多層配線構造を形成したい下地11
上に、層間絶縁膜形成用の樹脂として例えば熱硬化性の
樹脂の膜が、例えばスピンコート法やスプレー法などの
好適な方法で形成される。次に、この試料に対し所定の
温度の熱処理がなされ、樹脂で構成される第1層目の層
間絶縁膜13が得られる(図4(A))。ここで、下地
とは例えばセラミック基板、アルミナ基板、或いは半導
体基板などのような多層配線構造を形成したい種々のも
のである。また、層間絶縁膜形成用の樹脂とは、例え
ば、ポリイミド、BCB(ベンゾシクロブテン)、ポリ
キノリン(Maxdem社製)、パイレーン(CNET
社製)、サイトップ(旭硝子製)、テフロンAF(デュ
ポン社製)、PTEF、PFA等種々の好適な樹脂であ
る。
First, the base 11 on which a multilayer wiring structure is desired to be formed
As the resin for forming the interlayer insulating film, for example, a thermosetting resin film is formed thereon by a suitable method such as a spin coating method or a spraying method. Next, this sample is heat-treated at a predetermined temperature to obtain a first-layer interlayer insulating film 13 made of resin (FIG. 4A). Here, the base is various things such as a ceramic substrate, an alumina substrate, or a semiconductor substrate for which a multilayer wiring structure is desired to be formed. The resin for forming the interlayer insulating film is, for example, polyimide, BCB (benzocyclobutene), polyquinoline (manufactured by Maxdem), or pyrene (CNET).
Various resins such as CYTOP (manufactured by Asahi Glass), Teflon AF (manufactured by DuPont), PTEF, and PFA.

【0006】次に、層間絶縁膜13上に導体層15とし
てクロム、銅、チタンまたはアルミニウムなどの好適な
薄膜が好適な方法により形成される(図4(B))。な
お、場合によっては、層間絶縁膜13と導体層15との
密着力を高めるために導体層15を形成する前に層間絶
縁膜13の表面がプラズマや薬品によって処理される場
合もある。
Next, a suitable thin film of chromium, copper, titanium, aluminum or the like is formed as the conductor layer 15 on the interlayer insulating film 13 by a suitable method (FIG. 4 (B)). In some cases, the surface of the interlayer insulating film 13 may be treated with plasma or chemicals before forming the conductor layer 15 in order to increase the adhesion between the interlayer insulating film 13 and the conductor layer 15.

【0007】次に、導体層15上に、この導体層の所定
部分のみを露出する開口17aを有するレジストパター
ン17が公知のリソグラフィ技術により形成される(図
4(C))。
Then, a resist pattern 17 having an opening 17a exposing only a predetermined portion of the conductor layer 15 is formed on the conductor layer 15 by a known lithography technique (FIG. 4C).

【0008】次に、導体層15のレジスト開口17aか
ら露出している部分上に電解めっき或いは無電解めっき
法によりコンタクト配線用の導体膜19いわゆるビヤポ
スト19が形成される(図4(D))。
Next, a conductor film 19 for contact wiring, a so-called via post 19, is formed on the portion of the conductor layer 15 exposed from the resist opening 17a by electrolytic plating or electroless plating (FIG. 4D). .

【0009】次に、レジストパターン17が除去される
(図5(A))。
Next, the resist pattern 17 is removed (FIG. 5A).

【0010】次に、この試料上に再び層間絶縁膜形成用
の熱硬化性の樹脂の膜21が形成され(図5(B))、
さらに、この試料に所定の熱が加えられてこの樹脂膜2
1の硬化が行われる。
Next, a thermosetting resin film 21 for forming an interlayer insulating film is formed again on this sample (FIG. 5B).
Further, a predetermined heat is applied to this sample, so that the resin film 2
1 curing is performed.

【0011】次に、この硬化された樹脂膜が、ビヤポス
ト19の表面が露出されるまで除去されて、第2の層間
絶縁膜21aが得られる(図5(C))。その後、必要
な層数に応じて図4(B)〜図5(C)を用いて説明し
た手順を繰り返すことにより所望の多層配線構造が得ら
れる。
Next, the cured resin film is removed until the surface of the via post 19 is exposed, and the second interlayer insulating film 21a is obtained (FIG. 5C). After that, the desired multilayer wiring structure is obtained by repeating the procedure described with reference to FIGS. 4B to 5C according to the required number of layers.

【0012】[0012]

【発明が解決しようとする課題】しかしながら、上述の
従来の多層配線構造の形成方法では、層間絶縁膜の形成
を、単に樹脂の膜を形成しこの膜を硬化させることで行
っていた。このため、この層間絶縁膜の比誘電率はこの
層間絶縁膜を構成している樹脂が有する比誘電率で決ま
ってしまうので、樹脂を購入し単に使用する側では層間
絶縁膜の比誘電率を制御することが困難であるという問
題点があった。プリント配線基板やICでは、伝送特性
などを向上させるなどの都合上、層間絶縁膜の比誘電率
を変化させたい場合が多々あるので、樹脂で構成される
層間絶縁膜の比誘電率をこの膜の製造段階で制御できる
技術が望まれる。
However, in the above-described conventional method for forming a multilayer wiring structure, the interlayer insulating film is formed by simply forming a resin film and curing the film. Therefore, the relative permittivity of this interlayer insulating film is determined by the relative permittivity of the resin that constitutes this interlayer insulating film. Therefore, on the side of purchasing and simply using the resin, the relative permittivity of the interlayer insulating film is There is a problem that it is difficult to control. In printed wiring boards and ICs, it is often desired to change the relative permittivity of the interlayer insulating film for the purpose of improving the transmission characteristics and the like. A technology that can be controlled at the manufacturing stage is desired.

【0013】この発明はこのような点に鑑みなされたも
のであり、従ってこの発明の目的は樹脂で構成された層
間絶縁膜を有する多層配線構造を形成する際に層間絶縁
膜の比誘電率を製造段階で制御し得る方法を提供するこ
とにある。
The present invention has been made in view of the above circumstances, and therefore an object of the present invention is to improve the relative dielectric constant of an interlayer insulating film when forming a multilayer wiring structure having an interlayer insulating film made of a resin. It is to provide a method that can be controlled at the manufacturing stage.

【0014】[0014]

【課題を解決するための手段】この目的の達成を図るた
め、この発明によれば、樹脂で構成された層間絶縁膜を
有する多層配線構造を形成するに当たり、層間絶縁膜の
形成を以下の(a)〜(c)の工程を含む工程により行
うことを特徴とする。
In order to achieve this object, according to the present invention, in forming a multilayer wiring structure having an interlayer insulating film made of a resin, the formation of the interlayer insulating film is performed as follows. It is characterized in that the steps are carried out including the steps a) to (c).

【0015】(a)層間絶縁膜を形成するための樹脂中
に、該樹脂を硬化させるために後に該樹脂に印加される
エネルギの作用により分解する発泡剤を、混入する工
程。
(A) A step of mixing a foaming agent which is decomposed by the action of energy applied to the resin to cure the resin into the resin for forming the interlayer insulating film.

【0016】(b)該発泡剤を混入させた樹脂の膜を層
間絶縁膜を形成するための下地上に形成する工程。
(B) A step of forming a resin film mixed with the foaming agent on a lower surface for forming an interlayer insulating film.

【0017】(c)該樹脂の膜が形成された下地に前述
のエネルギを加え該樹脂の膜を硬化させると共に該硬化
膜中に前述の発泡剤に起因した空隙を形成する工程。
(C) A step of applying the above-mentioned energy to the underlayer on which the resin film is formed to cure the resin film and form voids due to the foaming agent in the cured film.

【0018】ここで、層間絶縁膜を形成するための樹脂
は、目的とする多層配線構造に適した種々のものとでき
特に限定はされない。例えば、ポリイミド樹脂をはじめ
とする上述の例示樹脂は好適である。
Here, the resin for forming the interlayer insulating film may be various resins suitable for the intended multilayer wiring structure and is not particularly limited. For example, the above-exemplified resins such as polyimide resin are suitable.

【0019】また、樹脂を硬化させるために該樹脂に後
に印加するエネルギは、たとえば熱が好適である。しか
し、場合によっては光など他のエネルギ源でも良い。
Further, the energy to be applied to the resin later to cure the resin is preferably heat, for example. However, other energy sources such as light may be used in some cases.

【0020】また、層間絶縁膜を形成するための下地と
は、層間絶縁膜を形成したい各種の下地であることがで
きる。例えば、ガラスエポキシ基板、セラミックス基
板、ガラス基板、若しくは半導体基板などの種々の基
板、これら基板に1層若しくは何層かの多層配線構造が
既に形成されたものなどである。
Further, the base for forming the interlayer insulating film can be various kinds of bases on which the interlayer insulating film is desired to be formed. For example, various substrates such as a glass epoxy substrate, a ceramics substrate, a glass substrate, or a semiconductor substrate, and those on which one layer or several layers of a multilayer wiring structure have been already formed, etc.

【0021】また、前述の発泡剤としては、これに限定
されないが、例えば芳香族ビスアジド例えばナフトキノ
ンジアジド化合物を挙げることができる。
The above-mentioned foaming agent is not limited to this, but examples thereof include aromatic bisazides such as naphthoquinonediazide compounds.

【0022】[0022]

【作用】この発明の構成によれば、樹脂で構成され、か
つ、内部に空隙を多数有する層間絶縁膜(多孔質状の層
間絶縁膜)が得られる。空隙部分の誘電率は層間絶縁膜
形成用の樹脂の誘電率と異なるから、この発明の方法で
形成された層間絶縁膜の比誘電率は単に樹脂のみで層間
絶縁膜を構成した場合とは異なる値になる。例えば、空
隙内が空気であるとすると、この層間絶縁膜の比誘電率
は樹脂のみで層間絶縁膜を構成した場合より小さくなる
方向に制御できる。また、空隙の大きさや密度により層
間絶縁膜の比誘電率を変えることができ、さらにこの空
隙の密度は、例えば、層間絶縁膜形成用の樹脂への発泡
剤の混合量を調整することにより制御できるので、層間
絶縁膜の比誘電率制御が行える。
According to the structure of the present invention, an interlayer insulating film (porous interlayer insulating film) made of resin and having a large number of voids inside can be obtained. Since the dielectric constant of the void portion is different from the dielectric constant of the resin for forming the interlayer insulating film, the relative dielectric constant of the interlayer insulating film formed by the method of the present invention is different from that in the case where the interlayer insulating film is simply formed of resin. It becomes a value. For example, if the void is air, the relative dielectric constant of the interlayer insulating film can be controlled to be smaller than that in the case where the interlayer insulating film is made of only resin. Further, the relative permittivity of the interlayer insulating film can be changed by the size and density of the voids, and the density of the voids can be controlled by, for example, adjusting the amount of the foaming agent mixed with the resin for forming the interlayer insulating film. Therefore, the relative dielectric constant of the interlayer insulating film can be controlled.

【0023】[0023]

【実施例】以下、図1〜図3を参照してこの発明の多層
配線構造の形成方法の実施例について説明する。なお、
これら図は多層配線構造を形成する工程中の主な工程で
の試料をその厚さ方向と平行な方向に沿って切った断面
で示したものである。しかしながら、これら図はこの発
明を理解できる程度に各構成成分の寸法、形状及び配置
関係を概略的に示してあるにすぎない。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the method for forming a multilayer wiring structure of the present invention will be described below with reference to FIGS. In addition,
These figures show a cross section of the sample in the main step of forming the multilayer wiring structure, taken along a direction parallel to the thickness direction. However, these figures merely show the dimensions, shapes, and positional relationships of the respective constituents to the extent that the present invention can be understood.

【0024】先ず、多層配線構造を形成したい下地例え
ばガラス基板、セラミックス基板などを用意し、これを
有機溶剤等を用い洗浄する。一方、層間絶縁膜を形成す
るための樹脂としてのこの場合ポリイミド樹脂中に、該
樹脂を硬化させるために後に該樹脂に印加されるエネル
ギ(この実施例では熱としている。)の作用により分解
する発泡剤としてのこの場合ナフトキノンジアジド化合
物を、適当量混入しておく。
First, an underlayer on which a multilayer wiring structure is desired to be formed, such as a glass substrate or a ceramic substrate, is prepared and washed with an organic solvent or the like. On the other hand, in this case, the polyimide resin as the resin for forming the interlayer insulating film is decomposed by the action of energy (heat in this embodiment) applied to the resin later to cure the resin. An appropriate amount of naphthoquinonediazide compound in this case as a foaming agent is mixed therein.

【0025】次に、発泡剤を混入させた上記ポリイミド
樹脂を基板上に例えばスピナ、ロールコータ若しくはバ
ーコータなどの好適な装置を用い塗布して、基板31上
に発泡剤33を含有する樹脂の膜35を形成する(図1
(A))。
Next, the above-mentioned polyimide resin mixed with a foaming agent is applied onto a substrate using a suitable device such as a spinner, a roll coater or a bar coater, and a resin film containing the foaming agent 33 is applied onto the substrate 31. 35 (FIG. 1
(A)).

【0026】次に、この樹脂の膜35を硬化させるため
にこの試料を好適な加熱装置を用いて加熱する。この加
熱は、これに限られないが例えば、ハーフキュアと称さ
れる工程(たとえば80〜130℃の温度とされる工
程)と、この工程に続くフルキユアと称される工程(た
とえば200〜450℃の温度とされる工程)とにより
行える。ナフトキノンジアジド化合物は140℃以上に
加熱すると分解し窒素(N2 )ガスを発することが知ら
れている。そして、ポリイミド樹脂を硬化させる温度
は、上述のごとく200〜450℃の高温を含むので、
ナフトキノンジアジド化合物がN2 ガスを発する温度に
比べ充分高い。このため、ポリイミド樹脂の膜35を硬
化させるための工程ではこの膜35中のナフトキノンジ
アジド化合物がN2 ガスを発するのでこの影響でこのポ
リイミド樹脂の膜35が発泡し、この結果、空隙37a
を有する層間絶縁膜37が得られる(図1(B))。こ
こで、層間絶縁膜37中の空隙37aの密度(数)によ
りこの層間絶縁膜37の比誘電率を変えられる。そし
て、空隙37aの密度(数)は、樹脂へのナフトキノン
ジアジド化合物の添加量で調整できる。
Next, the sample is heated using a suitable heating device in order to cure the resin film 35. Although this heating is not limited to this, for example, a step called half cure (for example, a step at a temperature of 80 to 130 ° C.) and a step called Frucure that follows this step (for example, 200 to 450 ° C.). The temperature is set to the above step). It is known that a naphthoquinonediazide compound decomposes when heated to 140 ° C. or higher and emits nitrogen (N 2 ) gas. And since the temperature for curing the polyimide resin includes the high temperature of 200 to 450 ° C. as described above,
The temperature of the naphthoquinonediazide compound is sufficiently higher than the temperature at which N 2 gas is emitted. Therefore, in the step of curing the polyimide resin film 35, the naphthoquinonediazide compound in the film 35 emits N 2 gas, which causes the polyimide resin film 35 to foam, resulting in the voids 37a.
The inter-layer insulating film 37 having the above is obtained (FIG. 1B). Here, the relative permittivity of the interlayer insulating film 37 can be changed by the density (number) of the voids 37a in the interlayer insulating film 37. The density (number) of the voids 37a can be adjusted by the amount of the naphthoquinonediazide compound added to the resin.

【0027】次に、層間絶縁膜37の表面を平坦化する
目的で、この層間絶縁膜37上に、今度は層間絶縁膜形
成用の樹脂(説明上、平坦化用樹脂ともいう。)のみ
(ナフトキノンジアジド化合物を含まないもの)を好適
な方法で塗布し、ついで、これを熱硬化させ平坦化層3
9を得る(図1(C))。この平坦化層39は勿論、層
間絶縁膜の一部を構成する。ただし、層間絶縁膜37の
表面が実用上問題の無い平坦性を有している場合はこの
平坦化層39は必ずしも設ける必要はない。反面、平坦
化用樹脂の塗布では平坦化ができないような場合は、研
磨処理やエッチバック処理を実施するのが良い。
Next, for the purpose of flattening the surface of the interlayer insulating film 37, only the resin for forming the interlayer insulating film (also referred to as a planarizing resin for the sake of explanation) is formed on the interlayer insulating film 37 (this time also). Naphthoquinonediazide compound-free) is applied by a suitable method, and then this is heat-cured to flatten the flattening layer 3
9 is obtained (FIG. 1 (C)). The flattening layer 39, of course, constitutes a part of the interlayer insulating film. However, if the surface of the interlayer insulating film 37 has a flatness that causes no practical problem, the planarizing layer 39 is not necessarily provided. On the other hand, when flattening cannot be achieved by applying the flattening resin, it is preferable to carry out a polishing process or an etch-back process.

【0028】次に、層間絶縁膜37上(平坦化層39を
設けた場合はこの上)に、導体層(図示せず)としてク
ロム、銅、チタンまたはアルミニウムなどの好適な薄膜
を蒸着法、スパッタ法等の好適な方法で形成する。な
お、場合によっては、層間絶縁膜37とこの導体層との
密着力を高めるために導体層を形成する前に層間絶縁膜
37の表面をプラズマや薬品によって処理しても良い。
次に、この導体層の形成された試料上にこの導体層の所
定部分のみを露出する開口を有するレジストパターン
(図示せず)を形成する。次に、この導体層のレジスト
開口から露出している部分上に電解めっき或いは無電解
めっき法により金属膜を形成し下側配線41を得る(図
1(D))。次に、下側配線41形成済みの試料上に下
側配線41の所定部分のみを露出する開口43aを有す
るレジストパターン43を公知のリソグラフィ技術によ
り形成する(図1(D))。
Next, a suitable thin film of chromium, copper, titanium, aluminum or the like is formed as a conductor layer (not shown) on the interlayer insulating film 37 (on which the flattening layer 39 is provided) by a vapor deposition method, It is formed by a suitable method such as a sputtering method. In some cases, the surface of the interlayer insulating film 37 may be treated with plasma or chemicals before forming the conductor layer in order to increase the adhesion between the interlayer insulating film 37 and the conductor layer.
Next, a resist pattern (not shown) having an opening exposing only a predetermined portion of the conductor layer is formed on the sample on which the conductor layer is formed. Next, a metal film is formed on the portion of the conductor layer exposed from the resist opening by electrolytic plating or electroless plating to obtain the lower wiring 41 (FIG. 1D). Next, a resist pattern 43 having an opening 43a exposing only a predetermined portion of the lower wiring 41 is formed on the sample on which the lower wiring 41 has been formed by a known lithography technique (FIG. 1D).

【0029】次に、配線形成用の薄膜41のレジスト開
口43aから露出している部分上に電解めっき或いは無
電解めっき法によりコンタクト配線用の導体膜45いわ
ゆるビヤポスト45を形成する(図2(A))。次に、
レジストパターン43を除去する(図2(B))。
Next, a conductor film 45 for contact wiring, a so-called via post 45, is formed on the portion of the wiring forming thin film 41 exposed from the resist opening 43a by electrolytic plating or electroless plating (see FIG. 2A). )). next,
The resist pattern 43 is removed (FIG. 2 (B)).

【0030】次に、この試料上に発泡剤35を含有させ
た層間絶縁膜形成用の樹脂の膜35を再び例えば図1
(A)を用い説明した方法により形成する(図2
(C))。
Next, a resin film 35 for forming an interlayer insulating film containing a foaming agent 35 is again formed on this sample, for example, as shown in FIG.
It is formed by the method described with reference to FIG.
(C)).

【0031】次に、例えば図2(B)を用い説明した方
法によりこの樹脂の膜35を硬化させると共に発泡させ
て空隙37aを形成する(図3(A))。
Next, the resin film 35 is cured and foamed by the method described with reference to FIG. 2B to form the void 37a (FIG. 3A).

【0032】次に、必要に応じ図1(C)を用い説明し
た方法により平坦化層(図示せず)を形成し、次に、こ
の試料表面を、ビヤポスト45の表面が露出されるまで
エッチングする。これにより空隙37aを有する層間絶
縁膜47が得られる(図3(B))。
Next, if necessary, a planarizing layer (not shown) is formed by the method described with reference to FIG. 1C, and then the sample surface is etched until the surface of the via post 45 is exposed. To do. As a result, the interlayer insulating film 47 having the void 37a is obtained (FIG. 3B).

【0033】次に、この層間絶縁膜47上に上側配線形
成用の薄膜たとえばクロム、金、或いは銅などの薄膜
(図示せず)を好適な方法により形成し、さらにこの薄
膜を公知の方法によりパターニングして上側配線49を
得る(図3(C))。
Next, a thin film (not shown) such as chromium, gold, or copper for forming the upper wiring is formed on the interlayer insulating film 47 by a suitable method, and the thin film is formed by a known method. The upper wiring 49 is obtained by patterning (FIG. 3C).

【0034】その後、必要な層数に応じて図1(D)〜
図3(C)を用いて説明した手順を繰り返すことにより
所望の多層配線構造が得られる。
Then, depending on the required number of layers, the process shown in FIG.
By repeating the procedure described with reference to FIG. 3C, a desired multilayer wiring structure can be obtained.

【0035】上述においてはこの発明の多層配線構造の
実施例について説明したがこの発明は上述の実施例に限
られない。たとえば、下側配線や上側配線の形成手順は
単なる例示にすぎない。また、多層配線の構造も単なる
例示にすぎない。
Although the embodiments of the multilayer wiring structure of the present invention have been described above, the present invention is not limited to the above embodiments. For example, the procedure for forming the lower wiring and the upper wiring is merely an example. Moreover, the structure of the multilayer wiring is merely an example.

【0036】[0036]

【発明の効果】上述した説明から明らかなようにこの発
明によれば、樹脂で構成され、かつ、内部に空隙を多数
有する多孔質状の層間絶縁膜を、多層配線構造の形成途
中で形成できる。したがって、単に樹脂のみで層間絶縁
膜を構成する場合とは異なる比誘電率の層間絶縁膜が容
易に得られる。しかも、層間絶縁膜形成用の樹脂への発
泡剤の混合量を調整することにより比誘電率を制御でき
るので、層間絶縁膜の比誘電率制御が行える。このた
め、所望の比誘電率の層間絶縁膜が得やすくなるので電
子装置やICにおける伝送特性の向上が期待できる。
As is apparent from the above description, according to the present invention, a porous interlayer insulating film made of resin and having a large number of voids inside can be formed during the formation of a multilayer wiring structure. . Therefore, it is possible to easily obtain an interlayer insulating film having a relative dielectric constant different from that of the case where the interlayer insulating film is made of only resin. Moreover, since the relative permittivity can be controlled by adjusting the mixing amount of the foaming agent in the resin for forming the interlayer insulating film, the relative permittivity of the interlayer insulating film can be controlled. Therefore, an interlayer insulating film having a desired relative permittivity can be easily obtained, so that improvement in transmission characteristics in electronic devices and ICs can be expected.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例の説明に供する工程図である。FIG. 1 is a process drawing for explaining an example.

【図2】実施例の説明に供する図1に続く工程図であ
る。
FIG. 2 is a process chart following FIG. 1 for explaining an example.

【図3】実施例の説明に供する図2に続く工程図であ
る。
FIG. 3 is a process chart following FIG. 2 for explaining the embodiment.

【図4】従来技術の説明に供する工程図である。FIG. 4 is a process diagram for explaining the conventional technique.

【図5】従来技術の説明に供する図4に続く工程図であ
る。
FIG. 5 is a process chart following FIG. 4 for explaining the conventional technique.

【符号の説明】[Explanation of symbols]

31:基板 33:発泡剤 35:層間絶縁膜形成用樹脂の膜 37,47:空隙を有する層間絶縁膜 37a:空隙 41:下側配線 45:ビヤポスト 49:上側配線 31: Substrate 33: Foaming Agent 35: Interlayer Insulating Film Forming Resin Film 37, 47: Interlayer Insulating Film Having Voids 37a: Voids 41: Lower Wiring 45: Beer Post 49: Upper Wiring

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H05K 1/03 E 7011−4E ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H05K 1/03 E 7011-4E

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 樹脂で構成された層間絶縁膜を有する多
層配線構造を形成するに当たり、 層間絶縁膜の形成を以下の(a)〜(c)の工程を含む
工程により行うことを特徴とする多層配線構造の形成方
法。 (a)層間絶縁膜を形成するための樹脂中に、該樹脂を
硬化させるために後に該樹脂に印加されるエネルギの作
用により分解する発泡剤を、混入する工程。 (b)該発泡剤を混入させた樹脂の膜を層間絶縁膜を形
成するための下地上に形成する工程。 (c)該樹脂の膜が形成された下地に前記エネルギを加
え該樹脂の膜を硬化させると共に該硬化膜中に前記発泡
剤に起因した空隙を形成する工程。
1. When forming a multilayer wiring structure having an interlayer insulating film made of resin, the interlayer insulating film is formed by steps including the following steps (a) to (c): Method for forming multi-layer wiring structure. (A) A step of mixing a foaming agent that is decomposed by the action of energy applied to the resin to cure the resin into the resin for forming the interlayer insulating film. (B) A step of forming a resin film mixed with the foaming agent on a lower surface for forming an interlayer insulating film. (C) A step of applying the energy to the underlayer on which the resin film is formed to cure the resin film and form voids due to the foaming agent in the cured film.
【請求項2】 請求項1に記載の多層配線構造の形成方
法において、 前記発泡剤をナフトキノンジアジド化合物としたことを
特徴とする多層配線構造の形成方法。
2. The method for forming a multilayer wiring structure according to claim 1, wherein the foaming agent is a naphthoquinonediazide compound.
JP6861793A 1993-03-26 1993-03-26 Forming method for multilayer interconnection structure Withdrawn JPH06283864A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6861793A JPH06283864A (en) 1993-03-26 1993-03-26 Forming method for multilayer interconnection structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6861793A JPH06283864A (en) 1993-03-26 1993-03-26 Forming method for multilayer interconnection structure

Publications (1)

Publication Number Publication Date
JPH06283864A true JPH06283864A (en) 1994-10-07

Family

ID=13378905

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6861793A Withdrawn JPH06283864A (en) 1993-03-26 1993-03-26 Forming method for multilayer interconnection structure

Country Status (1)

Country Link
JP (1) JPH06283864A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6194029B1 (en) 1998-02-12 2001-02-27 Matsushita Electric Industrial Co., Ltd. Method of forming porous film and material for porous film
JP2002280692A (en) * 2001-03-22 2002-09-27 Hitachi Chem Co Ltd Method for manufacturing double-sided board having connecting conductor with metal thin film layer
US7264482B2 (en) 2004-03-10 2007-09-04 J.S.T. Mfg. Co., Ltd. Anisotropic conductive sheet
JP2008060270A (en) * 2006-08-30 2008-03-13 Fujitsu Ltd Electronic device, and its manufacturing method
JP2021034485A (en) * 2019-08-21 2021-03-01 株式会社デンソー Semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6194029B1 (en) 1998-02-12 2001-02-27 Matsushita Electric Industrial Co., Ltd. Method of forming porous film and material for porous film
US6319854B1 (en) 1998-02-12 2001-11-20 Matsushita Electric Industrial Co., Ltd. Method of forming porous film and material for porous film
JP2002280692A (en) * 2001-03-22 2002-09-27 Hitachi Chem Co Ltd Method for manufacturing double-sided board having connecting conductor with metal thin film layer
US7264482B2 (en) 2004-03-10 2007-09-04 J.S.T. Mfg. Co., Ltd. Anisotropic conductive sheet
JP2008060270A (en) * 2006-08-30 2008-03-13 Fujitsu Ltd Electronic device, and its manufacturing method
JP2021034485A (en) * 2019-08-21 2021-03-01 株式会社デンソー Semiconductor device

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