WO2018186131A1 - Dispositif semi-conducteur - Google Patents

Dispositif semi-conducteur Download PDF

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Publication number
WO2018186131A1
WO2018186131A1 PCT/JP2018/009849 JP2018009849W WO2018186131A1 WO 2018186131 A1 WO2018186131 A1 WO 2018186131A1 JP 2018009849 W JP2018009849 W JP 2018009849W WO 2018186131 A1 WO2018186131 A1 WO 2018186131A1
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WO
WIPO (PCT)
Prior art keywords
separation
surface electrode
electrode
semiconductor chip
film
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PCT/JP2018/009849
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English (en)
Japanese (ja)
Inventor
正範 大島
英二 林
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株式会社デンソー
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Publication of WO2018186131A1 publication Critical patent/WO2018186131A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present disclosure relates to a semiconductor device having a surface electrode formed on the surface of a semiconductor substrate and a back electrode formed on the back surface.
  • a semiconductor device having a surface electrode formed on the surface of a semiconductor substrate and a back electrode formed on the back surface is known.
  • the thickness of the semiconductor substrate has been reduced in order to reduce the loss.
  • the structure such as the film thickness is different between the front electrode and the back electrode.
  • the semiconductor device may be warped due to the thin plate and the difference in the bimetal effect between the front and back sides.
  • the surface electrode to be soldered is divided into a plurality of parts in both the row direction and the column direction perpendicular to the plate thickness direction by a protective film in order to reduce warpage. .
  • the protective film is formed using a hygroscopic material such as polyimide.
  • a hygroscopic material such as polyimide.
  • This disclosure is intended to provide a semiconductor device that can effectively suppress the generation of voids in solder on a surface electrode while reducing warpage.
  • a semiconductor device includes a semiconductor substrate having a front surface and a back surface opposite to the front surface in the plate thickness direction, on which elements are formed, and provided on the front surface and soldered.
  • a protection formed using a hygroscopic material having a first separation part that divides the surface electrode in the column direction and a second separation part that extends in the column direction in the region and divides the surface electrode in the row direction A film, and a back electrode provided on the back surface.
  • the first separation part and the second separation part are provided apart from each other so as not to cross each other.
  • the protective film has the first separation portion extending in the row direction and the second separation portion extending in the column direction, and the surface electrode is thereby separated, the warp of the semiconductor device is reduced. Can be reduced.
  • the protective film does not have an intersection between the first separation part and the second separation part, the retention of water vapor generated by moisture absorption of the protective film is suppressed, and consequently, the generation of voids in the solder on the surface electrode is suppressed. can do.
  • a semiconductor device has a front surface and a back surface opposite to the front surface in the thickness direction, and is provided with a semiconductor substrate on which elements are formed, and is soldered.
  • a surface electrode, a peripheral portion provided around the surface electrode on the surface, and a column extending in a row direction orthogonal to the plate thickness direction in a region surrounded by the peripheral portion and orthogonal to the plate thickness direction and the row direction A first separation portion that divides the surface electrode in the direction, a second separation portion that extends in the column direction in the region and divides the surface electrode in the row direction, and an intersection of the first separation portion and the second separation portion
  • the first separation part and the second separation part are provided apart from the peripheral part so as not to be connected to the peripheral part.
  • the protective film has the first separation portion extending in the row direction and the second separation portion extending in the column direction, and the surface electrode is thereby separated, the warp of the semiconductor device is reduced. Can be reduced.
  • the protective film has a crossing portion, the first separation portion and the second separation portion are provided apart from the surrounding portion. Thereby, it can suppress that the water
  • FIG. 5 It is a top view for demonstrating void generation in a comparative example. It is sectional drawing which follows the XX line of FIG. 5 for demonstrating void generation
  • the thickness direction of the semiconductor substrate is referred to as the Z direction.
  • a direction perpendicular to the Z direction and the extending direction of the first separation portion is indicated as an X direction.
  • the direction orthogonal to both the Z direction and the X direction, that is, the extending direction of the second separation portion is indicated as the Y direction.
  • the shape along the XY plane is a planar shape.
  • the semiconductor module 10 includes a semiconductor chip 12, a sealing resin body 14, a signal terminal 18, a terminal 22, a heat sink 26, a main terminal 28, a heat sink 32, and a main terminal 34.
  • a semiconductor module 10 is used for a main inverter of a hybrid vehicle or an electric vehicle, for example.
  • the semiconductor module 10 includes one semiconductor chip 12.
  • the semiconductor module 10 constitutes one of six arms constituting a three-phase inverter. Since such a semiconductor module 10 includes one arm in the package, it is also referred to as a 1 in 1 package.
  • the semiconductor chip 12 is formed with an element in which a current flows in the Z direction which is the thickness direction, a so-called vertical element.
  • the semiconductor chip 12 corresponds to a semiconductor device. MOSFET, IGBT, etc. are employable as a vertical element.
  • the semiconductor chip 12 has electrodes on both sides in the Z direction.
  • a pad for the signal terminal 18 is provided on one surface.
  • the sealing resin body 14 is made of, for example, an epoxy resin.
  • the sealing resin body 14 is formed by transfer molding.
  • the sealing resin body 14 has a substantially rectangular planar shape.
  • the sealing resin body 14 has one surface 14a orthogonal to the Z direction, a back surface 14b opposite to the one surface 14a, and side surfaces.
  • the one surface 14a and the back surface 14b are flat surfaces, for example.
  • the sealing resin body 14 seals the semiconductor chip 12.
  • a signal terminal 18 is connected to a pad (a pad 129 described later) of the semiconductor chip 12 through a bonding wire 16.
  • the signal terminal 18 extends in the Y direction, and protrudes to the outside from one side surface 14 c of the sealing resin body 14. Thereby, the signal terminal 18 can be electrically connected to an external device.
  • the signal terminal 18 may be formed integrally with the heat sink 32 as a part of the lead frame, or the signal terminal 18 of another member may be connected to the heat sink 32.
  • a terminal 22 is connected to one electrode (surface electrode 121 described later) of the semiconductor chip 12 via a solder 20.
  • the terminal 22 is interposed between the semiconductor chip 12 and the heat sink 26.
  • the terminal 22 transfers heat generated by the semiconductor chip 12 to the heat sink 26.
  • the terminal 22 electrically relays the semiconductor chip 12 and the heat sink 26.
  • the terminal 22 is formed using a metal material (for example, Cu) in order to ensure thermal conductivity and electrical conductivity.
  • the terminal 22 has a substantially rectangular parallelepiped shape.
  • a heat sink 26 is connected to the surface of the terminal 22 opposite to the semiconductor chip 12 via a solder 24.
  • the heat sink 26 radiates heat generated by the semiconductor chip 12 to the outside of the semiconductor module 10.
  • the heat sink 26 electrically relays the semiconductor chip 12 and the main terminal 28.
  • the heat sink 26 is formed using a metal material (for example, Cu) having excellent thermal conductivity and electrical conductivity.
  • the surface of the heat sink 26 opposite to the terminal 22 is a heat radiating surface 26 a exposed from the one surface 14 a of the sealing resin body 14.
  • the one surface 14a and the heat radiation surface 26a are substantially flush.
  • the surface facing the terminal 22 and the side surface connecting the facing surface and the heat radiating surface 26 a are covered with the sealing resin body 14.
  • a main terminal 28 is connected to the heat sink 26.
  • the main terminal 28 is electrically connected to the semiconductor chip 12 via the terminal 22 and the heat sink 26.
  • the main terminal 28 extends from the heat sink 26 in the Y direction and on the side opposite to the signal terminal 18.
  • the main terminal 28 projects outward from a side surface 14d opposite to the side surface 14c from which the signal terminal 18 projects. Thereby, the main terminal 28 can be electrically connected to an external device.
  • the main terminal 28 may be formed integrally with the heat sink 26 as a part of the lead frame, or a separate main terminal 28 may be connected to the heat sink 26.
  • a heat sink 32 is connected to the other electrode of the semiconductor chip 12 (a back electrode 130 described later) via a solder 30. Like the heat sink 26, the heat sink 32 radiates the heat generated by the semiconductor chip 12 to the outside of the semiconductor module 10. The heat sink 32 electrically relays the semiconductor chip 12 and the main terminal 34.
  • the heat sink 32 is also formed using a metal material (for example, Cu) excellent in thermal conductivity and electrical conductivity.
  • a surface of the heat sink 32 opposite to the semiconductor chip 12 is a heat radiating surface 32 a exposed from the back surface 14 b of the sealing resin body 14.
  • the back surface 14b and the heat dissipation surface 32a are substantially flush.
  • the surface facing the semiconductor chip 12 and the side surface connecting the facing surface and the heat radiating surface 32 a are covered with the sealing resin body 14.
  • the main terminal 34 is connected to the heat sink 32.
  • the main terminal 34 is electrically connected to the semiconductor chip 12 via the heat sink 32.
  • the main terminal 34 extends from the heat sink 32 in the Y direction and on the same side as the main terminal 28.
  • the main terminal 34 protrudes from the same side surface 14 d as the main terminal 28. Thereby, the main terminal 34 can be electrically connected to an external device.
  • the main terminal 34 may be formed integrally with the heat sink 32 as a part of the lead frame, or a separate main terminal 34 may be connected to the heat sink 32. In a plan view from the Z direction, the main terminals 28 and 34 are arranged side by side in the X direction.
  • the semiconductor chip 12 configured as described above, the semiconductor chip 12, the bonding wire 16, a part of the signal terminal 18, the solder 20, 24, 30, the terminal 22, the part of the heat sink 26, the part of the main terminal 28, the heat sink.
  • a part of 32 and a part of the main terminal 34 are sealed with the sealing resin body 14.
  • heat sinks 26 and 32 are disposed on both sides of the semiconductor chip 12, and heat can be radiated to the outside by the heat radiating surfaces 26a and 32a.
  • semiconductor chip 12 semiconductor device
  • the semiconductor chip 12 includes a semiconductor substrate 120, a surface electrode 121, a protective film 125, a pad 129, and a back electrode 130.
  • the front electrode 121 and the back electrode 130 correspond to the above-described double-sided electrodes.
  • the semiconductor substrate 120 is made of a known semiconductor material such as Si (silicon) or SiC (silicon carbide).
  • the above-described vertical element is formed on the semiconductor substrate 120.
  • an n-channel IGBT and an FWD (commutation diode) connected in reverse parallel to the IGBT are formed on a semiconductor substrate 120 made of Si. That is, RC-IGBT is formed on the semiconductor substrate 120. Note that the IGBT and the FWD can be formed on different semiconductor substrates.
  • the semiconductor substrate 120 has a substantially rectangular planar shape.
  • the semiconductor substrate 120 has a front surface 120a and a back surface 120b opposite to the front surface 120a in the Z direction.
  • an IGBT emitter region, a trench gate, an FWD anode region, and the like are formed in the active region (main region).
  • the active area has a substantially rectangular shape in plan view.
  • a breakdown voltage structure such as a guard ring is formed in the outer peripheral region surrounding the active region.
  • an IGBT collector region and an FWD cathode region are formed on the surface layer on the back surface 120b side.
  • a surface electrode 121, a protective film 125, and a pad 129 are formed on the surface 120 a of the semiconductor substrate 120.
  • the surface electrode 121 is formed corresponding to the active region.
  • the surface electrode 121 is an electrode that is electrically connected to the emitter region and the anode region. For this reason, the surface electrode 121 is also referred to as an emitter electrode.
  • the surface electrode 121 not only functions as an emitter electrode but also functions as an anode electrode of the FWD.
  • the front electrode 121 is also referred to as a main electrode because a current flows between the front electrode 121 and the back electrode 130.
  • the surface electrode 121 is formed on one end side in the Y direction in the semiconductor substrate 120 having a substantially rectangular plane.
  • the surface electrode 121 has a base film 122 and a metal thin film.
  • the base film 122 is formed using a material whose main component is Al (aluminum).
  • the base film 122 is formed by sputtering using AlSi as a material.
  • the thickness of the base film 122 is 5 ⁇ m, for example.
  • a metal thin film is formed on the base film 122 for the purpose of improving the bonding strength with the solder 20 and improving the wettability with respect to the solder 20.
  • a Ni film 123 and an Au film 124 are provided as metal thin films.
  • the Ni film 123 is formed using a material mainly composed of Ni (nickel). When Ni is used, for example, the bonding strength with the solder 20 can be improved.
  • the Ni film 123 is a plating film.
  • the electroless Ni plating film contains P (phosphorus) in addition to Ni as the main component.
  • the thickness of the Ni film 123 is, for example, 5 ⁇ m.
  • the Au film 124 is formed using a material whose main component is Au (gold). When Au is used, for example, wettability with the solder 20 can be improved. In the present embodiment, the Au film 124 is a plating film. The thickness of the Au film 124 is, for example, less than 1 ⁇ m (nm order). Thus, the surface electrode 121 has a multilayer film structure.
  • the protective film 125 is formed using a hygroscopic material such as polyimide.
  • the protective film 125 includes a peripheral portion 126, a first separation portion 127, and a second separation portion 128.
  • the peripheral portion 126 is provided on the surface 120a so as to surround the surface electrode 121.
  • the peripheral portion 126 is provided on the outer peripheral region so as to surround the active region.
  • the peripheral portion 126 has a rectangular ring shape.
  • the thickness of the portion without the base film 122 for example, the thickness of the peripheral portion 126, is substantially equal to the thickness of the laminated portion of the base film 122, the Ni film 123, and the Au film 124 in the surface electrode 121.
  • the first separation unit 127 and the second separation unit 128 are provided in a region surrounded by the peripheral portion 126, that is, in an active region.
  • the first separation unit 127 extends along the X direction, which is a first direction orthogonal to the Z direction.
  • the X direction corresponds to the row direction.
  • the protective film 125 has a plurality of first separators 127.
  • the inner peripheral surface of the peripheral portion 126 has a substantially rectangular planar shape.
  • the peripheral portion 126 has a pair of surfaces (hereinafter referred to as a first surface) orthogonal to the X direction and a pair of surfaces (hereinafter referred to as a second surface) orthogonal to the Y direction as inner peripheral surfaces. is doing.
  • the length between the first surfaces (opposite distance) is longer than the length between the second surfaces (opposite distance). That is, the inner peripheral surface has the X direction as the long direction and the Y direction as the short direction.
  • the first separation portion 127 is continuous with the inner peripheral surface of the peripheral portion 126.
  • the first separation part 127 extends from each of the first surfaces. Specifically, two first separation portions 127 are extended from each of the first surfaces. In the plurality of first separation portions 127, the extending lengths from the first surface are substantially equal to each other. The extended length is shorter than 1 ⁇ 2 of the length (opposite distance) between the pair of first surfaces.
  • the first separator 127 divides the surface electrode 121 in the Y direction, which is the second direction orthogonal to the Z direction.
  • the Y direction corresponds to the column direction.
  • the surface electrode 121 is divided into substantially equal lengths in the Y direction by two first separation portions 127 that are continuous with the same first surface. That is, the surface electrode 121 is divided into three equal parts by the first separator 127.
  • the first separation unit 127 is separated into two in the X direction.
  • the first separation portion 127 is provided on the base film 122, and the Ni film 123 and the Au film 124 that are metal thin films are separated by the first separation portion 127.
  • the second separation unit 128 extends along the Y direction.
  • the protective film 125 has one second separation unit 128.
  • the second separation part 128 is also connected to the inner peripheral surface of the peripheral part 126.
  • the second separation unit 128 extends from the second surface.
  • the second separation unit 128 is provided so as to straddle the second surface.
  • the extending length of the second separation portion 128 is substantially equal to the length (opposite distance) between the pair of second surfaces.
  • the second separator 128 divides the surface electrode 121 in the X direction.
  • the surface electrodes 121 are partitioned by the second separator 128 into substantially equal lengths in the X direction. That is, the surface electrode 121 is divided into two equal parts by the second separator 128.
  • the second separation portion 128 is also provided on the base film 122, and the Ni film 123 and the Au film 124 that are metal thin films are separated by the second separation portion 128.
  • the second separation unit 128 is provided in the center of the active region in the X direction.
  • Each first separation unit 127 is provided apart from the second separation unit 128 so as not to intersect the second separation unit 128, that is, not to be connected to the second separation unit 128.
  • the surface electrode 121 (metal thin film) has two-fold symmetry around the center 121a.
  • the protective film 125 has a predetermined gap between the second separator 128 and each first separator 127 in the X direction.
  • the Ni film 123 and the Au film 124 that are metal thin films are also disposed in the gap, that is, the region where the first separation portion 127 and the second separation portion 128 are opposed to each other.
  • This opposing region is a first connecting portion 121b that connects portions separated by the first separating portion 127 in the surface electrode 121.
  • the surface electrode 121 has four first connecting portions 121b.
  • the pad 129 is an electrode to which the signal terminal 18 is electrically connected.
  • the pad 129 also has a multilayer structure similar to that of the surface electrode 121.
  • the pad 129 is formed at a position different from the surface electrode 121 on the surface 120a.
  • the pad 129 is electrically separated from the surface electrode 121.
  • the pad 129 is formed at the end on the opposite side of the surface electrode 121 formation region in the Y direction.
  • the semiconductor chip 12 has five pads 129.
  • the pad 129 the potential of the anode potential of the temperature sensor (temperature-sensitive diode) for detecting the temperature of the semiconductor substrate 120, the cathode potential, the gate electrode, the current sense, and the potential of the surface electrode 121 (emitter electrode) are similarly used. It has a Kelvin emitter for detection.
  • the cathode potential, anode potential, gate electrode, current sense, and Kelvin emitter are formed in this order from one end side.
  • the five pads 129 are collectively formed on one end side in the Y direction and formed side by side in the X direction on the substantially rectangular planar semiconductor substrate 120. Each pad 129 is surrounded by a peripheral portion 126.
  • a back electrode 130 is formed on the back surface 120 b of the semiconductor substrate 120.
  • the back electrode 130 is an electrode that is electrically connected to the collector region and the cathode region. For this reason, the back electrode 130 is also referred to as a collector electrode.
  • the back electrode 130 not only functions as a collector electrode, but also serves as an FWD cathode electrode.
  • a current flows between the surface electrode 121 and the surface electrode 121, it is also called a main electrode.
  • the back electrode 130 is formed on almost the entire back surface 120b.
  • the back electrode 130 also has a multilayer structure.
  • the back electrode 130 also has a base film and a metal thin film.
  • the base film is made of AlSi and is formed by sputtering.
  • the metal thin film includes a Ni film and an Au film.
  • the Ni film is formed by sputtering.
  • the Au film is a plating film.
  • the thickness of the Ni film on the back electrode 130 is made thinner than the thickness of the Ni film 123 on the front electrode 121. Thereby, the thickness of the back electrode 130 is made thinner than the thickness of the front electrode 121 (thickness of the laminated portion).
  • each element constituting the semiconductor module 10 is prepared. That is, the semiconductor chip 12, the signal terminal 18, the terminal 22, the heat sink 26 connected with the main terminal 28, and the heat sink 32 connected with the main terminal 34 are prepared.
  • the semiconductor chip 12 having the surface electrode 121 and the protective film 125 described above is prepared.
  • the semiconductor chip 12 is disposed on the opposite surface of the heat sink 32 via the solder 30.
  • the semiconductor chip 12 is arranged so that the back electrode 130 faces the heat sink 32.
  • the terminal 22 in which the solders 20 and 24 are arranged on both sides in advance as the incoming solder is arranged so that the solder 20 is on the semiconductor chip 12 side.
  • the quantity which can absorb the height variation in the semiconductor module 10 is arrange
  • the solder 20, 24, 30 is reflowed (1st reflow), thereby connecting the back electrode 130 of the semiconductor chip 12 and the heat sink 32 via the solder 30. Further, the surface electrode 121 of the semiconductor chip 12 and the terminal 22 are connected via the solder 20. Since there is no heat sink 26 to be connected yet, the solder 24 has a shape that rises with the center of the surface facing the heat sink 26 as a vertex due to surface tension.
  • the pads 129 of the semiconductor chip 12 and the signal terminals 18 are connected by the bonding wires 16.
  • a connection body in which the semiconductor chip 12, the signal terminal 18, the terminal 22, and the heat sink 32 are integrated is obtained.
  • connection body and the heat sink 26 are connected via the solder 24.
  • the heat sink 26 is disposed on a pedestal (not shown) so that the surface facing the terminal 22 faces up.
  • a connection body is arrange
  • the load of the heat sink 26 is applied so that the height of the semiconductor module 10 becomes a predetermined height.
  • a spacer (not shown) is disposed between the heat sink 26 and the base, and the spacer is brought into contact with both the heat sink 26 and the base. In this way, the height of the semiconductor module 10 is set to a predetermined height.
  • the sealing resin body 14 is molded by a transfer mold method.
  • the sealing resin body 14 is molded so that the heat sinks 26 and 32 are completely covered. Then, by cutting the molded sealing resin body 14 together with a part of the heat sinks 26 and 32, the heat radiation surfaces 26a and 32a of the heat sinks 26 and 32 are exposed.
  • the sealing resin body 14 may be molded in a state where the heat radiation surfaces 26a and 32a of the heat sinks 26 and 32 are pressed against and adhered to the cavity wall surface of the molding die. In this case, when the sealing resin body 14 is molded, the heat radiation surfaces 26 a and 32 a are exposed from the sealing resin body 14. For this reason, the cutting after shaping
  • the semiconductor module 10 can be obtained by removing unnecessary portions of the lead frame.
  • FIG. 6 shows a result of inspecting a solder void by an ultrasonic flaw detector (SAT: Scanning Acoustic Tomograph) from the Z direction in a soldered state, that is, in a semiconductor module state.
  • FIG. 10 shows a simplified structure of the semiconductor chip 12.
  • r is added to the end of the reference numerals of the related elements in the present embodiment. 9 to 12, the flow of water vapor during reflow is indicated by arrows.
  • the inventor made a prototype of the semiconductor chip 12r having the configuration shown in FIG.
  • the first separation portion 127r extends along the X direction so as to straddle the first surface of the peripheral portion 126r, and intersects the second separation portion 128r near the center in the X direction.
  • the protective film 125r has an intersecting portion 131r formed by intersecting the first separating portion 127r and the second separating portion 128r. Other points are the same as in the present embodiment (see FIG. 2).
  • the first separation portion 127r and the second separation portion 128r provided in the peripheral portion 126r have lower wettability with respect to the solder 20r than the surface electrode 121r. Therefore, during reflow, the solder 20r does not wet and spread on the first separation portion 127r and the second separation portion 128r, and the non-wetting portion 36r is formed as shown in FIGS.
  • the non-wetting portion 36r is formed at the interface between the solder 20r, the first separation portion 127r, the second separation portion 128r, and the solder 20r.
  • the non-wetting portion 36r is a portion where the solder 20r can be pulled without getting wet. This non-wetting part 36r was confirmed by SAT.
  • the non-wetting portion 36r is confirmed in the configuration in which the surface electrode 121r is separated by the protective film 125r.
  • a void 38r may occur in the solder 20r.
  • the void 38r was generated in the solder 20r at the intersecting portion 131 and the portion directly above the periphery.
  • the void 38r is formed including the non-wetting portion 36r on the protective film 125 (the first separation portion 127r and the second separation portion 128r).
  • the void 38r is opened at least on the surface of the solder 20r on the semiconductor chip 12 side. In this test, the void 38r penetrated the solder 20r. It was also found that the void 38r is more likely to occur as the time from the end of the first reflow to the start of the second reflow is longer.
  • the surface electrode 121 in the solder 20r. It became clear that a void 38r could occur in the upper part.
  • the protective film 125r has a hygroscopic property, and moisture in the protective film 125r is vaporized during reflow.
  • the water vapor moves in the protective film 125r or in the non-wetting portion 36r that is an interface with the solder 20r.
  • a part of the water vapor moves in a direction approaching the intersection 131r.
  • water vapor collects and stays at the intersecting portion 131r or the unwetting portion 36r immediately above it from the first separation portion 127r and the second separation portion 128r (or the non-wetting portion 36r) connected to the intersecting portion 131r. .
  • the semiconductor chip 12r is warped to some extent as shown in FIG. Specifically, a concave warp occurs on the surface electrode 121r side. In FIG. 10, the back electrode 130r is omitted for convenience.
  • the rear surface electrode 130r which is the convex side is arranged upward, and the front surface electrode 121r which is the concave side is arranged downward, so that the intersecting portion is passed through the first separation portion 127r and the second separation portion 128r (or the non-wetting portion 36r)
  • Water vapor collects and stays at 131r.
  • the water vapor in the surrounding portion 126r also moves toward the intersecting portion 131r. This is the second presumed cause that the void 38r is generated around the intersection 131r.
  • the protective film 125 includes a first separation portion 127 extending in the X direction and a second separation portion 128 extending in the Y direction, whereby the surface electrode 121 is partitioned in both the X direction and the Y direction. It has been. Therefore, the warp of the semiconductor chip 12 can be reduced.
  • the protective film 125 does not have a crossing portion between the first separation portion 127 and the second separation portion 128. Therefore, even if a part of the water vapor formed by vaporization of the water in the protective film 125 during reflow moves from each of the first separation unit 127 and the second separation unit 128 toward the portion corresponding to the intersection 131r, As shown in FIG. 11, they are not collected in one place.
  • the first connecting portion 121b of the surface electrode 121 is present in the opposing region between the first separating portion 127 and the second separating portion 128, and the water vapor in the first separating portion 127 and the water vapor in the second separating portion 128 are present. Does not cross. Therefore, it can suppress that a void arises in the part on the surface electrode 121 in the solder 20.
  • the first separation portion 127 and the second separation portion 128 are not connected, and the first connection portion is interposed therebetween. Since 121b exists, the water vapor in the 1st separation part 127 and the water vapor in the 2nd separation part 128 do not cross. Also by this, it can suppress that water vapor
  • FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 2, and corresponds to FIG. 8 (comparative example). As shown in FIG. 13, even in the portion where the void 38r is generated in the comparative example, no void is generated, and the non-wetting portion 36 is merely formed on the protective film 125 (second separation portion 128 in FIG. 13).
  • the first separation unit 127 is divided into a plurality of pieces in the X direction that is the extending direction. Therefore, it is possible to suppress the generation of voids on the surface electrode 121 while effectively reducing the warpage of the semiconductor chip 12.
  • it is divided into a plurality in the longitudinal direction.
  • the first separation part 127 having a long length between both ends is divided into a plurality of parts. Therefore, it is possible to effectively suppress water vapor from being collected near the center in the longitudinal direction.
  • each of the first separation unit 127 and the second separation unit 128 is connected to the peripheral portion 126.
  • the first separation unit 127 and the second separation unit 128 are not connected and the first connection unit 121b exists between them, the water vapor (moisture) in the surrounding portion 126 passes through the first separation unit 127. It does not intersect with the water vapor in the second separation part 128. Therefore, it is possible to suppress the generation of voids even though the first separation unit 127 and the second separation unit 128 are configured to be continuous with the peripheral portion 126.
  • the Ni film 123 that is the most rigid film among the plurality of thin films is divided by the first separation part 127 and the second separation part 128 of the protective film 125.
  • that rigidity is large means that the expansion
  • the temperature of the semiconductor chip 12 becomes highest near the center of the active region, that is, near the center 121a of the surface electrode 121 by driving the element.
  • the first connecting portion 121b that is, the Ni film 123 and the Au film 124 are arranged in the opposing region of the first separation portion 127 and the second separation portion 128, and the solder 20 is connected (joined). Is done. Therefore, the heat of the semiconductor chip 12 can be effectively radiated to the terminal 22 side.
  • the first separation unit 127 may not be divided, and only the second separation unit 128 may be divided into a plurality of pieces.
  • the length of the protective film 125 disposed on the surface electrode 121 (the base film 122) is longer, the possibility that water vapor stays on the surface electrode 121 is increased. It is better to divide the separation unit 127.
  • the numbers of the first separation unit 127 and the second separation unit 128 that are connected to the same surface of the peripheral portion 126 are not limited to the above example. For example, you may have two 2nd isolation
  • the semiconductor chip 12 of this embodiment not only the first separation unit 127 but also the second separation unit 128 is divided into a plurality of parts. And the 2nd separation part 128 is divided
  • the opposing region between the first separation parts 127 and the opposing region between the second separation parts 128 are integrally connected. That is, the first separation unit 127 and the second separation unit 128 are divided at the same position.
  • the Ni film 123 and the Au film 124 that are metal thin films are arranged in the facing region, and thereby, the second connecting portion 121c to which the solder 20 is connected is formed.
  • the 2nd connection part 121c has comprised the plane substantially cross shape.
  • the surface electrode 121 has two second connecting portions 121c.
  • the second connecting portion 121c connects the portions separated in the X direction by the second separating portion 128 in the surface electrode 121 and also connects the portions separated in the Y direction by the first separating portion 127. .
  • each of the first separation unit 127 and the second separation unit 128 is divided into a plurality of parts, and thus has no intersection. As shown in FIG. 16, the water vapor in the first separator 127 and the water vapor in the second separator 128 do not intersect. Further, the water vapor in the divided first separation unit 127 does not intersect, and the water vapor in the divided second separation unit 128 does not intersect. Therefore, it is possible to effectively suppress the occurrence of voids in the portion of the solder 20 on the surface electrode 121 while reducing the warp of the semiconductor chip 12.
  • the water vapor (moisture) in the surrounding portion 126 does not intersect with the water vapor in the other divided first separation portion 127 and second separation portion 128 through the first separation portion 127.
  • the water vapor in the peripheral portion 126 does not intersect with the water vapor in the other divided second separation portion 128 or the first separation portion 127 through the second separation portion 128. Also by this, it can suppress that a void arises.
  • the second connecting portion 121c has a substantially cross shape in a plane, and has a larger area along the XY plane than the first connecting portion 121b. For this reason, the 2nd connection part 121c has a larger connection area with the solder 20 than the 1st connection part 121b. Since the second connecting portion 121c is provided in the vicinity of the center 121a that is at a high temperature, the heat of the semiconductor chip 12 can be radiated more effectively.
  • the number of divisions is not limited to the above example. Further, the numbers of the first separation unit 127 and the second separation unit 128 connected to the same surface of the peripheral portion 126 are not limited to the above example.
  • the protective film 125 has an intersecting portion 131 where the first separating portion 127 and the second separating portion 128 intersect.
  • the protective film 125 has one second separator 128 and two first separators 127.
  • the two first separators 127 have the same length, and the surface electrode 121 is divided into three equal parts in the Y direction by the first separators 127.
  • the second separator 128 is provided at the center in the X direction, and the surface electrode 121 is divided into two equal parts in the X direction by the second separator 128.
  • the protective film 125 has two intersecting portions 131.
  • the first separation portion 127 is provided away from the peripheral portion 126 so as not to be connected to the peripheral portion 126.
  • a Ni film 123 and an Au film 124 which are metal thin films, are arranged in regions facing both ends of the first separation part 127 and the inner peripheral surface of the peripheral part 126, whereby the outer peripheral connection to which the solder 20 is connected.
  • a portion 121d is formed.
  • the second separation portion 128 is provided away from the peripheral portion 126 so as not to be continuous with the peripheral portion 126.
  • a Ni film 123 and an Au film 124, which are metal thin films, are arranged in regions opposite to both ends of the second separation part 128 and the inner peripheral surface of the peripheral part 126, whereby the outer peripheral connection to which the solder 20 is connected.
  • a portion 121e is formed.
  • the surface electrode 121 has six outer peripheral connection parts 121d and 121e.
  • the outer periphery connecting portion 121 d connects the portions separated in the Y direction by the first separation portion 127 in the surface electrode 121 in the vicinity of the outer peripheral end of the surface electrode 121.
  • the outer periphery connecting portion 121 e connects the portions separated in the X direction by the second separation portion 128 in the surface electrode 121 in the vicinity of the outer peripheral end of the surface electrode 121.
  • the protective film 125 has an intersection 131.
  • the first separation portion 127 and the second separation portion 128 are separated from the peripheral portion 126.
  • the water vapor (moisture) in the peripheral portion 126 does not intersect with the water vapor in the first separation portion 127 or the second separation portion 128. That is, the surrounding water vapor does not reach the intersection 131.
  • the water vapor collected at the intersection 131 can be reduced.
  • the length of the 1st separation part 127 and the 2nd separation part 128 is shortened for the outer periphery connection parts 121d and 121e, and thereby, water vapor collected at the intersection part 131 can be reduced.
  • voids are formed on the portion of the solder 20 on the surface electrode 121 while reducing the warp of the semiconductor chip 12 by the protective film 125. It can be suppressed from occurring.
  • the first separation unit 127 and the second separation unit 128 are provided apart from the peripheral portion 126, and the first separation unit 127 and the second separation unit 128 are disposed between the peripheral portion 126.
  • the number of the 1st separation part 127 and the 2nd separation part 128 is not limited to the said example.
  • a configuration having one first separation unit 127 and two second separation units 128 may be employed.
  • the semiconductor chip 12 shown in FIG. 19 is configured by combining the second embodiment and the third embodiment.
  • the first separation unit 127 and the second separation unit 128 do not have an intersecting portion and are provided so as not to be connected to the peripheral portion 126.
  • the surface electrode 121 has the 2nd connection part 121c and the outer periphery connection parts 121d and 121e.
  • first separation unit 127 In the first embodiment and the second embodiment, an example in which there is no intersection between the first separation unit 127 and the second separation unit 128 is shown.
  • the closer to the center 121a the easier it is for water vapor to collect from the surroundings. Therefore, it may be configured such that only the vicinity of the center 121a does not intersect and intersects at a position away from the center 121a.
  • first connecting portion 121b is formed by disposing the Ni film 123 and the Au film 124, which are metal thin films, in the facing region between the first separation portion 127 and the second separation portion 128.
  • second connecting portion 121c is formed in the facing region between the first separation portions 127 and the facing region between the second separation portions 128 has been shown.
  • region of the 1st separation part 127, the 2nd separation part 128, and the surrounding part 126 was shown.
  • a configuration in which the metal thin film is not disposed in the facing region and the base film 122 is exposed may be employed.
  • a 1 in 1 package including one semiconductor chip 12 is shown as the semiconductor module 10, it is not limited to this.
  • the present invention can also be applied to a 2-in-1 package that includes two semiconductor chips 12 and constitutes an upper and lower arm for one phase, and a 6-in1 package that includes six semiconductor chips 12 and constitutes an upper- and lower-arm for three phases.
  • the present invention can also be applied to a configuration that does not include the sealing resin body 14.
  • the present invention can be applied to a configuration in which the heat sinks 26 and 32 are not exposed from the sealing resin body 14.
  • the present invention is not limited to this.
  • a configuration in which the terminal 22 is not provided and the heat sink 26 is connected to the surface electrode 121 of the semiconductor chip 12 via solder may be employed.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

L'invention concerne un dispositif semi-conducteur qui comprend : un substrat en semi-conducteur (120) qui possède une surface avant (120a) et une surface arrière (120b) opposée à la surface avant dans une direction d'épaisseur de plaque, et sur lequel est formé un élément ; une électrode de surface avant (121) soudée sur la surface avant du substrat en semi-conducteur ; un film protecteur (125) formé en utilisant un matériau hygroscopique ; et une électrode de surface arrière (130) disposée sur la surface arrière du substrat en semi-conducteur. Le film protecteur comprend : une section périphérique (126) disposée de façon à entourer l'électrode de surface avant sur la surface avant du substrat en semi-conducteur ; une première section de séparation (127) qui s'étend dans le sens des lignes, orthogonal au sens de l'épaisseur de la plaque dans une région entourée par la section périphérique, et qui divise l'électrode de surface avant dans le sens des colonnes, orthogonal au sens de l'épaisseur de plaque et au sens des lignes ; et une deuxième section de séparation (128) qui s'étend dans le sens des colonnes dans la région et qui divise l'électrode de surface avant dans le sens des lignes. La première section de séparation et la deuxième section de séparation sont disposées de manière séparée l'une de l'autre de façon à éviter une intersection.
PCT/JP2018/009849 2017-04-06 2018-03-14 Dispositif semi-conducteur WO2018186131A1 (fr)

Applications Claiming Priority (2)

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JP2017-076086 2017-04-06
JP2017076086A JP6702250B2 (ja) 2017-04-06 2017-04-06 半導体装置

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Publication number Priority date Publication date Assignee Title
JP7293978B2 (ja) * 2019-08-21 2023-06-20 株式会社デンソー 半導体装置
JP7287181B2 (ja) * 2019-08-21 2023-06-06 株式会社デンソー 半導体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03184396A (ja) * 1989-12-13 1991-08-12 Fujitsu Ltd 多層配線基板におけるポリイミド層の膨らみ防止構造
JP2000183108A (ja) * 1998-12-18 2000-06-30 Nec Corp 半導体集積回路装置及びその製造方法
JP2005116962A (ja) * 2003-10-10 2005-04-28 Denso Corp パッケージ型半導体装置
JP2011066377A (ja) * 2009-08-18 2011-03-31 Denso Corp 半導体装置およびその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03184396A (ja) * 1989-12-13 1991-08-12 Fujitsu Ltd 多層配線基板におけるポリイミド層の膨らみ防止構造
JP2000183108A (ja) * 1998-12-18 2000-06-30 Nec Corp 半導体集積回路装置及びその製造方法
JP2005116962A (ja) * 2003-10-10 2005-04-28 Denso Corp パッケージ型半導体装置
JP2011066377A (ja) * 2009-08-18 2011-03-31 Denso Corp 半導体装置およびその製造方法

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