JPH0263148A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0263148A JPH0263148A JP21551188A JP21551188A JPH0263148A JP H0263148 A JPH0263148 A JP H0263148A JP 21551188 A JP21551188 A JP 21551188A JP 21551188 A JP21551188 A JP 21551188A JP H0263148 A JPH0263148 A JP H0263148A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor chip
- resin
- semiconductor device
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 229920005989 resin Polymers 0.000 claims abstract description 18
- 239000011347 resin Substances 0.000 claims abstract description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 3
- 239000002356 single layer Substances 0.000 claims abstract description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 238000007789 sealing Methods 0.000 abstract description 5
- 230000035939 shock Effects 0.000 abstract description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 1
- 229910052593 corundum Inorganic materials 0.000 abstract 1
- 238000000605 extraction Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 1
- 238000007747 plating Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 235000008331 Pinus X rigitaeda Nutrition 0.000 description 1
- 235000011613 Pinus brutia Nutrition 0.000 description 1
- 241000018646 Pinus brutia Species 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Formation Of Insulating Films (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に樹脂封止された半導体
装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device, and particularly to a resin-sealed semiconductor device.
従来、樹脂封止型半導体装置におけるパッシベーション
技術では、第４図に示すように、回路素子の形成された
半導体チップ１０１の表面を電極パッド部が開口された
保護膜１０４（例えば、ＰＳＧ膜、５ｉｚＮ４膜）で被
覆することによってのみ、回路素子への水分、不純物等
の浸入低減を計っていた。Conventionally, in the passivation technology for resin-sealed semiconductor devices, as shown in FIG. 4, a protective film 104 (for example, a PSG film, 5izN4 The only way to reduce the infiltration of moisture, impurities, etc. into circuit elements was by coating them with a film.
上述した従来の樹脂封止型半導体装置は、封入樹脂と密
着性のよいＰ Ｓ Ｇ、 Ｓ ｉ ３Ｎ４等の保護膜１
０４で覆われている、回路素子の形成された半導体チッ
プ面と、半導体チップ１０１の支持体（アイランド）１
０５および外部導出線部（ピン）１０６等封入樹脂１０
７との密着性の悪い金属部分とが存在するため、はんだ
付は等の熱衝撃が加わると封入樹脂１０７との密着性の
不均一性から応力集中が起こり、封入樹脂１０７の亀裂
（パッケージ・クラック）、封入樹脂１０７と上記金属
とのはがれ、あるいは保護膜１０４の亀裂（パッシベー
ション・クラック）が生じ、その結果回路素子の耐湿性
を低下させるという欠点がある。さらに、回路素子の形
成されていない半導体チップ面とポンディング・ワイヤ
１０３との短絡や保護膜１０４の形成されていない電極
パッド部の腐食が生じるという欠点もある。The conventional resin-encapsulated semiconductor device described above uses a protective film 1 such as PSG, Si3N4, etc. that has good adhesion to the encapsulating resin.
04 and the semiconductor chip surface on which circuit elements are formed, and the support (island) 1 of the semiconductor chip 101.
05 and external lead wire portion (pin) 106 etc. encapsulating resin 10
Since there are metal parts with poor adhesion to the encapsulating resin 107, when a thermal shock such as during soldering is applied, stress concentration occurs due to the uneven adhesion with the encapsulating resin 107, resulting in cracks in the encapsulating resin 107 (package/ Cracks), peeling between the encapsulating resin 107 and the metal, or cracks in the protective film 104 (passivation cracks) occur, resulting in a disadvantage in that the moisture resistance of the circuit element is reduced. Further, there are also disadvantages in that a short circuit occurs between the surface of the semiconductor chip on which no circuit elements are formed and the bonding wire 103, and corrosion occurs in the electrode pad portion on which the protective film 104 is not formed.
本発明の樹脂封止型半導体装置は、半導体チッフ、半導
体チップの支持体および外部導出線部での少なくとも封
入樹脂との接触面を被覆する絶縁膜を有している。The resin-sealed semiconductor device of the present invention includes a semiconductor chip, a support for the semiconductor chip, and an insulating film that covers at least the contact surface with the encapsulating resin at the external lead wire portion.
そして、上記絶縁膜としては５ｉｎ２膜、Ｓｉ。The insulating film is a 5in2 film of Si.
Ｎ、膜、Ｓ ｉ、Ｏ，Ｎｌ膜、ＰＳＧ膜およびＡβ、０
゜膜の単層膜もしくは多層膜が用いられる。N, film, Si, O, Nl film, PSG film and Aβ, 0
A single-layer film or a multi-layer film of ゜ film is used.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の断面図である。１０１は半
導体チップ、１０２は電極パッド部（ＡＩ；！パッド）
、１０３は金線（ボンディングワイヤ）、１０４はパッ
シベーション膜（Ｓ ｉ ｓ Ｎ ｓ ［） テｔｂる
。また、１０５，１０６はリードフレームであり、１０
５は半導体チップの支持体部（マウント部）、１０６は
外部導出線部（ピン部）で、１０７は封入樹脂である。FIG. 1 is a sectional view of an embodiment of the present invention. 101 is a semiconductor chip, 102 is an electrode pad part (AI;! pad)
, 103 is a gold wire (bonding wire), and 104 is a passivation film (S i s N s [)]. Further, 105 and 106 are lead frames, and 10
Reference numeral 5 denotes a support part (mount part) for the semiconductor chip, 106 a lead-out wire part (pin part), and 107 a sealing resin.
半導体チップ１０１．！ｊ−ドフレームマウント部１０
５． リードフレームビン！マツ
部１０６の半導体チップ１０１側およびＡｆｌ？ドレス
部１０２と樹脂１０７との接触面はすべてシリコン酸化
膜（Ｓ １ｏｚ） １０８により覆われている。Semiconductor chip 101. ! J-frame mount part 10
5. Lead frame bin! The semiconductor chip 101 side of the pine portion 106 and Afl? The entire contact surface between the dress portion 102 and the resin 107 is covered with a silicon oxide film (S 1 oz) 108.
第２図は第１図に示した本実施例の半導体装置と第４図
に示した従来の半導体装置の、耐湿性を比較するために
行ったプレッシャークツカー試験（Ｐ ＣＴ）の結果で
ある。第１図に示した本実施例の半導体装置１０００個
と第４図に示した従来の半導体装置１０００個の試料を
、１５０℃、２気圧の水蒸気釜に入れ不良数を調べた。Figure 2 shows the results of a pressure pressure test (PCT) conducted to compare the moisture resistance of the semiconductor device of this embodiment shown in Figure 1 and the conventional semiconductor device shown in Figure 4. . Samples of 1,000 semiconductor devices of the present embodiment shown in FIG. 1 and 1,000 samples of conventional semiconductor devices shown in FIG. 4 were placed in a steam oven at 150° C. and 2 atm to determine the number of defects.
第２図に示すように、本実施例の半導体装置の方が従来
の半導体装置に比べ耐湿性が向上し、不良数の発生が低
減している。また、ＰＣＴ試験試験２峙０波探傷法によ
り調べたところ発生クラブク数は、従来のものに比べ本
実施例の半導体装置は１割程度に低減していた。As shown in FIG. 2, the semiconductor device of this example has better moisture resistance than the conventional semiconductor device, and the number of defects is reduced. Further, when examined using the PCT test and the 0-wave flaw detection method, it was found that the number of cracks generated in the semiconductor device of this example was reduced to about 10% compared to the conventional one.
第３図は本発明の他の実施例の断面図であり、プラスチ
ックＰＧＡ （３２ｉｎ ｇｒｉｄ ａｒｒａｙ）を示
している。４０１はプリント基板で、半導体チップ１０
１の支持体である。４０２はプリント基板４０１上にパ
ターニングされた金メツキ、４０３は半導体チップ１０
１を金メツキ４０２部に固定するための銀ペースト、４
０４はプリント基板４０１上にパターニングされた銅メ
ツキである。FIG. 3 is a cross-sectional view of another embodiment of the invention, showing a plastic PGA (32 inch grid array). 401 is a printed circuit board with semiconductor chip 10
1 support. 402 is the gold plating patterned on the printed circuit board 401, and 403 is the semiconductor chip 10.
Silver paste for fixing 1 to gold plating 402 parts, 4
04 is copper plating patterned on the printed circuit board 401.
４０５はリードピンで、銅メツキ４０４とリードピン４
０５で外部導出線を形成する。４０６は封入樹脂である
エポキシ樹脂である。４０７はシリコン酸化窒化膜（Ｓ
１ｚｏｙＮｓ）であり、エポキシ樹脂４０６と接触す
る半導体チップ１０１，プリント基板４０１，銅メツキ
４０４のすべての表面を被覆している。405 is a lead pin, copper plating 404 and lead pin 4
In step 05, an external lead line is formed. 406 is an epoxy resin which is a sealing resin. 407 is a silicon oxynitride film (S
1 zoyNs), and covers all surfaces of the semiconductor chip 101, printed circuit board 401, and copper plating 404 that come into contact with the epoxy resin 406.
第３図に示したプラスチックＰＧＡは１４４ピンで、パ
ッケージの１辺が４４鵬である。ＰＣＴによる耐湿性試
験を行った結果は、セラミックパッケージのＰＧＡとほ
ぼ同様の耐湿性を示して、ぎわ・めて耐湿性の良いこと
が示された。The plastic PGA shown in FIG. 3 has 144 pins, and each side of the package has 44 pins. The results of a moisture resistance test using PCT showed that it had almost the same moisture resistance as the PGA of the ceramic package, indicating that it had extremely good moisture resistance.
また、従来技術の多ピンの半導体装置で比較的起こり易
い、ボンディングワイヤ１０３と半導体チップ１０１側
面との短絡は全く起こらない。Further, short circuit between the bonding wire 103 and the side surface of the semiconductor chip 101, which is relatively easy to occur in conventional multi-pin semiconductor devices, does not occur at all.
以上説明したように本発明の半導体装置は、半導体チッ
プ、半導体チップの支持体および外部導出線部と封入樹
脂との接触面を絶縁膜により被覆することにより、封入
樹脂と内部部品（半導体チップ、半導体チップの支持体
および外部導出線）との密着性を均等に高めることによ
って、熱衝撃時における内部部品と封入樹脂とのはがれ
、パッケージ・クラック、パッシベーションクラックを
抑制でき、耐湿性をきわめて高くすることができる効果
がある。As explained above, in the semiconductor device of the present invention, the contact surface between the semiconductor chip, the support of the semiconductor chip, the external lead wire portion, and the encapsulating resin is coated with an insulating film, so that the encapsulating resin and internal parts (semiconductor chip, By uniformly increasing the adhesion with the semiconductor chip support and external lead-out wires, it is possible to suppress peeling of internal parts and encapsulating resin during thermal shock, package cracks, and passivation cracks, and extremely high moisture resistance. There is an effect that can be done.
また、金属パッド部，半導体チップ側面部も上記絶縁膜
で被覆していることにより、金属パッド腐食の抑制，半
導体チップ側面とポンディングワイヤの短絡の防止がで
きる効果がある。Furthermore, since the metal pad portion and the side surface of the semiconductor chip are also covered with the insulating film, corrosion of the metal pad can be suppressed and short circuit between the side surface of the semiconductor chip and the bonding wire can be prevented.
第１図は本発明の一実施例の樹脂封止型半導体装置の断
面図、第２図は本発明の一実施例の効果を示す耐湿性試
験の結果を示す図、第３図は本発明の他の実施例のプラ
スチックＰＧＡの断面図、第４図は従来の半導体装置の
断面図である。FIG. 1 is a cross-sectional view of a resin-sealed semiconductor device according to an embodiment of the present invention, FIG. 2 is a diagram showing the results of a moisture resistance test showing the effects of an embodiment of the present invention, and FIG. 3 is a diagram showing the results of a moisture resistance test according to an embodiment of the present invention. FIG. 4 is a sectional view of a conventional semiconductor device.
Claims (1)
該半導体チップの支持体および外部導出線部の少なくと
も封入樹脂との接触面が絶縁膜で被覆されていることを
特徴とする半導体装置（２）前記絶縁膜がシリコン酸化
膜、シリコン窒化膜、シリコン酸化窒化膜、リンガラス
膜あるいは酸化アルミニウム膜の単層膜及びこれらの膜
を組み合わせた多層膜であることを特徴とする請求項１
記載の半導体装置(1) In a resin-sealed semiconductor device, a semiconductor chip,
A semiconductor device characterized in that at least the contact surface with the encapsulating resin of the support body and the external lead-out wire portion of the semiconductor chip is covered with an insulating film (2) The insulating film is a silicon oxide film, a silicon nitride film, a silicon Claim 1, characterized in that it is a single layer film of an oxynitride film, a phosphorous glass film, or an aluminum oxide film, or a multilayer film combining these films.
Semiconductor device described
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21551188A JPH0263148A (en) | 1988-08-29 | 1988-08-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21551188A JPH0263148A (en) | 1988-08-29 | 1988-08-29 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0263148A true JPH0263148A (en) | 1990-03-02 |
Family
ID=16673620
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21551188A Pending JPH0263148A (en) | 1988-08-29 | 1988-08-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0263148A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1992004729A1 (en) * | 1990-09-10 | 1992-03-19 | Olin Corporation | Leadframe for molded plastic electronic packages |
| US5455453A (en) * | 1991-07-01 | 1995-10-03 | Sumitomo Electric Industries, Ltd. | Plastic package type semiconductor device having a rolled metal substrate |
| US5523590A (en) * | 1993-10-20 | 1996-06-04 | Oki Electric Industry Co., Ltd. | LED array with insulating films |
| US5530292A (en) * | 1990-03-15 | 1996-06-25 | Fujitsu Limited | Semiconductor device having a plurality of chips |
| JP2014116333A (en) * | 2012-12-06 | 2014-06-26 | Mitsubishi Electric Corp | Semiconductor device |
| JP5804203B2 (en) * | 2012-07-11 | 2015-11-04 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
-
1988
- 1988-08-29 JP JP21551188A patent/JPH0263148A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5530292A (en) * | 1990-03-15 | 1996-06-25 | Fujitsu Limited | Semiconductor device having a plurality of chips |
| WO1992004729A1 (en) * | 1990-09-10 | 1992-03-19 | Olin Corporation | Leadframe for molded plastic electronic packages |
| US5122858A (en) * | 1990-09-10 | 1992-06-16 | Olin Corporation | Lead frame having polymer coated surface portions |
| US5455453A (en) * | 1991-07-01 | 1995-10-03 | Sumitomo Electric Industries, Ltd. | Plastic package type semiconductor device having a rolled metal substrate |
| US5643834A (en) * | 1991-07-01 | 1997-07-01 | Sumitomo Electric Industries, Ltd. | Process for manufacturing a semiconductor substrate comprising laminated copper, silicon oxide and silicon nitride layers |
| US5523590A (en) * | 1993-10-20 | 1996-06-04 | Oki Electric Industry Co., Ltd. | LED array with insulating films |
| US5733689A (en) * | 1993-10-20 | 1998-03-31 | Oki Electric Industry Co., Ltd. | Led array fabrication process with improved unformity |
| US5869221A (en) * | 1993-10-20 | 1999-02-09 | Oki Electric Industry Co., Ltd. | Method of fabricating an LED array |
| JP5804203B2 (en) * | 2012-07-11 | 2015-11-04 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
| US9543252B2 (en) | 2012-07-11 | 2017-01-10 | Mitsubishi Electric Corporation | Semiconductor apparatus and method for producing the same |
| JP2014116333A (en) * | 2012-12-06 | 2014-06-26 | Mitsubishi Electric Corp | Semiconductor device |
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