JPH01282844A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPH01282844A JPH01282844A JP88113188A JP11318888A JPH01282844A JP H01282844 A JPH01282844 A JP H01282844A JP 88113188 A JP88113188 A JP 88113188A JP 11318888 A JP11318888 A JP 11318888A JP H01282844 A JPH01282844 A JP H01282844A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor element
- sealing resin
- semiconductor device
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 229920005989 resin Polymers 0.000 claims abstract description 21
- 239000011347 resin Substances 0.000 claims abstract description 21
- 238000007789 sealing Methods 0.000 abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 230000001070 adhesive effect Effects 0.000 abstract 2
- 230000002950 deficient Effects 0.000 abstract 2
- 210000001331 nose Anatomy 0.000 abstract 1
- 230000006866 deterioration Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 230000035939 shock Effects 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000010306 acid treatment Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 150000003961 organosilicon compounds Chemical class 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は樹脂封止型半導体装置に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a resin-sealed semiconductor device.
従来、半導体装置は安価で、しかも、量産性に適してい
ることから樹脂封止型が主流となっていた。そして、こ
の種の樹脂封止型半導体装置は、第３図（ａ）に示す様
に、Ａｇペースト等のろう材３１０で半導体素子搭載部
３９に半導体素子３１が固着され、半導体素子３１のＡ
ｕパッド部３２と内部リード端子３６とがＡｕ線等の金
属細線３４で電気的接続され、エポキシ樹脂等の樹脂３
８で封止され、樹脂の外部に成型加工された外部リード
端子３５が設けられている。Conventionally, resin-sealed semiconductor devices have been the mainstream because they are inexpensive and suitable for mass production. In this type of resin-sealed semiconductor device, as shown in FIG.
The u pad portion 32 and the internal lead terminal 36 are electrically connected with a thin metal wire 34 such as an Au wire, and a resin 3 such as an epoxy resin is used.
8 and is provided with an external lead terminal 35 molded on the outside of the resin.
上述した従来の樹脂封止型半導体装置では、封止樹脂と
リードフレームの熱膨張係数が異なるために密着性が悪
く、特に、半導体装置をプリント基板に実装する際に熱
衝撃が加わると、樹脂−リードフレーム界面にすきまを
生じ、水分・不純物がこのすきまから半導体装置内に侵
入して耐湿性を劣化させるという欠点がある。さらに、
表面実装型の樹脂封止型半導体装置は薄型化、小型化し
ているために、実装時の熱衝撃により、樹脂−半導体素
子搭載部界面が剥離して半導体素子搭載部の端部（エツ
ジ）に内部応力が集中し、封止樹脂に亀裂（クラック）
が生じる。その結果、耐湿性劣化、Ａｕ線切れ、実装不
良という欠点をも有する。しかも、従来の樹脂封止型半
導体装置は半導体素子上のポンディング後のＡＡ電極（
パッド）部に保護膜（パッシベーション膜）が形成され
ていないために、半導体装置内に入り込んだ水分・不純
物が半導体素子の表面に達し、パッド部のＡｎを腐食し
耐湿性不良を招きやすいという欠点がある。In the conventional resin-encapsulated semiconductor device described above, the sealing resin and the lead frame have different coefficients of thermal expansion, resulting in poor adhesion.In particular, when a thermal shock is applied when the semiconductor device is mounted on a printed circuit board, the resin - There is a drawback that a gap is created at the interface of the lead frame, and moisture and impurities enter the semiconductor device through this gap, deteriorating the moisture resistance. moreover,
Surface-mounted resin-sealed semiconductor devices are becoming thinner and smaller, so thermal shock during mounting can cause the resin-semiconductor element mounting area interface to peel off, causing the edge of the semiconductor element mounting area to peel off. Internal stress concentrates and cracks occur in the sealing resin.
occurs. As a result, it also has drawbacks such as deterioration of moisture resistance, breakage of Au wires, and poor mounting. Moreover, the conventional resin-sealed semiconductor device has an AA electrode (
Because a protective film (passivation film) is not formed on the pad portion, moisture and impurities that enter the semiconductor device reach the surface of the semiconductor element, corrode the An on the pad portion, and tend to cause poor moisture resistance. There is.
本発明の樹脂封止型半導体装置は、半導体素子搭載部を
持たないリードフレームの内部リードと半導体素子がワ
イヤボンディングされ、前記半導体素子とボンディング
ワイヤ及び内部リードの表面が絶縁膜で被覆され、かつ
、前記絶縁膜表面が全て樹脂で封止されていることを特
徴とする。In the resin-sealed semiconductor device of the present invention, an internal lead of a lead frame having no semiconductor element mounting portion and a semiconductor element are wire-bonded, and the surfaces of the semiconductor element, the bonding wire, and the internal lead are coated with an insulating film, and , the entire surface of the insulating film is sealed with resin.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）は本発明の第１の実施例である樹脂封止型
半導体装置の断面図、第１図（ｂ）は該第１の実施例の
ポンディング直後の平面図である。半導体素子１１を、
半導体素子搭載部をもたないリードフレーム１７の内部
リード１６先端に、絶縁ペースト１１１で固着し、半導
体素子上に形成されたＡｊ２パッド部１２の内部リード
、外部リード１５をＡｕ線で電気的に接続する。さらに
、封止樹脂１８との接触面、すなわち、半導体素子、Ａ
ｎパッド部、Ａｕ線、内部リード全面を、封止樹脂と密
着性の良好なシリコン酸化膜（ＳｉＯ２）１１２で被覆
する。膜は化学的気相成長法（ＣＶＤ）で形成するが、
半導体素子への影響、ポンディング剥れ（パープル・ブ
レーグ）、量産性を考慮に入れて、低温・短時間・常圧
下で行なわれるのが望ましい。−例として、ボンディン
グ後リードフレームを一定温度に保たれた反応炉内に導
入し、Ｓ ｉ Ｈ４ガスと０２ガスを流し込み、紫外線
を照射することによりＳｉＯ□膜を形成する方法があげ
られる。反応源として紫外線の光エネルギーを使用する
ために低温・短時間で反応できる。FIG. 1(a) is a sectional view of a resin-sealed semiconductor device according to a first embodiment of the present invention, and FIG. 1(b) is a plan view of the first embodiment immediately after bonding. The semiconductor element 11,
The inner leads 16 of the lead frame 17 which does not have a semiconductor element mounting part are fixed with an insulating paste 111, and the inner leads and outer leads 15 of the Aj2 pad part 12 formed on the semiconductor element are electrically connected with Au wires. Connecting. Furthermore, the contact surface with the sealing resin 18, that is, the semiconductor element, A
The n pad portion, the Au wire, and the entire surface of the internal lead are covered with a silicon oxide film (SiO2) 112 that has good adhesion to the sealing resin. The film is formed by chemical vapor deposition (CVD),
Taking into consideration the effect on semiconductor elements, bonding peeling (purple breakage), and mass productivity, it is preferable to carry out the process at low temperature, for a short time, and under normal pressure. - As an example, there is a method of forming a SiO□ film by introducing the lead frame after bonding into a reactor kept at a constant temperature, pouring S i H4 gas and O2 gas, and irradiating it with ultraviolet rays. Because it uses ultraviolet light energy as the reaction source, it can react at low temperatures and in a short time.
Ｓ ｉ Ｏ２膜で被覆した後、エポキシ樹脂で封止し、
外部リードの成型加工を行なう。外部リード全面にも５
ｉｎ２膜が被覆されるが、外部リードに半田めっきを付
ける際の酸処理等で容易に除去することができる。上記
のように、半導体素子搭載部をなくし、封止樹脂との接
触面を、封止樹脂と密着性の良好なＳ ｉ Ｏ２膜で被
覆することにより、実装時に発生するクラック、界面す
き間を著しく低減し、耐湿性劣化を防止することができ
る。After covering with SiO2 film, sealing with epoxy resin,
Performs molding of external leads. 5 on the entire external lead
Although the in2 film is covered, it can be easily removed by acid treatment or the like when attaching solder plating to the external lead. As mentioned above, by eliminating the semiconductor element mounting area and covering the contact surface with the sealing resin with a SiO2 film that has good adhesion to the sealing resin, cracks and interface gaps that occur during mounting can be significantly reduced. It is possible to reduce moisture resistance and prevent deterioration of moisture resistance.
第２図（ａ）は本発明の第２の実施例である樹脂封止型
半導体装置の断面図、第２図（ｂ）は該第２の実施例の
ポンディング直後の断面図である。半導体素子２１を支
持台２１３に吸着させて固定し、半導体素子上に形成さ
れたＡＡパッド部２２と内部リード２６、外部リード２
５をＡｕ線線種４電気的に接続する。さらに、第１の実
施例と同様に、封止樹脂２８との接触面を、封止樹脂と
密着性の良好なシリコン酸化窒化膜（Ｓ ｉ 、０．Ｎ
、） ２１２で被覆する。−例として、ポンディング後
リードフレームを一定温度に保たれた反応炉内に導入し
、窒素原子（Ｎ）を含む有機ケイ素化合物ガスを化学的
に活性な０３ガスを用いて分解し５ｉｘＯアＮ。FIG. 2(a) is a sectional view of a resin-sealed semiconductor device according to a second embodiment of the present invention, and FIG. 2(b) is a sectional view of the second embodiment immediately after bonding. The semiconductor element 21 is adsorbed and fixed on a support base 213, and the AA pad portion 22, internal leads 26, and external leads 2 formed on the semiconductor element are attached.
5 is electrically connected to Au wire type 4. Further, as in the first embodiment, the contact surface with the sealing resin 28 is coated with a silicon oxynitride film (S i , 0.N
, ) 212. - For example, after bonding, the lead frame is introduced into a reactor kept at a constant temperature, and organosilicon compound gas containing nitrogen atoms (N) is decomposed using chemically active 03 gas. .
膜を形成する方法があげられる。上記のように、半導体
素子搭載部をなくし、封止樹脂との接触面を、封止樹脂
と密着性の良好なＳｉヨ０アＮ、膜で被覆することによ
り、実装時に発生するクラック、界面すきまを著しく低
減し、耐湿性劣化を防止することができる。なお、半導
体素子搭載部を有さないものであればどのような樹脂封
止型半導体装置でも構わない。また、絶縁膜はシリコン
酸化膜（Ｓｉ（ｈ）、シリコン窒化膜（ＳｉｘＮ４）、
シリコン酸化窒化膜（Ｓｉ、○アＮ８）、リンシリケー
トガラス膜（Ｐ Ｓ Ｇ）、ポロンシリケートガラス膜
（Ｂ Ｓ Ｇ）、ポロンリンシリケートガラス膜（ＢＰ
ＳＧ）あるいは酸化アルミニウム膜（ＡＡ□０．）の単
相膜あるいは多層膜を用いることが出来る。One example is a method of forming a film. As mentioned above, by eliminating the semiconductor element mounting part and covering the contact surface with the sealing resin with a SiO2 film that has good adhesion to the sealing resin, cracks that occur during mounting can be avoided, and the interface It is possible to significantly reduce gaps and prevent deterioration of moisture resistance. Note that any resin-sealed semiconductor device may be used as long as it does not have a semiconductor element mounting portion. In addition, the insulating film is a silicon oxide film (Si(h)), a silicon nitride film (SixN4),
Silicon oxynitride film (Si, ○AN8), phosphorus silicate glass film (P S G), poron silicate glass film (B S G), poron phosphorus silicate glass film (BP
A single phase film or a multilayer film of an aluminum oxide film (AA□0.) or an aluminum oxide film (AA□0.) can be used.
そして、低温・短時間・常圧下で形成されるピンホール
のない均質な膜であれば膜厚、膜種に依らず、どのよう
な手法で形成しても構わない。As long as it is a homogeneous film without pinholes that is formed at low temperature, short time, and normal pressure, any method may be used regardless of the film thickness and film type.
以上説明したように本発明は、半導体素子を搭載する半
導体素子搭載部を取り除き、さらに、封止樹脂との接触
面を、封止樹脂と密着性の良好な絶縁膜で被覆すること
により、実装時の熱衝撃で特に発生しやすいクラック、
界面すきまを著しく低減し、Ａｕ線切れや実装不良をな
くすことができる。As explained above, the present invention eliminates the semiconductor element mounting part on which the semiconductor element is mounted, and further covers the contact surface with the sealing resin with an insulating film that has good adhesion to the sealing resin. Cracks that are particularly likely to occur due to thermal shock during
It is possible to significantly reduce the interface gap and eliminate Au wire breakage and mounting defects.
更にボンディング後のＡρパッド部も絶縁膜で被覆され
ることにより、水分・不純物によるＡｕパッド部の腐食
を抑制し、半導体装置の耐湿性劣化を防止して高品質を
維持できる効果がある。Further, since the Aρ pad portion after bonding is also covered with an insulating film, corrosion of the Au pad portion due to moisture and impurities is suppressed, and moisture resistance deterioration of the semiconductor device is prevented to maintain high quality.
第１図（ａ）は本発明の第１の実施例である樹脂封止型
半導体装置の断面図、第１図（ｂ）は該第１の実施例の
ボンディング直後の平面図、第２図（ａ）は本発明の第
２の実施例の樹脂封止型半導体装置の断面図、第２図（
ｂ）は該第２の実施例のポンディング直後の断面図、第
３図（ａ）は従来の樹脂封止型半導体装置の断面図、第
３図（ｂ）は該従来例のポンディング直後の平面図であ
る。
１１．２１．３１・・・・・・半導体素子、１２，２２
゜３２・・・・・・Ａρパッド部、１３，２３．３３・
・・・・・パッジベージ３ン膜、１４，２４，３４・・
・・・・Ａｕ線、１５，２５．３５・・・・・・外部リ
ード、１６，２６゜３６・・・・・・内部リード、１７
，２７．３７・・・・・・リードフレーム、１８，２８
．３８・・・・・・封止樹脂、３９・・・・・・半導体
素子搭載部、３１０・・・・・・Ａｇペースト、１１１
・・・・・・絶縁ペース）、１１２，２１２・・・・・
・絶縁被膜、２１３・・・・・・支持台。
代理人 弁理士 内 原 音
（ｌジ
、筋１図
ど３ ？？
（ｂ）
万２国FIG. 1(a) is a sectional view of a resin-sealed semiconductor device according to a first embodiment of the present invention, FIG. 1(b) is a plan view of the first embodiment immediately after bonding, and FIG. (a) is a sectional view of a resin-sealed semiconductor device according to a second embodiment of the present invention;
b) is a sectional view of the second embodiment immediately after bonding, FIG. 3(a) is a sectional view of a conventional resin-sealed semiconductor device, and FIG. 3(b) is a sectional view of the conventional example immediately after bonding. FIG. 11.21.31...Semiconductor element, 12,22
゜32...Aρ pad part, 13,23.33.
...Padgebage 3-inch membrane, 14, 24, 34...
...Au wire, 15,25.35...External lead, 16,26゜36...Internal lead, 17
,27.37...Lead frame, 18,28
．． 38...Sealing resin, 39...Semiconductor element mounting part, 310...Ag paste, 111
...Insulating pace), 112,212...
- Insulating coating, 213... Support stand. Agent Patent Attorney Oto Uchihara
Claims (1)
ードと半導体素子がワイヤボンディングされ、前記半導
体素子とボンディングワイヤ及び内部リードの表面が絶
縁膜で被覆され、かつ、前記絶縁膜表面が全て樹脂で封
止されていることを特徴とする樹脂封止型半導体装置。An internal lead of a lead frame that does not have a semiconductor element mounting portion and a semiconductor element are wire-bonded, the surfaces of the semiconductor element, the bonding wire, and the internal lead are covered with an insulating film, and the entire surface of the insulating film is sealed with resin. A resin-sealed semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP88113188A JPH01282844A (en) | 1988-05-09 | 1988-05-09 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP88113188A JPH01282844A (en) | 1988-05-09 | 1988-05-09 | Resin-sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01282844A true JPH01282844A (en) | 1989-11-14 |
Family
ID=14605785
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP88113188A Pending JPH01282844A (en) | 1988-05-09 | 1988-05-09 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01282844A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5448106A (en) * | 1991-08-20 | 1995-09-05 | Kabushiki Kaisha Toshiba | Thin semiconductor integrated circuit device assembly |
| TWI387123B (en) * | 2005-01-05 | 2013-02-21 | Stanley Electric Co Ltd | Surface mounted LEDs |
| JP2014158052A (en) * | 2009-01-30 | 2014-08-28 | Nichia Chem Ind Ltd | Light emitting device and method of manufacturing the same |
| US9525115B2 (en) | 2009-01-30 | 2016-12-20 | Nichia Corporation | Light emitting device |
-
1988
- 1988-05-09 JP JP88113188A patent/JPH01282844A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5448106A (en) * | 1991-08-20 | 1995-09-05 | Kabushiki Kaisha Toshiba | Thin semiconductor integrated circuit device assembly |
| TWI387123B (en) * | 2005-01-05 | 2013-02-21 | Stanley Electric Co Ltd | Surface mounted LEDs |
| JP2014158052A (en) * | 2009-01-30 | 2014-08-28 | Nichia Chem Ind Ltd | Light emitting device and method of manufacturing the same |
| US9525115B2 (en) | 2009-01-30 | 2016-12-20 | Nichia Corporation | Light emitting device |
| US10319888B2 (en) | 2009-01-30 | 2019-06-11 | Nichia Corporation | Method of manufacturing light emitting device |
| US10505089B2 (en) | 2009-01-30 | 2019-12-10 | Nichia Corporation | Method of manufacturing light emitting device |
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