JPH01187954A - Resin seal type semiconductor device - Google Patents
Resin seal type semiconductor deviceInfo
- Publication number
- JPH01187954A JPH01187954A JP1296988A JP1296988A JPH01187954A JP H01187954 A JPH01187954 A JP H01187954A JP 1296988 A JP1296988 A JP 1296988A JP 1296988 A JP1296988 A JP 1296988A JP H01187954 A JPH01187954 A JP H01187954A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- tab
- resin
- semiconductor device
- thin layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 239000011347 resin Substances 0.000 title abstract description 17
- 229920005989 resin Polymers 0.000 title abstract description 17
- 230000008646 thermal stress Effects 0.000 abstract description 6
- 230000001681 protective effect Effects 0.000 abstract description 5
- 229910000679 solder Inorganic materials 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract description 2
- 229920001721 polyimide Polymers 0.000 abstract description 2
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 238000007789 sealing Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は樹脂封止型半導体装置のチップ搭載タブの構造
に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to the structure of a chip mounting tab for a resin-sealed semiconductor device.
従来の技術
従来の樹脂封止型半導体装置のチップ搭載タブ構造につ
いて第３図、第４図の内部平面図、断面図を用いて説明
する。各図において、樹脂封止型半導体装置の構造は、
チップ搭載タブ１の上面に搭載したチップ２に設けられ
た電極３がリードフレーム４と金属細線５により電気的
に接続された形で外囲樹脂６により封止されている。2. Description of the Related Art A chip mounting tab structure of a conventional resin-sealed semiconductor device will be described with reference to internal plan views and cross-sectional views shown in FIGS. 3 and 4. In each figure, the structure of the resin-sealed semiconductor device is
An electrode 3 provided on a chip 2 mounted on the upper surface of the chip mounting tab 1 is electrically connected to a lead frame 4 by a thin metal wire 5 and sealed with an outer resin 6.
したがってチップ表面７全体が樹脂と接触している構造
となっている。Therefore, the entire chip surface 7 is in contact with the resin.
発明が解決しようとする課題
半導体装置のプリント基板などへの実装方法は、自動化
が進み、昨今ではハンダリフロー、ハンダデイツプ等の
方法が広く用いられるようになってきた。Problems to be Solved by the Invention Methods for mounting semiconductor devices onto printed circuit boards have become increasingly automated, and methods such as solder reflow and solder dip have recently come into widespread use.
しかし、このような方法は半導体装置を急激な温度変化
にさらすことになり、特に樹脂封止型半導体装置の場合
、樹脂の線膨張係数がチップに比べて大きいために、チ
ップ表面に樹脂の熱応力が加わりやすい。このためチッ
プ表面保護膜にクラックが発生することによりそこから
水分が進入し、リークなどによる半導体装置の性能劣化
や、場合によっては、アルミ配線パターンの腐食断線な
どが発生するという問題があった。However, such a method exposes the semiconductor device to rapid temperature changes, and in the case of resin-sealed semiconductor devices in particular, the coefficient of linear expansion of the resin is larger than that of the chip, so the heat of the resin is applied to the chip surface. Easy to apply stress. For this reason, cracks occur in the chip surface protective film, allowing moisture to enter through the cracks, resulting in deterioration of the performance of the semiconductor device due to leakage, and in some cases, corrosion and breakage of the aluminum wiring pattern.
本発明はかかる点に鑑みてなされたもので、チップ表面
に加わる樹脂の熱応力ストレスに起因する信頼性の低下
を防止することを目的としている。The present invention has been made in view of this point, and an object of the present invention is to prevent a decrease in reliability due to thermal stress of the resin applied to the chip surface.
課題を解決するための手段
本発明は、上記課題を解決するため、チップ搭載タブを
チップ上面に設け、かつ、前記チップとの間に絶縁性薄
層体を介在させて外囲樹脂封止したものである。Means for Solving the Problems In order to solve the above problems, the present invention provides a chip mounting tab on the top surface of the chip, and an insulating thin layer interposed between the chip and the outer resin seal. It is something.
作用
本発明により、直接チップ表面に加わる樹脂の熱応力ス
トレスが減少することによってチップ表面保護膜にクラ
ックが発生しにくくなる。Effect: According to the present invention, the thermal stress of the resin directly applied to the chip surface is reduced, so that cracks are less likely to occur in the chip surface protective film.
実施例 次に本発明を実施例により説明する。Example Next, the present invention will be explained by examples.
第１図は、本発明による樹脂封止型半導体装置の内部平
面図、第２図はその断面図である。FIG. 1 is an internal plan view of a resin-sealed semiconductor device according to the present invention, and FIG. 2 is a sectional view thereof.
チップ２の上面にチップ搭載タブ８が設けられ、前記チ
ップ２との間に絶縁性薄層体９（たとえばポリイミドフ
ィルム）を介在させ、強固に相互接着がなされた構造に
なっている。A chip mounting tab 8 is provided on the top surface of the chip 2, and an insulating thin layer 9 (for example, a polyimide film) is interposed between the chip 2 and the chip 2, so that the tab 8 is firmly bonded to the chip 2.
ここで本実施例では金属細線５によるリードフレーム４
とチップ上電極３との電気的接続はチップ２を絶縁性薄
層体９を用いてチップ搭載タブ８に強固に固着させたの
ちに行い、その後、外囲樹脂６で封止している。Here, in this embodiment, the lead frame 4 is made of thin metal wires 5.
The electrical connection between the chip 2 and the on-chip electrode 3 is made after the chip 2 is firmly fixed to the chip mounting tab 8 using an insulating thin layer 9, and then sealed with the surrounding resin 6.
このような構造にすることにより直接チップに加わるは
ずの樹脂の熱応力ストレスはチップ搭載タブに吸収され
ることによりチップ表面に加わりに（くなった。これに
より、チップ表面保護膜のクラックの発生は減少し、信
頼性を著しく向上させることができた。With this structure, the thermal stress of the resin that would have been applied directly to the chip is absorbed by the chip mounting tab and is no longer applied to the chip surface.This reduces the possibility of cracks in the chip surface protective film. was reduced, significantly improving reliability.
なお本実施例では、デュアルインラインパッケージ（Ｄ
ＩＰ）型の樹脂封止型半導体装置を用いて説明したが、
フラットパッケージ、スモールアウトラインパッケージ
（ＳＯＰ）などあらゆる樹脂封圧型パッケージに適用可
能なことは言うまでもない。Note that in this example, a dual inline package (D
Although the explanation was made using an IP) type resin-sealed semiconductor device,
Needless to say, the present invention is applicable to all resin-sealed packages such as flat packages and small outline packages (SOP).
発明の効果
以上述べたように、本発明の樹脂封止型半導体装置によ
ると、チップ搭載タブを同チップ上面に配設した構造に
変えることより、たとえば、同半導体装置のプリント基
板へのハンダ実装時に問題となっていた樹脂の熱応力ス
トレスに起因するチップ表面保護膜のクラックの発生を
減少させ、信頼性を大幅に向上させることができた。Effects of the Invention As described above, according to the resin-sealed semiconductor device of the present invention, by changing the structure to a structure in which the chip mounting tab is disposed on the top surface of the chip, it is possible, for example, to solder-mount the semiconductor device onto a printed circuit board. We were able to reduce the occurrence of cracks in the chip surface protective film caused by the thermal stress of the resin, which was sometimes a problem, and significantly improve reliability.
第１図、第２図は本発明の実施例の平面図、断面図、第
３図、第４図は従来装置の概要を示す平面図、断面図で
ある。
１・・・・・・チップ搭載タブ、２・・・・・・チップ
、３・・・・・・チップ上電極、４・・・・・・リード
フレーム、５・・・・・・金属細線、６・・・・・・外
囲樹脂、７・・・・・・チップ表面、８・・・・・・チ
ップ搭載タブ、９・・・・・・絶縁性薄層体。
代理人の氏名 弁理士 中尾敏男 ばか１名第１図1 and 2 are a plan view and a sectional view of an embodiment of the present invention, and FIGS. 3 and 4 are a plan view and a sectional view showing an outline of a conventional device. 1... Chip mounting tab, 2... Chip, 3... Electrode on chip, 4... Lead frame, 5... Fine metal wire , 6... Surrounding resin, 7... Chip surface, 8... Chip mounting tab, 9... Insulating thin layer body. Name of agent: Patent attorney Toshio Nakao One idiot Figure 1
Claims (1)
上面に設け、かつ、前記半導体チップとの間に絶縁性薄
層体を介在させた構造を特徴とする樹脂封止型半導体装
置。A resin-sealed semiconductor device characterized by a structure in which a chip mounting tab of the resin-sealed semiconductor device is provided on the upper surface of the semiconductor chip, and an insulating thin layer is interposed between the chip mounting tab and the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1296988A JPH01187954A (en) | 1988-01-22 | 1988-01-22 | Resin seal type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1296988A JPH01187954A (en) | 1988-01-22 | 1988-01-22 | Resin seal type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01187954A true JPH01187954A (en) | 1989-07-27 |
Family
ID=11820062
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1296988A Pending JPH01187954A (en) | 1988-01-22 | 1988-01-22 | Resin seal type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01187954A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01286342A (en) * | 1988-05-12 | 1989-11-17 | Hitachi Ltd | Surface mounting ultrathin type semiconductor device |
| JPH0697353A (en) * | 1992-09-17 | 1994-04-08 | Sharp Corp | Semiconductor device and manufacture thereof |
-
1988
- 1988-01-22 JP JP1296988A patent/JPH01187954A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01286342A (en) * | 1988-05-12 | 1989-11-17 | Hitachi Ltd | Surface mounting ultrathin type semiconductor device |
| JPH0697353A (en) * | 1992-09-17 | 1994-04-08 | Sharp Corp | Semiconductor device and manufacture thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7443022B2 (en) | Board-on-chip packages | |
| JP2001036000A (en) | Chip size stack package and manufacture therefor | |
| JPH06302653A (en) | Semiconductor device | |
| US5841183A (en) | Chip resistor having insulating body with a continuous resistance layer and semiconductor device | |
| KR960005039B1 (en) | Semiconductor device | |
| JPH01187954A (en) | Resin seal type semiconductor device | |
| JP4038021B2 (en) | Manufacturing method of semiconductor device | |
| JP3153809B2 (en) | Semiconductor device | |
| JPH05160304A (en) | Semiconductor device | |
| JPS63248155A (en) | Semiconductor device | |
| JP3337526B2 (en) | Structure of package type semiconductor parts | |
| JPS6386461A (en) | Resin sealed semiconductor device | |
| JP3016380B2 (en) | Semiconductor device | |
| JP2802959B2 (en) | Semiconductor chip sealing method | |
| JPS6236385B2 (en) | ||
| KR20210131139A (en) | Method for fabricating semiconductor having double-sided substrate | |
| JPH01187959A (en) | Resin seal type semiconductor device | |
| JPS6193654A (en) | Resin sealed type semiconductor device | |
| JPH08279585A (en) | Lead frame and its semiconductor device | |
| JPH0243758A (en) | Resin sealed type semiconductor element | |
| JPH0547835A (en) | Mounting structure of semiconductor device | |
| JPH0661379A (en) | Semiconductor device | |
| JPH05218271A (en) | Ic package | |
| JPH03109757A (en) | Resin-sealed semiconductor device | |
| JPS6118157A (en) | Semiconductor device |