JPH05160304A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05160304A JPH05160304A JP32262891A JP32262891A JPH05160304A JP H05160304 A JPH05160304 A JP H05160304A JP 32262891 A JP32262891 A JP 32262891A JP 32262891 A JP32262891 A JP 32262891A JP H05160304 A JPH05160304 A JP H05160304A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- semiconductor device
- aluminum oxide
- oxide layer
- lead terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体チップとリード
端子とを金属板に固着する半導体装置に係わり、特に半
導体チップとリード端子間の熱抵抗を低くしたものに関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor chip and a lead terminal are fixed to a metal plate, and more particularly to a semiconductor device having a low thermal resistance between the semiconductor chip and the lead terminal.
【０００２】[0002]
【従来の技術】半導体チップは電源電圧を加えて動作さ
せると発熱する。この熱を発散させるための従来の半導
体装置の構造は例えば図５のようなものがある。この半
導体装置において、半導体チップ10は銅板11上に接着剤
12により接着されている。この銅板11とリード端子13，
13，…とは図示していない接着剤が両面に塗布されてい
るポリィミド・テープ14によって接着されている。そし
て、この半導体チップ10上に形成されている図示してい
ない複数の電極とリード端子13，13，…とが、それぞれ
金属細線15，15，…とによって接続されている。そし
て、この半導体チップ10と銅板11とリード端子13，13，
…のインナー・リード部および金属細線15，15，…とは
樹脂16によって封止され、パッケージ化している。2. Description of the Related Art A semiconductor chip generates heat when operated by applying a power supply voltage. The structure of a conventional semiconductor device for dissipating this heat is, for example, as shown in FIG. In this semiconductor device, the semiconductor chip 10 has an adhesive on the copper plate 11.
Bonded by 12. This copper plate 11 and lead terminal 13,
, 13 ... Are adhered by a polyimide tape 14 coated on both sides with an adhesive (not shown). Then, a plurality of electrodes (not shown) formed on the semiconductor chip 10 and the lead terminals 13, 13, ... Are connected to the thin metal wires 15, 15 ,. Then, the semiconductor chip 10, the copper plate 11, the lead terminals 13, 13,
The inner lead portion and the thin metal wires 15, 15, ... Are sealed with resin 16 and packaged.
【０００３】上記半導体チップ10が発生する熱の大半は
接着剤12を介して銅板11へ伝わり、銅板11からポリィミ
ド・テープ14を介してリード端子13へと伝わる経路で半
導体装置の外部へ放熱される。このポリィミド・テープ
14は銅板11とリード端子13との電気的絶縁の確保のため
に使用されているが、熱抵抗が大きく上記経路による放
熱特性を悪くしている。また、このポリィミド・テープ
14は２度の打ち抜き工程により成形されているので製造
工程が増え、製造価格が高価になるという問題がある。Most of the heat generated by the semiconductor chip 10 is transmitted to the copper plate 11 via the adhesive 12, and is radiated to the outside of the semiconductor device through the route from the copper plate 11 to the lead terminal 13 via the polyimide tape 14. It This Polyimide tape
Although 14 is used for ensuring electrical insulation between the copper plate 11 and the lead terminal 13, it has a large thermal resistance and deteriorates the heat dissipation characteristics through the above path. Also, this polyimide tape
Since 14 is formed by two punching steps, there is a problem that the number of manufacturing steps increases and the manufacturing cost becomes expensive.
【０００４】[0004]
【発明が解決しようとする課題】いま、上記経路による
放熱特性を改善する場合、経路上で最も熱抵抗の大きい
ポリィミド・テープ14の厚さを薄くすることが効果的で
ある。しかし、ポリィミド・テープ14の厚さは従来２０
μｍ程度に加工されており、さらに薄く加工することは
困難である。この発明は上記のような事情を考慮してな
されたものであり、その目的は従来よりも放熱特性のよ
い半導体装置を提供することである。In order to improve the heat dissipation characteristics of the above route, it is effective to reduce the thickness of the polyimide tape 14 having the highest heat resistance on the route. However, the thickness of the polyimide tape 14 is 20
Since it is processed to about μm, it is difficult to process it thinner. The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a semiconductor device having better heat dissipation characteristics than ever before.
【０００５】[0005]
【課題を解決するための手段】この発明による半導体装
置は表面に酸化アルミニウム層が形成されているアルミ
ニウム板と、上記酸化アルミニウム層に固着される半導
体チップと、上記酸化アルミニウム層に固着されるリー
ド端子と、上記半導体チップ上に形成された電極と上記
リード端子とを接続する金属細線とを具備することを特
徴とする。A semiconductor device according to the present invention comprises an aluminum plate having an aluminum oxide layer formed on its surface, a semiconductor chip fixed to the aluminum oxide layer, and leads fixed to the aluminum oxide layer. It is characterized by comprising a terminal and a thin metal wire connecting the electrode formed on the semiconductor chip and the lead terminal.
【０００６】[0006]
【作用】半導体チップとリード端子間の熱抵抗が従来の
半導体装置に比べ小さくなる。The thermal resistance between the semiconductor chip and the lead terminal becomes smaller than that of the conventional semiconductor device.
【０００７】[0007]
【実施例】以下、図面を参照してこの発明を実施例によ
り説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings.
【０００８】図１は本発明の第１の実施例に係る半導体
装置の断面図である。図において、アルミニウム板17の
上面にはアルマイト処理により酸化アルミニウム層18が
形成されている。この酸化アルミニウム層18上に半導体
チップ10が接着剤12により接着されている。さらに、酸
化アルミニウム層18上には接着剤19によりリード端子1
3，13，…が接着されている。そして、半導体チップ10
上に形成されている図示していない複数の電極とリード
端子13，13，…は金属細線15，15，…により接続されて
いる。そして、半導体チップ10と金属細線15，15，…と
アルミニウム板17およびリード端子13，13，…のインナ
ー・リード部とは樹脂16により封止され、パッケージ化
している。FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention. In the figure, an aluminum oxide layer 18 is formed on the upper surface of an aluminum plate 17 by alumite treatment. The semiconductor chip 10 is adhered onto the aluminum oxide layer 18 with an adhesive 12. Further, the lead terminal 1 is provided on the aluminum oxide layer 18 with an adhesive 19.
3, 13, ... Are glued together. And the semiconductor chip 10
The plurality of electrodes (not shown) formed above and the lead terminals 13, 13, ... Are connected by the thin metal wires 15, 15 ,. The semiconductor chip 10, the thin metal wires 15, 15, ..., The aluminum plate 17 and the inner lead portions of the lead terminals 13, 13, ... Are sealed with resin 16 to form a package.
【０００９】上記実施例による半導体装置では、半導体
チップ10が発生する熱の大半は接着剤12と酸化アルミニ
ウム層18を介してアルミニウム板17へ伝わり、酸化アル
ミニウム層18と接着剤19を介してリード端子13，13，…
へ伝わる経路で半導体装置の外部へと放熱される。この
放熱経路上にはポリィミド・テープのように熱抵抗の大
きい部材を用いていないので半導体チップとリード端子
間の熱抵抗を下げることができ、放熱特性を向上させる
ことができる。また、ポリィミド・テープを使用しない
ことにより打ち抜き工程を削減することができるので製
造価格を低減させることができる。In the semiconductor device according to the above-described embodiment, most of the heat generated by the semiconductor chip 10 is transmitted to the aluminum plate 17 via the adhesive 12 and the aluminum oxide layer 18, and is lead via the aluminum oxide layer 18 and the adhesive 19. Terminals 13, 13, ...
Heat is radiated to the outside of the semiconductor device through the path transmitted to the semiconductor device. Since a member having a high thermal resistance such as a polyimide tape is not used on this heat dissipation path, the heat resistance between the semiconductor chip and the lead terminal can be reduced, and the heat dissipation characteristics can be improved. Moreover, since the punching process can be omitted by not using the polyimide tape, the manufacturing cost can be reduced.
【００１０】図２は第２の実施例に係る半導体装置の断
面図である。上記第１の実施例では上面に酸化アルミニ
ウム層18が形成されているアルミニウム板17を半導体チ
ップ10の下面に接着している。しかし、この実施例の場
合には下面に酸化アルミニウム層20，20，…が形成され
ているアルミニウム板21を半導体チップ10の下面よりも
発熱量の多い上面に接着するようにしたものである。こ
のアルミニウム板21は酸化アルミニウム層20，20，…を
介してリード端子13，13，…それぞれの上面に接着剤22
によって接着され、さらに酸化アルミニウム層20を介し
て半導体チップ10の上面に接着剤23によって接着されて
いる。他の構成は上記第１の実施例と同様である。FIG. 2 is a sectional view of a semiconductor device according to the second embodiment. In the first embodiment, the aluminum plate 17 having the aluminum oxide layer 18 formed on the upper surface is bonded to the lower surface of the semiconductor chip 10. However, in the case of this embodiment, the aluminum plate 21 having the aluminum oxide layers 20, 20, ... Formed on the lower surface thereof is bonded to the upper surface of the semiconductor chip 10 which generates more heat than the lower surface. The aluminum plate 21 has an adhesive 22 on the upper surface of each of the lead terminals 13, 13, ... Through the aluminum oxide layers 20, 20 ,.
And is further bonded to the upper surface of the semiconductor chip 10 with an adhesive 23 via the aluminum oxide layer 20. The other structure is similar to that of the first embodiment.
【００１１】この実施例の場合も上記第１の実施例の場
合と同様に、熱抵抗の大きいポリィミド・テープを使用
せず、半導体チップとリード端子間の熱抵抗を低下させ
ている。In the case of this embodiment, as in the case of the first embodiment, the polyimide tape having a large thermal resistance is not used, and the thermal resistance between the semiconductor chip and the lead terminal is reduced.
【００１２】図３は第３の実施例に係る半導体装置の断
面図である。この実施例では上記第１の実施例の半導体
装置の半導体チップ10の上面にさらに上記第２の実施例
と同様にアルミニウム板21を接着したものである。FIG. 3 is a sectional view of a semiconductor device according to the third embodiment. In this embodiment, an aluminum plate 21 is further adhered to the upper surface of the semiconductor chip 10 of the semiconductor device of the first embodiment as in the second embodiment.
【００１３】この実施例では半導体チップとリード端子
とが２枚のアルミニウム板で固定されるため、上記第１
及び第２の実施例よりも半導体チップとリード端子間と
の熱抵抗が小さい半導体装置が得られる。In this embodiment, since the semiconductor chip and the lead terminal are fixed by the two aluminum plates, the first
Also, a semiconductor device having a smaller thermal resistance between the semiconductor chip and the lead terminals than in the second embodiment can be obtained.
【００１４】図４は第４の実施例に係る半導体装置の断
面図である。上記第３の実施例ではリード端子13，13，
…の間にできる隙間は樹脂16による封止を行うことによ
り、埋められている。しかし、この実施例では上記隙間
が接着剤19，22により埋められ、半導体チップ10がアル
ミニウム板17，21とリード端子13，13，…により気密封
止されており、樹脂による封止は行われていない。他の
構成は上記第３の実施例と同様である。FIG. 4 is a sectional view of a semiconductor device according to the fourth embodiment. In the third embodiment, the lead terminals 13, 13,
The gap formed between ... Is filled by sealing with the resin 16. However, in this embodiment, the gap is filled with the adhesives 19 and 22, and the semiconductor chip 10 is hermetically sealed by the aluminum plates 17 and 21 and the lead terminals 13, 13, ... Not not. The other structure is similar to that of the third embodiment.
【００１５】この実施例では上記第３の実施例同様に半
導体チップとリード端子間の熱抵抗を下げることがで
き、さらに樹脂による封止を行わないので製造価格を低
減させることができる。In this embodiment, the thermal resistance between the semiconductor chip and the lead terminal can be reduced as in the third embodiment, and the manufacturing cost can be reduced because no resin encapsulation is performed.
【００１６】[0016]
【発明の効果】以上、説明したようにこの発明によれ
ば、従来よりも放熱特性のよい半導体装置を提供するこ
とができる。As described above, according to the present invention, it is possible to provide a semiconductor device having better heat dissipation characteristics than ever before.
【図１】この発明の第１の実施例に係わる半導体装置の
断面図。FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.
【図２】この発明の第２の実施例に係わる半導体装置の
断面図。FIG. 2 is a sectional view of a semiconductor device according to a second embodiment of the present invention.
【図３】この発明の第３の実施例に係わる半導体装置の
断面図。FIG. 3 is a sectional view of a semiconductor device according to a third embodiment of the present invention.
【図４】この発明の第４の実施例に係わる半導体装置の
断面図。FIG. 4 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.
【図５】従来の半導体装置の断面図。FIG. 5 is a sectional view of a conventional semiconductor device.
10…半導体チップ、11…銅板、12，19，22，23…接着
剤、13…リード端子、14…ポリィミド・テープ、15…金
属細線、16…樹脂、17，21…アルミニウム板、18，20…
酸化アルミニウム層。10 ... Semiconductor chip, 11 ... Copper plate, 12, 19, 22, 23 ... Adhesive, 13 ... Lead terminal, 14 ... Polyimide tape, 15 ... Fine metal wire, 16 ... Resin, 17, 21 ... Aluminum plate, 18, 20 …
Aluminum oxide layer.
Claims (1)
いるアルミニウム板と、 上記酸化アルミニウム層に固着される半導体チップと、 上記酸化アルミニウム層に固着されるリード端子と、 上記半導体チップ上に形成された電極と上記リード端子
とを接続する金属細線とを具備することを特徴とする半
導体装置。1. An aluminum plate having an aluminum oxide layer formed on a surface thereof, a semiconductor chip fixed to the aluminum oxide layer, lead terminals fixed to the aluminum oxide layer, and a semiconductor chip formed on the semiconductor chip. And a thin metal wire that connects the electrode and the lead terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32262891A JPH05160304A (en) | 1991-12-06 | 1991-12-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32262891A JPH05160304A (en) | 1991-12-06 | 1991-12-06 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05160304A true JPH05160304A (en) | 1993-06-25 |
Family
ID=18145839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32262891A Pending JPH05160304A (en) | 1991-12-06 | 1991-12-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05160304A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0658935A3 (en) * | 1993-12-16 | 1996-07-10 | Seiko Epson Corp | Resin sealing type semiconductor device and method of making the same. |
| EP0690501A3 (en) * | 1994-07-01 | 1997-03-26 | Saint Gobain Norton Ind Cerami | Integrated circuit package with diamond heat sink |
| US6661081B2 (en) | 2000-10-20 | 2003-12-09 | Hitachi, Ltd. | Semiconductor device and its manufacturing method |
| US6812064B2 (en) * | 2001-11-07 | 2004-11-02 | Micron Technology, Inc. | Ozone treatment of a ground semiconductor die to improve adhesive bonding to a substrate |
| JP2009124082A (en) * | 2007-11-19 | 2009-06-04 | Mitsubishi Electric Corp | Semiconductor device for power |
-
1991
- 1991-12-06 JP JP32262891A patent/JPH05160304A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5891759A (en) * | 1993-12-16 | 1999-04-06 | Seiko Epson Corporation | Method of making a multiple heat sink resin sealing type semiconductor device |
| US5594282A (en) * | 1993-12-16 | 1997-01-14 | Seiko Epson Corporation | Resin sealing type semiconductor device and method of making the same |
| EP0658935A3 (en) * | 1993-12-16 | 1996-07-10 | Seiko Epson Corp | Resin sealing type semiconductor device and method of making the same. |
| KR100296664B1 (en) * | 1993-12-16 | 2001-10-24 | 구사마 사부로 | Resin-encapsulated semiconductor device and manufacturing method thereof |
| US6466446B1 (en) | 1994-07-01 | 2002-10-15 | Saint Gobain/Norton Industrial Ceramics Corporation | Integrated circuit package with diamond heat sink |
| US5696665A (en) * | 1994-07-01 | 1997-12-09 | Saint-Gobain/Norton Industrial Ceramics Corporation | Integrated circuit package with diamond heat sink |
| EP0690501A3 (en) * | 1994-07-01 | 1997-03-26 | Saint Gobain Norton Ind Cerami | Integrated circuit package with diamond heat sink |
| KR100405845B1 (en) * | 1994-07-01 | 2004-03-18 | 쌩 고벵/노튼 인더스트리얼 세라믹스 코포레이션 | Integrated Circuit Package with Diamond Heatsink |
| US6661081B2 (en) | 2000-10-20 | 2003-12-09 | Hitachi, Ltd. | Semiconductor device and its manufacturing method |
| US6962836B2 (en) | 2000-10-20 | 2005-11-08 | Renesas Technology Corp. | Method of manufacturing a semiconductor device having leads stabilized during die mounting |
| US6812064B2 (en) * | 2001-11-07 | 2004-11-02 | Micron Technology, Inc. | Ozone treatment of a ground semiconductor die to improve adhesive bonding to a substrate |
| US7170184B2 (en) | 2001-11-07 | 2007-01-30 | Micron Technology, Inc. | Treatment of a ground semiconductor die to improve adhesive bonding to a substrate |
| JP2009124082A (en) * | 2007-11-19 | 2009-06-04 | Mitsubishi Electric Corp | Semiconductor device for power |
| JP4531087B2 (en) * | 2007-11-19 | 2010-08-25 | 三菱電機株式会社 | Power semiconductor device |
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