TW202040707A - Semiconductor element package structure and method - Google Patents

Abstract

A semiconductor element package structure, comprising a first and a second semiconductor elements each having a first electrode and a second electrode arranged on a top surface and a bottom surface of the semiconductor elements, respectively; first substrate, on which a second electrode of the first semiconductor element and a first electrode of the second semiconductor element are respectively connected; second substrate and third substrate in connection with the other electrodes of the two semiconductor elements; wherein the outer surface of the second and third substrates position substantially in the same level; and insulator filled in a space between the first substrate and the second and third substrates. The polarity of the first and second electrodes may be the same or different.

Description

Semiconductor element packaging structure and semiconductor element packaging method

The present invention relates to a semiconductor element packaging structure and a semiconductor element packaging method, in particular to a semiconductor element packaging structure containing many semiconductor elements, and a method for manufacturing such a semiconductor element packaging structure.

In the semiconductor component manufacturing industry, the packaging technology of semiconductor components, especially the technology used to encapsulate most semiconductor components, is an important technology. A good packaging structure can provide advantages such as reduced device volume, cost savings, simplified production, and convenient storage, transportation and application. In addition, the scalability of the semiconductor device packaging structure is a goal pursued by the industry today. Especially semiconductor components used in the fields of power supply, data storage, etc., require packaging technology that can arbitrarily reduce or increase the number of semiconductor components to match the scale required by the device.

Most semiconductor components can be packaged in a vertical stack.

Chinese utility model patent CN 204991698U discloses a "semiconductor chip integrated component". The disclosed structure includes a first lead structure, a second lead structure, and N third lead structures stacked between the two. A piece of semiconductor chip is connected between two adjacent lead structures. Such stacking becomes a semiconductor device packaging structure.

Chinese utility model patent CN 206505909U discloses a "two-chip vertical parallel diode package structure". The structure includes a lead frame composed of outer leads A and B and a mounting table, and inner leads A, B and vertically stacked first and second chips are arranged in the frame.

In addition to vertically stacked packaging structures, horizontally arranged packaging structures can also be used.

The US Patent Publication US 2004/041230 discloses a "semiconductor package with series diodes", which is used to package two series connected diodes in one power package. Wherein, the negative electrode of the first diode is electrically connected to the positive electrode of the second diode by a common conductive plate. The common conductive plate and the conductive plate connecting the remaining electrodes of the two diodes have pins extending laterally.

US Patent No. 4,047,197A discloses a "casing and wire structure of a series semiconductor rectifier configuration". Among them, two rectifiers are fixed on one side of the common metal base, and the two are electrically isolated but thermally conductive. Two rectifiers are connected into a series circuit to form a structural unit, and are accommodated in the casing. This patent uses a Z-shaped metal plate to connect two rectifiers in series.

US patent US 6,031,279A discloses a "semiconductor device for power supply", in which there are two second chips with a third vertical transistor and a fourth vertical transistor, respectively, mounted on a first chip. The first chip has two horizontally arranged first vertical transistors and second vertical transistors. The load paths of the four transistors are connected in series. The electrodes of the series circuit are connected to the lead frame by leads. The part of the lead frame exposed to the package structure forms a pin.

From the above observation of the prior art, it can be known that the semiconductor device packaging structure of the prior art attempts to package most semiconductor devices in a vertical stack or a horizontal arrangement, or even a combination of vertical stack and horizontal arrangement. However, the formed package structure requires the use of specially designed conductive plates to connect the relevant electrodes. This complicates the packaging process of the semiconductor element and increases the packaging cost. In addition, the packaging structure of the conventional technology lacks scalability. The number of semiconductor components in the package cannot be reduced or enlarged with the scale required by the system.

Therefore, there is an urgent need for a novel semiconductor device packaging technology in the industry, which can be applied to structures containing most semiconductor devices, which can reduce the device volume, save packaging costs, simplify the production process, and form a packaging structure that is convenient for storage, transportation, and application.

In addition, the industry also needs an innovative semiconductor device packaging technology that can provide a high degree of scalability and is applied to the packaging of different numbers of semiconductor devices.

The purpose of the present invention is to provide a novel semiconductor device packaging technology for packaging structures containing many semiconductor devices.

The purpose of the present invention is also to provide a semiconductor element packaging structure, which can reduce the volume of the device, save packaging costs, simplify the production process, and facilitate storage, transportation and application.

The object of the present invention is also to provide a semiconductor device packaging structure to provide a high degree of scalability, which can be used to package different numbers of semiconductor devices.

The object of the present invention is also to provide a packaging method of the above-mentioned semiconductor element packaging structure.

According to the basic design of the present invention, the semiconductor device packaging structure includes: first and second semiconductor devices, each having a first electrode and a second electrode, which are respectively disposed on the top surface and the bottom surface of the semiconductor device. The second electrode of the first semiconductor element and the first electrode of the second semiconductor element are connected to the first substrate, and the first electrode of the first semiconductor element and the second electrode of the second semiconductor element are respectively connected to the second substrate and the third Substrate. The outer surfaces of the second substrate and the third substrate are substantially on the same plane. The space between the first substrate and the second and third substrates is filled with an insulator. The so-called outer surface refers to the surface of the substrate away from the first and second semiconductor elements.

The polarity of the first electrode and the second electrode may be the same or different. For example, in the case of a bipolar semiconductor element, the top electrode and the bottom electrode of the semiconductor element have the same polarity. The first electrode and the second electrode have the same polarity.

In some embodiments of the present invention, the semiconductor device is a device containing a single semiconductor device, such as a single diode, a rectifier, a transistor, a transient voltage suppression diode (TVS), a light emitting diode, etc. Components of the device. However, in other embodiments of the present invention, the semiconductor device is a device containing a plurality of semiconductor devices, such as a semiconductor device formed by a vertical stack, a horizontal arrangement, or a vertical stack/horizontal arrangement of a plurality of semiconductor devices.

In some specific embodiments of the present invention, one of the two semiconductor elements may be a simple conductive element or a simple insulating element.

The first, second, and third substrates of the present invention are usually conductive substrates. However, in certain embodiments, at least one substrate may be an insulating substrate.

In a preferred embodiment of the present invention, at least one of the first, second, and third substrates may provide mesa-shaped protrusions. The mesa protrusion can be used to form a stable electrical contact. However, in some embodiments of the present invention, the mesa protrusion can be used to adjust the distance between the second substrate and/or the third substrate and the first substrate.

In a specific embodiment of the present invention, the semiconductor device packaging structure includes a plurality of semiconductor devices, a plurality of first substrates having the same number of semiconductor devices, and a plurality of second substrates having the same number of semiconductor devices. The plurality of semiconductor elements are respectively arranged on the plurality of first substrates, so that two adjacent semiconductor elements are connected to the first substrate with their first electrodes and second electrodes, respectively, and the plurality of second substrates are connected to the plurality of The other electrode of the semiconductor element; wherein: the distance between the first substrate and the second substrate is substantially the same; and an insulator filled between the first substrate and the second substrate, and between the first substrate and the first substrate, and The space between the second substrate and the second substrate. The polarity of the first electrode and the second electrode may be the same or different.

The design of the present invention is expandable. In some preferred embodiments, the first and second semiconductor devices are used as a unit, and the semiconductor device package structure may include a plurality of semiconductor devices. The semiconductor elements of the plurality of units can be arranged vertically, horizontally, vertically stacked, and horizontally arranged. If stacked vertically, between two vertically adjacent semiconductor elements, a conductive sheet can be provided to connect the two different electrodes. If arranged horizontally, a conductive sheet can be provided between two adjacent semiconductor elements to connect different electrodes of the two. The conductive sheet may also form a mesa-shaped protrusion.

The present invention also provides a method for packaging semiconductor elements. The method includes preparing a top substrate. A conductive material is applied on the top substrate to configure a predetermined position on the surface of the semiconductor element. Most semiconductor elements are placed on the corresponding conductive material of the top substrate, so that every two semiconductor elements are electrically connected to the top substrate with different electrodes. Prepare a bottom substrate. A conductive material is applied to a predetermined position of the base substrate. The predetermined position of the bottom substrate corresponds to the predetermined position of the top substrate. The bottom substrate and the top substrate are combined, so that the plurality of semiconductor elements contact the conductive material on the top substrate and are fixed. If necessary, heat or pressure can be applied to make the conductive material adhere to the top substrate and the bottom substrate.

Next, an insulator is filled in the space between the top substrate and the bottom substrate. The gap between the two substrates can be filled by capillary phenomenon, pressure pouring or vacuuming to form an insulating layer. A partition is formed on the base substrate so that each unit of the base substrate forms a first base substrate and a second base substrate. Wherein, each unit may include two adjacent semiconductor elements electrically connected to the top substrate with different polarities. The method of forming the partition can be a chemical etching method or a laser ablation method. If necessary, a solder resist layer can be applied to the surface of the top substrate facing away from the semiconductor element.

The above packaged structure has a large number of semiconductor package structure units. In the overall structure, in addition to filling the insulator in the space between the top substrate and the bottom substrate, an insulator can also be filled between every two bottom substrates. However, the partition can also be reserved. The package structure thus completed is suitable for storage, transportation and transaction. Finally, the structure can be cut to form a semiconductor device packaging structure of multiple units. Each unit contains two adjacent semiconductor devices electrically connected to the top substrate with different polarities.

In the above steps, the package structure forming the insulating layer can be baked at a high temperature to cure the insulating layer.

The above and other objectives and advantages of the present invention can be more clearly illustrated from the following detailed description and with reference to the following drawings.

The present invention provides a novel semiconductor element packaging structure and a semiconductor element packaging method for forming the new invention structure. Hereinafter, embodiments will be used to illustrate several preferred implementations of the semiconductor device packaging structure and semiconductor device packaging method of the present invention, so that the reader can easily understand the main technical features of the present invention. However, the description content of the embodiments shall not be used to limit the scope of the present invention. Those with considerable knowledge and skills in the industry can grasp the spirit of the present invention from the description of the embodiments and make various possible changes and extensions. These changes and extensions still belong to the patent scope of the present invention.

Example 1 FIG. 3 shows a schematic diagram of an embodiment of the semiconductor device packaging structure of the present invention. The semiconductor device packaging structure 300 shown in the figure basically has a top substrate 302, two bottom substrates 303A, 303B, and two semiconductor devices 301, namely a first semiconductor device 301A and a second semiconductor device 301B. In this basic structure, the top substrate 302 and the bottom substrates 303A and 303B are electrical conductors. The semiconductor elements 301 and 301 each include at least one semiconductor device. Each semiconductor device has a top surface first electrode and a bottom surface second electrode. The first electrode and the second electrode have opposite polarities, and the top substrate 302 is connected to the two semiconductor devices 301 in series.

Those in the industry know that the polarity of the first electrode and the second electrode can also be the same. For example, in the case of a bipolar semiconductor element, the top electrode and the bottom electrode of the semiconductor element have the same polarity. The first electrode and the second electrode have the same polarity. Therefore, in the following description of this specification, although a semiconductor element in which the first electrode and the second electrode have opposite polarities is mainly taken as an example, any bipolar semiconductor element can be applied to the present invention. In this case, if specified, in each of the embodiments, the polarity of the first electrode and the second electrode may be the same or different.

FIG. 4 shows a schematic structural diagram of a semiconductor device 301 suitable for the semiconductor device packaging structure of the present invention. As shown in the figure, the semiconductor device has a single semiconductor device 101. The semiconductor device 101 includes a top surface first electrode 111 and a bottom surface second electrode 121, and is located between the top surface first electrode 111 and the bottom surface second electrode 121, and is electrically connected to the top surface first electrode 111 And the semiconductor wafer 131 with the second electrode 121 on the bottom surface. The first electrode 111 and the second electrode 121 have opposite polarities, that is, one of them is an anode and the other is a cathode. However, if it is a bipolar device, the first electrical property and the second electrode have the same polarity. The figure also shows that there is an encapsulating material 141 on the side of the semiconductor device 101.

The semiconductor device 101 can be any semiconductor electrical or circuit device. In a preferred embodiment of the present invention, the semiconductor device 101 is a diode device, that is, the semiconductor chip 131 is simply a diode device. However, other semiconductor devices, such as rectifiers, transistors, transient voltage suppression diodes (TVS), light emitting diodes, etc., can also be applied to the present invention.

The top first electrode 111 and the bottom second electrode 121 are usually made of thin plates of conductive material. A preferred example is to plate metal films on both sides of the semiconductor wafer 131. However, other metal films of any conductive material that can be applied to the semiconductor device 101 can be applied to the present invention. The first electrode 111 on the top surface and the second electrode 121 on the bottom surface may use conductive metal films to contact and clamp the semiconductor device 101. It can also be formed by directly coating the top and bottom surfaces of the semiconductor device 101 with a conductive material paste. The sealing material 141 is usually an electrical insulating material, such as a plastic material, a resin material, a silicon-containing material, a glass material, a ceramic material, and so on. Surround the periphery of the semiconductor device 101 in a suitable manner.

The semiconductor element 301 may include many semiconductor devices. One suitable example is the stacked structure of semiconductor devices. A common semiconductor device stack structure in the industry is shown in FIG. 1. The semiconductor device stack structure 100A shown in the figure includes a plurality of (N, N is a positive integer) semiconductor devices 101A to 101N, forming a stack. Conductive adhesive materials such as solder paste 102A~102(N-1) are located between every two semiconductor devices. Each of the semiconductor devices 101A to 101N has the same structure as the semiconductor device 101 shown in FIG. 1, that is, it has a first electrode 111 on the top surface and a second electrode 121 on the bottom surface, between the first electrode 111 on the top surface and the bottom surface. Between the second electrodes 121, the semiconductor chip 131 of the top first electrode 111 and the bottom second electrode 121 and the encapsulating material 141 are electrically connected, but their circuits and functions can be the same or different. All the semiconductor devices 101A to 101N have the same polarity direction and are stacked to form a series connection. However, the stacking mode can also be arranged so that the top electrode and the bottom electrode of the stacked structure have the same polarity. The number N of semiconductor devices 101A to 101N used is not particularly limited, but considering the thickness of the semiconductor device stack structure 100A formed, the number N of semiconductor devices 101A to 101N is usually less than 10, preferably less than 5, and The thickness of the semiconductor devices 101A to 101N itself is related. In this semiconductor device stack structure, the top first electrode of the first semiconductor device 101A and the bottom second electrode of the Nth semiconductor device 101N become the top first electrode 111 and the bottom second electrode of the semiconductor device stack 100A. Two electrodes 121.

Another suitable stacked structure of semiconductor devices is shown in FIG. 2. The semiconductor device stack structure 100B shown in the figure also includes N semiconductor devices 101A to 101N, forming a stack. However, the material between every two semiconductor devices is a conductive metal plate, such as copper particles 103A~103(N-1). Each of the semiconductor devices 101A to 101N has the same structure as the semiconductor device 101 shown in FIG. 1, that is, it has a first electrode 111 on the top surface and a second electrode 121 on the bottom surface, between the first electrode 111 on the top surface and the bottom surface. Between the second electrodes 121, the semiconductor chip 131 of the top first electrode 111 and the bottom second electrode 121 and the encapsulating material 141 are electrically connected, but their circuits and functions can be the same or different. The conductive metal plates 103A~103(N-1) can directly contact the first electrodes on the top surface and the second electrodes on the bottom surface of the respective corresponding semiconductor devices 101A~101N, or through conductive adhesive materials, such as solder paste 102A~102( N-1) and 104A~104(N-1) are in contact with the first electrode on the top surface and the second electrode on the bottom surface. In this semiconductor device stack structure, the top first electrode of the first semiconductor device 101A and the bottom second electrode of the Nth semiconductor device 101N become the top first electrode 111 and the bottom second electrode of the semiconductor device stack 100B. Two electrodes 121.

In the semiconductor device stack structure 100B, the conductive adhesive material is used as a connection medium between the semiconductor device and the conductive metal plate, and the conductive metal plate can provide a buffer between the semiconductor devices and reduce the damage of the semiconductor device due to stress during the stacking process. Achieve the protection effect of semiconductor components. In addition, if the conductive metal plate is made of copper pellets, the heat dissipation effect can be improved in high current applications, and a good heat dissipation space can be provided for the heat generated when the semiconductor element is applied.

The above two semiconductor device stack structures 100A and 100B have their own advantages and disadvantages. Since the semiconductor device stack structure 100A does not use the conductive metal plate 103, the advantage is that the number of stackable semiconductor devices 101 is larger, and higher power is obtained. The disadvantage is that because the conductive metal plate 103 is not used as a stress buffer and heat dissipation medium, the semiconductor device 101 is easily damaged due to stress during the stacking process, and the heat dissipation effect is poor. Since the semiconductor device stack structure 100B is stacked through the conductive metal plate 103, it is less prone to damage due to stress during the stacking process, and has better heat dissipation. However, the disadvantage is that the number of stacks of the semiconductor device 101 is small, and higher power usage cannot be obtained.

In addition to the above-mentioned three types of semiconductor elements 301, other types or structures of semiconductor elements can be formed using the packaging method of the present invention to form the packaging structure of the present invention.

Please refer to Figure 3. In the semiconductor device packaging structure shown in FIG. 3, the top substrate 302 connects two semiconductor devices 301. That is, the polarity direction of the first semiconductor element 301A is opposite to the polarity direction of the second semiconductor element 301B (or bipolar characteristics), and the second electrode on the bottom surface of the first semiconductor element 301A and the second semiconductor element 301B The first electrodes on the top surface are in electrical contact with the top substrate 302. In addition, the first electrode on the top surface of the first semiconductor element 301A is in electrical contact with the first base substrate 303A in the base substrate, and the second electrode on the bottom surface of the second semiconductor element 301B is in contact with the second base substrate in the base substrate. 303B electrical contact. The top substrate 302 is electrically insulated from the two bottom substrates 303A and 303B, and the first bottom substrate 303A and the bottom substrate 303B are also electrically insulated. In the circuit structure formed in this way, the first base substrate 303A expresses the first polarity of the circuit, and the second base substrate 303B expresses the second polarity of the circuit. And the first base substrate 303A and the second base substrate 303B face substantially the same direction.

The top substrate 302 and the bottom substrates 303A and 303B can be made of any conductive material. Same as the foregoing, the top substrate 302 and the bottom substrates 303A and 303B can be made of thin plates of conductive material. Preferable examples include common conductive material thin plates such as copper foil and aluminum plate. However, other conductive materials that can be applied to the packaging of semiconductor elements, regardless of the form of a sheet or paste, can be applied to the present invention.

Preferably, the surfaces of the top substrate 302 and the bottom substrates 303A, 303B facing the semiconductor devices 301A, 301B form protrusions or mesa shapes, so that the contact between the substrate and the electrodes of the semiconductor devices is more stable. But the protrusion or mesa shape is not any technical limitation. In addition, it is preferable to use conductive adhesive materials, such as solder paste 102A to 102D, to fix the semiconductor elements 301A, 301B on the top substrate 302 and the bottom substrates 303A, 303B.

The spaces between the top substrate 302 and the bottom substrates 303A and 303B are filled with insulating layers 305A to 305C. The insulating layers 305A-305C can use any electrical insulating material. Preferable examples include plastic materials, resin materials, silicon-containing materials, glass materials, ceramic materials and other materials that are not conductive and flow easily before curing. It is preferably an epoxy resin material. Between the two base substrates 303A and 303B, a partition 304 is usually formed. The partition area 304 can be filled with the material of the insulating layers 305A to 305C, or can be filled with other insulating materials to make the structure more complete. But there is nothing to do without filling materials.

For application convenience, a solder mask 306 can be applied on the upper surface of the top substrate 302. The solder mask 306 can protect the top substrate 302 and prevent the top substrate 302 from forming electrical contact with other objects. The bottom substrates 303A and 303B may not be applied with a solder mask, or a solder mask may be applied on the surface as required. The solder mask is used to cover the exposed shape and shape of the first electrode and the second electrode. Therefore, the solder mask 306 Electrical insulating materials can be used. The applicable materials are as mentioned above. The solder mask 306 preferably uses an insulating material that can produce a hard surface after curing.

In the semiconductor device packaging structure described above, the top substrate 302 and the bottom substrates 303A, 303B provide electrical characteristics transfer and protect the semiconductor device or semiconductor device stack structure 301. The insulating layer can cover the semiconductor element to achieve protection functions such as isolating moisture and avoiding contact with foreign objects.

The packaging method of the semiconductor element packaging structure shown in FIG. 3 will be described below. FIG. 5 shows a method flowchart of a preferred embodiment of the semiconductor device packaging method of the present invention. This method is mainly used to manufacture the semiconductor device packaging structure as shown in FIG. 3.

As shown in the figure, in step 501, a top substrate 302 is prepared. In the mass production process, the top substrate 302 is used to support most semiconductor device packaging structural units. In this embodiment, each semiconductor device packaging structure unit includes two semiconductor devices. In step 502, conductive adhesive materials, such as solder pastes 102A and 102C, are applied on the top substrate 302 by a method such as dot attachment or printing, and used to configure predetermined positions on the surface of the semiconductor device 301. In step 503, the semiconductor device 301 is placed on the corresponding positions of the solder paste 102A and 102C to fix the semiconductor device 301 and electrically connect to the top substrate 302. At this step, it should be noted that the two semiconductor elements 301A and 301B per unit are located at the adjacent solder paste 102A and 102C points, and their polarities are opposite. However, if it is a bipolar device, there is no problem with the configuration of the polarity direction.

Next, in step 504, a base substrate is prepared. The bottom substrate is also used to support most semiconductor device packaging structural units. A conductive adhesive material, such as solder paste 102B and 102D, is applied to the predetermined position of the base substrate. The predetermined position of the bottom substrate corresponds to the predetermined position of the top substrate. In step 505, the bottom substrate and the top substrate are combined so that the individual solder paste 102B on the bottom substrate electrically contacts the first semiconductor element 301A on the top substrate, and the individual solder paste 102D on the bottom substrate electrically contacts the The second semiconductor element 301B on the top substrate is fixed. If necessary, heat or pressure can be applied to make the conductive adhesive materials 102A, 102B, 102C, and 102D firmly adhere the semiconductor elements 301A, 301B to the top substrate 302 and the bottom substrate.

In step 506, the space between the top substrate 302 and the bottom substrate is filled with insulating layers 305A, 305B, and 305C. The gap between the two substrates can be filled by capillary phenomenon, pressure pouring or vacuuming to form an insulating layer. After completion, the packaging structure with the insulating layer formed is baked in an oven to cure the insulating layer. In step 507, a partition 304 is formed on the base substrate, so that each unit of the base substrate forms a first base substrate 303A and a second base substrate 303B. The available processing method includes forming the partition 304 by a chemical etching method. After that, in step 508, a solder mask 306 is applied to the surface of the top substrate 302 facing away from the semiconductor elements 301A, 301B, and the bottom substrate 303A, 303B facing away from the surface of the semiconductor elements 301A, 301B (including the surface between the two substrates) , The solder resist layer 306 is applied as required, and the electrode shape is exposed according to the application requirement. Finally, a cutting operation is performed in step 509 to form a semiconductor device packaging structure 300 of a plurality of units, and each unit includes predetermined semiconductor devices 301A and 301B.

The semiconductor device packaging structure 300 manufactured by the above method is shown in FIG. 3. This structure is completely different from the conventional semiconductor device packaging structure. The conventional semiconductor device packaging structure includes only one semiconductor device or semiconductor device stack structure. However, the semiconductor device packaging structure of the present invention can include two semiconductor devices or semiconductor device stacked structures at the same height, so higher power wattage can be obtained. When used for stacking packaged semiconductor devices, the present invention uses a stacked structure of two semiconductor devices with a reduced number of layers, but still provides the original power capability. That is, under the same power wattage, the present invention can greatly reduce the thickness of the semiconductor device packaging structure. In addition, although the semiconductor device packaging structure of the present invention makes the structure longer, the first and second electrodes of the packaging structure have already faced substantially the same direction. If the conventional package structure is to achieve this application, conductive pins must be added. The length of the formed structure is substantially indistinguishable from the present invention.

Example 2 FIG. 6 shows a schematic structural view of a second embodiment of the semiconductor device packaging structure of the present invention. In the embodiment shown in FIG. 6, the semiconductor device packaging structure of each unit also includes two components, but the two are components of different properties. For example, it can be a semiconductor element and a conductive element.

As shown in FIG. 6, the semiconductor device packaging structure 600 of this embodiment also includes a top substrate 302 and two bottom substrates 303A and 303B. But in between are semiconductor elements 301 and conductive elements, such as pure copper particles 103. The semiconductor device packaging structure 600 also includes conductive adhesive materials used to connect the semiconductor device 301 and the conductive device to the top substrate 302 and the two bottom substrates 303A, 303B, such as solder paste 102A~102D, and separate the bottom substrates 303A and 303B. The partition 304, the insulating layers 305A to 305C filling the space between the substrates, and the solder mask 306 of the top substrate 302.

The structure shown in FIG. 6 is more suitable for a stacked structure of a semiconductor device. In other words, the semiconductor device 301 is preferably a semiconductor device stack structure, which can be a semiconductor device stack structure 100A or a semiconductor device stack structure 100B. The stacked structure of the semiconductor device has a considerable thickness. If it is applied to, for example, a surface mount method, the two electrodes must be positioned in the same direction. The conventional technology uses conductive pins to extend the upper electrode to the lower side. However, if the semiconductor element packaging structure of the present invention is used, as long as the second semiconductor element 301B in the structure shown in FIG. 3 is replaced by a conductive element, such as copper pellets 103, a semiconductor with both electrodes in the same direction can be easily completed. Component packaging structure.

The semiconductor device package structure shown in FIG. 6 is basically the same as the embodiment of FIG. 3. It is just that the second semiconductor element 301B in the structure shown in FIG. 3 is replaced with a conductive element, such as copper pellet 103. The manufacturing method of the semiconductor device packaging structure is also the same as the method steps shown in FIG. 5. However, when a large number of semiconductor elements 301 are arranged on the top substrate 302, the semiconductor elements 301 and the copper particles 103 or suitable conductive elements are arranged alternately. The details should not be repeated here.

The semiconductor device packaging structure 600 shown in FIG. 6 is completely different from the conventional semiconductor device packaging structure. The conventional technology must use a lead frame process (Lead Frame), and the manufacturing process is relatively cumbersome. However, the semiconductor device packaging structure 600 of this embodiment is mass-produced with two upper and lower metal plate arrays, and then pre-cutting, which can greatly simplify the production process. In addition, the present invention uses a simple metal substrate and can form a thinner appearance. The semiconductor device packaging structure 600 adopts a glue filling method, which can greatly reduce the waste of glue material compared with the conventional structure molding method.

Example 3 The structure of the second embodiment can be used in the package of a single semiconductor device with slight modification. As mentioned above, the stacked structure of semiconductor devices has a considerable height. When the semiconductor device packaging structure of the present invention is used for semiconductor devices containing only a single or a few semiconductor devices, the height or presence or absence of protrusions or mesas on the top substrate 302 and/or the bottom substrates 303A, 303B can be changed as needed. Comply with demand. FIG. 7A shows a schematic diagram of a semiconductor device package structure of the present invention which is applicable to only a single or a few semiconductor devices. As shown in the figure, in this embodiment, the semiconductor device packaging structure 700A also has a top substrate 302 and two bottom substrates 303A and 303B, and a semiconductor device 301 and conductive adhesive material, such as solder paste 102B, between them. The semiconductor device packaging structure 700A also includes solder pastes 102A and 102C for connecting the semiconductor device 301 to the top substrate 302 and the bottom substrate 303A, a partition 304 separating the bottom substrates 303A and 303B, and an insulating layer filling the space between the substrates 305A~305C, and the solder mask of the top substrate 302, or another solder mask of the bottom substrate 303A, 303B that is applied as required.

The coverage of the solder mask is not limited to covering the entire area of the substrate. FIG. 14 shows a schematic diagram of a semiconductor device package structure of another implementation type of this type of embodiment. In the figure, the upper figure A shows the longitudinal section view, and the figure B shows the bottom view. As shown in the figure, the bottom substrate 303A, 303B faces away from the outer surface of the semiconductor element 301A, 301B (including the surface between the two substrates), and a solder mask layer 306 is applied as needed, and the covering part of the solder mask layer is patterned according to application requirements. A part 303A' of the first electrode and a part 303B' of the second electrode are exposed.

Follow the instructions. The structure in FIG. 7A is different from FIG. 6 in that the first bottom substrate 303A is not provided with protrusions or mesa shapes, while the top substrate 302 provides mesa 701A in the contact area with the semiconductor element 301, and in the contact area with the solder paste 102B. A mesa 701B is provided, and the second base substrate 303B also provides a mesa 702B in a contact area with the solder paste 102B. Under this design, the height of the two mesa 701B and 702B reduces the distance between the two substrates in this part, and only needs to fill them with conductive adhesive material to make electrical contact between the two substrates.

In this embodiment, in addition to adjusting the distance between the two substrates by the presence or absence of the mesa shape, the distance between the two substrates may also be adjusted by the height of the mesa shape. For example, the height of the mesa 701B and/or the mesa 702B may be slightly higher than the height of the mesa 701A. A mesa shape may also be provided on the first base substrate 303A, but the sum of the heights of the mesa 701B and the mesa 702B is greater than the height of the mesa 701A and the mesa of the first base substrate 303A.

In addition, FIG. 7B additionally shows a schematic structural diagram of a modification of Embodiment 3. The semiconductor device packaging structure 700B in FIG. 7A provides mesa 701B and 702B only on the top substrate 302 and the contact area between the second bottom substrate 303B and the solder paste 102B. This structure can also achieve the purpose of adjusting the distance between the two substrates.

In addition, providing conductive elements (materials) between the mesa 701B and 702B, such as copper particles, can also achieve the purpose of additionally adjusting the distance between the two substrates. The copper particles can be combined with the mesa shape to achieve precise spacing adjustment.

The semiconductor device packaging structure of this embodiment is the same as the foregoing two embodiments. The packaging method is also the same, but in the steps of preparing the top substrate 302 and the bottom substrates 303A, 303B, a specific area must be selected to form the above-mentioned mesa shape. Methods of forming the mesa include molding, welding, welding, etching, etc., and so on. People in this industry can choose for application needs.

Example 4 Embodiment 2 shows a semiconductor device package structure including a semiconductor device and a conductive device. In the second embodiment, the semiconductor device packaging structure 600 uses thin metal plates as its top substrate 302 and bottom substrates 303A and 303B. However, the top substrate 302 and the bottom substrates 303A, 303B can actually be replaced by insulating substrates to reduce production costs. Figure 8 shows a schematic diagram of the semiconductor device package structure of this application example.

As shown in FIG. 8, the semiconductor device packaging structure includes a top insulating substrate 901 and a bottom insulating substrate 902, and a semiconductor element 301 and conductive elements in between, such as pure copper particles 103. On the inner side of the top insulating substrate 901, that is, the side close to the semiconductor element 301 and the copper particles 103, a first conductive film 901B is formed. The first conductive film 901B is usually a conductive metal film, which is formed on the inner side of the top insulating substrate 901 by coating, pasting, etching and forming. On the outer side of the top insulating substrate 901, in a region corresponding to the first conductive film 901B, a fourth conductive film 901A may also be formed. The material and manufacturing method of the fourth conductive film 901A are the same as or similar to those of the first conductive film 901B. Conductive adhesive materials, such as solder pastes 102A and 102C, electrically connect the semiconductor element 301 and the copper particles 103 to the first conductive film 901B.

On the inner side of the bottom insulating substrate 902, that is, the side close to the semiconductor element 301 and the copper particle 103, a second conductive film 902C and a third conductive film are respectively formed in the region corresponding to the semiconductor element 301 and the copper particle 103 902D. The fifth and sixth conductive films 902A and 902B may be formed on the outer side of the bottom insulating substrate 902. The fifth conductive film 902A is located outside the bottom insulating substrate 902 and corresponds to the area of the second conductive film 902C. The sixth conductive film 902B is located outside the bottom insulating substrate 902 and corresponds to the area of the third conductive film 902D. The second conductive film 902C is electrically isolated from the third conductive film 902D, and the fifth conductive film 902A is electrically isolated from the sixth conductive film 902B. The material and manufacturing method of the second, third, fifth, and sixth conductive films 902C, 902D, 902A, 902B are the same as or similar to those of the first conductive film 901B. Conductive adhesive materials, such as solder pastes 102B and 102D, electrically connect the semiconductor element 301 and the copper pellet 103 to the third conductive film 902D and the second conductive film 902C, respectively.

The top insulating substrate 901 and the bottom insulating substrate 902 can be glass fiber substrates or any insulating material that is easy to process. In order to reduce costs, plastic, resin, paper and other materials can usually be used. Among them, epoxy resin is the preferred material because of its low cost and easy availability. Since the top insulating substrate 901 and the bottom insulating substrate 902 are insulators, at the position where the first conductive film 901B overlaps the fourth conductive film 901A, a hole is formed through the top insulating substrate 901, and the hole is filled with conductive material or A conductive metal film, such as a metal material or a conductive paste, is formed on the wall of the hole to form the first conductive pillar 901D. At the position where the second conductive film 902C overlaps the fifth conductive film 902A, a hole is formed through the bottom insulating substrate 902, and a conductive material is filled in the hole or a conductive metal film is formed on the wall of the hole, such as metal material, conductive Paste to form the second conductive pillar 902F. In addition, at the position where the third conductive film 902D and the sixth conductive film 902B overlap, a hole is formed through the bottom insulating substrate 902, and a conductive material is filled in the hole or a conductive metal film, such as metal, is formed on the wall of the hole. Materials and conductive paste to form the third conductive pillar 902G.

The semiconductor device packaging structure 1100A additionally includes insulating layers 305A to 305C for filling the space between the two insulating substrates. If necessary, the solder mask layer 306 on the outer surfaces of the top insulating substrate 901 and the bottom insulating substrate 902 can also be included.

In the semiconductor device package structure formed in this way, the sixth conductive film 902B becomes the first electrode, and the fifth conductive film 902A becomes the second electrode. This structure can use the semiconductor element packaging structure of the present invention instead of the structure of the second embodiment.

The manufacturing method of the semiconductor element package structure shown in FIG. 8 will be described below. FIG. 9 shows a method flowchart of another preferred embodiment of the semiconductor device packaging method of the present invention. This method is mainly used to manufacture the semiconductor device packaging structure as shown in FIG. 8.

As shown in the figure, in step 1201, a top insulating substrate 901 is prepared. In the mass production process, the top insulating substrate 901 is used to support most semiconductor device packaging structural units. In this embodiment, each semiconductor device packaging structure unit includes a semiconductor device 301 and a conductive device, such as copper particles 103. In step 1202, a first conductive layer 901B is formed on the inner surface of the top insulating substrate 901, that is, the surface where the semiconductor element 301 and the copper particles 103 are arranged. A region is selected on the outer surface of the top insulating substrate 901 to form a fourth conductive layer 901A. Methods of forming the conductive layers 901B and 901A include printing, coating, pasting, etching and forming to form a conductive metal thin layer. In step 1203, conductive adhesive materials, such as solder pastes 102A and 102C, are applied to predetermined positions on the conductive layer 901B. In step 1204, place most of the semiconductor elements 301 on the positions of the corresponding solder paste 102C, and place most of the copper pellets 103 on the positions of the corresponding solder paste 102A to fix the semiconductor elements 301 and the copper pellets 103 , And electrically connected to the top insulating substrate 901.

Next, in step 1205, a bottom insulating substrate 902 is prepared. The bottom insulating substrate 902 is also used to support most semiconductor device packaging structural units. In step 1206, a plurality of second conductive layers 902C and third conductive layers 902D are formed on the inner surface of the bottom insulating substrate 902, that is, the surface where the semiconductor element 301 and the copper particles 103 are arranged. And on the outer surface of the bottom insulating substrate 902, a plurality of fifth conductive layers 902A and sixth conductive layers 902B are formed. The method of forming the metal layer is as described above. In step 1207, conductive adhesive materials, such as solder pastes 102B and 102D, are applied to predetermined positions on the conductive layer of the bottom insulating substrate 902. The predetermined position of the conductive layer of the bottom insulating substrate corresponds to the predetermined position of the conductive layer of the top insulating substrate. In step 1208, the bottom insulating substrate 902 is combined with the top insulating substrate 901, so that the individual solder paste 102D on the bottom insulating substrate 902 electrically contacts the semiconductor element 301 on the top insulating substrate 901, and the bottom insulating substrate 902 The individual solder paste 102B electrically contacts the copper particles 103 on the top substrate and is fixed. If necessary, heat or pressure can be applied to make the conductive adhesive materials 102A, 102B, 102C, and 102D firmly adhere the semiconductor elements 301A, 301B to the top substrate 302 and the bottom substrate.

In step 1209, the space between the top insulating substrate 901 and the bottom insulating substrate 902 is filled with insulating layers 305A, 305B, and 305C. The gap between the two substrates can be filled by capillary phenomenon, pressure pouring or vacuuming to form an insulating layer. After completion, the packaging structure with the insulating layer formed is baked in an oven to cure the insulating layer. In step 1210, at the position where the first conductive film 901B overlaps the fourth conductive film 901A, a hole is formed through the top insulating substrate 901, and a conductive material is filled in the hole to form a first conductive pillar 901D. At the position where the second conductive film 902C overlaps the fifth conductive film 902A, a hole is formed through the bottom insulating substrate 902, and a conductive material is filled in the hole or a conductive metal film is formed on the wall of the hole to form a second conductive film. Column 902F. And at the position where the third conductive film 902D overlaps the sixth conductive film 902B, a hole is formed through the bottom insulating substrate 902, and a conductive material is filled in the hole or a conductive metal film is formed on the wall of the hole to form a third Conductive pillar 902G. The method of forming the hole can use any known method, such as drilling, laser cutting or etching. The filled conductive material can also be any suitable material, such as solder paste, silver paste, copper paste, etc.

In this way, a semiconductor device packaging structure with multiple units is formed, and each unit includes a semiconductor device 301 and a copper particle 103. The first electrode of the package structure, that is, the sixth conductive film 902B, is electrically connected to the first electrode of the semiconductor element 301 via the third conductive pillar 902G, the third conductive film 902D, and the conductive material 102D. The second electrode of the semiconductor element 301 is electrically connected to the package structure via the conductive material 102C, the first conductive film 901B, the conductive material 102A, the copper particles 103, the conductive material 102B, the second conductive film 902C, and the second conductive pillar 902F. The second electrode is the fifth conductive film 902A.

If necessary, in step 1211, solder resist layers 306 and 307 are respectively applied to the outer surfaces of the top insulating substrate 901 and the bottom insulating substrate 902. Finally, in step 1212, a cutting operation is performed to form a semiconductor device packaging structure 1100A of a plurality of units.

Example 5 The packaging structure of Embodiment 4 uses an insulating substrate, which can reduce the manufacturing cost. Although the semiconductor device package structure of the process is relatively large, the structure is relatively stable. This structure can further save costs by not using conductive materials, such as copper particles, but still provide a fairly stable structure. Figure 10 shows the structure diagram of this change structure.

As shown in the figure, the semiconductor device packaging structure 1100B of this embodiment is similar to the structure 1100A of FIG. 8, but the conductive elements, such as copper particles 103, are not required. The semiconductor device packaging structure 1100B of FIG. 10 includes a top insulating substrate 901 and a bottom insulating substrate 902, and a semiconductor device 301 in between. On the inner side of the top insulating substrate 901, that is, the side close to the semiconductor element 301, a first conductive film 901B is formed. A fourth conductive film 901A is formed on the outer side of the top insulating substrate 901 at a position away from the semiconductor element 301 and corresponding to the area of the first conductive film 901B. A conductive adhesive material, such as solder paste 102A, electrically connects the semiconductor element 301 and the first conductive film 901B.

On the inner side of the bottom insulating substrate 902, that is, the side close to the semiconductor element 301, a region corresponding to the semiconductor element 301 is formed with a third conductive film 902D. On the inner side of the bottom insulating substrate 902, a second conductive film 902C is formed in a region corresponding to the fourth conductive film 901A. On the outer side of the bottom insulating substrate 902, a fifth conductive film 902A corresponding to the second conductive film 902C and a sixth conductive film 902B corresponding to the third conductive film 902D are respectively formed. The second conductive film 902C is electrically isolated from the third conductive film 902D, and the fifth conductive film 902A is electrically isolated from the sixth conductive film 902B. A conductive adhesive material, such as a solder paste 102B, electrically connects the semiconductor element 301 and the third conductive film 902D.

The semiconductor device packaging structure 1100B additionally includes insulating layers 305A to 305C for filling the space between the two insulating substrates. If necessary, the solder mask layer 306 on the outer surfaces of the top insulating substrate 901 and the bottom insulating substrate 902 can also be included.

At the position where the first conductive film 901B overlaps with the fourth conductive film 901A, toward the position where the second conductive film 902C overlaps with the fifth conductive film 902A, form the top insulating substrate 901, the insulating layers 305A, 305B. , And the hole of the bottom insulating substrate 902, and fill the hole with a conductive material or form a conductive metal film on the wall of the hole, such as a metal material, a conductive paste, to form a first conductive pillar 901D. In addition, at a position where the third conductive film 902D overlaps the sixth conductive film 902B, a hole is formed through the bottom insulating substrate 902, and a conductive material, such as a metal material, is filled in the hole to form a third conductive pillar 902G .

In the semiconductor device packaging structure formed in this way, the sixth conductive film 902B becomes the first electrode, and the fifth conductive film 902A becomes the second electrode. This structure can use the semiconductor element packaging structure of the present invention instead of the structure of the sixth embodiment. In this structure, each unit includes a semiconductor element 301. The first electrode of the package structure, that is, the sixth conductive film 902B, is electrically connected to the first electrode of the semiconductor element 301 via the third conductive pillar 902G, the third conductive film 902D, and the conductive material 102B. The second electrode of the semiconductor element 301 is electrically connected to the second electrode of the package structure, that is, the fifth conductive film 902A, via the conductive material 102A, the first conductive film 901B, and the first conductive pillar 901D.

The manufacturing method of the semiconductor device packaging structure of this embodiment is substantially the same as that of Embodiment 4, but the step of disposing copper particles and related conductive adhesive materials is omitted. In addition, in the step of forming a conductive pillar, in addition to forming the third conductive pillar 902G, a conductive pillar penetrating the top insulating substrate 901, the insulating layers 305A, 305B, and the bottom insulating substrate 902 is additionally formed.

Example 6 In Embodiments 1 to 3, the top substrate 302 in the semiconductor device packaging structure is integrated to connect the semiconductor devices 301A and 301B in series. However, in a specific application, the top substrate 302 can also use a second partition area 304A to be separated into electrically isolated first top block 801A and second top block 801B.

FIG. 11 is a schematic diagram showing an embodiment of the semiconductor device packaging structure of the present invention suitable for the above-mentioned application. As shown in the figure, the semiconductor packaging unit 800 of this embodiment includes a first top block 801A and a second top block 801B in a portion corresponding to the top substrate 302 of the previous embodiment. The rest of the structure is the same as that of the first embodiment, which also includes two bottom substrates 303A and 303B, the semiconductor element 301 between the first top block 801A and the second top block 801B and the two bottom substrates 303A and 303B. The semiconductor device packaging unit 800 additionally includes conductive adhesive materials for connecting the two semiconductor devices 301 to the first top block 801A and the second top block 801B, and the two bottom substrates 303A, 303B, such as solder paste 102A ~102D, the partition 304 separating the bottom substrates 303A and 303B, the second partition 304A separating the two top blocks 801A and 801B, and the insulating layers 305A-305C that fill the space between the substrates. However, in most applications, it is not necessary to apply a solder mask on the top substrate (the first top block 801A and the second top block 801B).

The semiconductor element packaging structure with the above structure can be applied to a variety of special purposes. For example: 1. Simply provide semiconductor packaging-this embodiment can be applied to provide packaging protection for the stacked structure of semiconductor devices. After the stacking structure of the conventional semiconductor device is completed, a plurality of semiconductor devices are exposed to the outside, and it is easily affected by external force impact or environmental impact during storage and movement, which may cause damage to single or multiple semiconductor devices. It is also susceptible to moisture during storage. The semiconductor device packaging structure and the semiconductor device packaging method of the present invention, after the semiconductor device stack structure is stacked, are added in an array form outside the stack structure, protected by an insulating layer, but still provide top and bottom electrodes as the upper and lower sides The electrode contact point does not change the original form of electrical conduction. The present invention can improve the stacking method of the conventional technology, effectively prevent damage to the stacking element caused by collision, and isolate the adverse effects of moisture. It should be noted that if only the novel structure and process of the present invention are used to provide packaging protection for the stacked structure of semiconductor elements or semiconductor devices, when multiple semiconductor devices or semiconductor elements are arranged in the process, if a single-unit semiconductor stacked device is used It is not necessary to pay special attention to making the polar directions of two adjacent semiconductor devices or semiconductor elements opposite when performing cutting applications. If there are considerations for polarity or circuit matching for subsequent applications, the semiconductor stack devices of adjacent units must pay special attention to the polarity directions of the two adjacent semiconductor devices, and the placement must be determined according to requirements. In addition, the packaged semiconductor device package structure will include most semiconductor device package structure units before being cut. This semiconductor device packaging structure is suitable for storage and transportation. Cutting is required before application, or cutting can be arranged first. 2. Stacking of a large number of semiconductor devices-The number of semiconductor devices or semiconductor devices that can be stacked in the semiconductor device stack structure of the known technology has its limit. The conventional stacked structure of semiconductor devices is not suitable for stacking each other, forming a large number of stacked structures. The semiconductor device packaging structure proposed in this embodiment can be used to stack more than two semiconductor devices to achieve greater application power. It should be noted that if the semiconductor device packaging structure of the present invention is to be used for stacking a large number of packaging structures, when placing a large number of semiconductor devices or semiconductor elements in the manufacturing process, special attention must be paid to the polarity direction of two adjacent semiconductor devices or semiconductor elements. Facing the opposite. If it is a bipolar semiconductor device, there is no requirement for polarity direction.

The semiconductor device packaging structure of this embodiment is the same as that shown in FIG. 3, but the top substrate 302 in FIG. 3 is replaced by a first top block 801A and a second top block 801B. The manufacturing process of the semiconductor device packaging structure is also the same as that shown in FIG. 5, but in step 507, before, after, or at the same time when the partition 304 is formed on the bottom substrate, a second partition is formed on the top substrate, so that the top substrate 302 is divided into a first top block 801A and a second top block 801B. In this step 503, the polarity directions of the two adjacent semiconductor elements 301 may be opposite, and the polarity directions of the two adjacent semiconductor elements 301 may not be opposite. The semiconductor element packaging method may or may not include a dividing step. The semiconductor device 301 may be a single semiconductor device, or a semiconductor device including multiple semiconductor devices, such as a stack of semiconductor devices.

Example 7 The semiconductor device packaging structure prepared in Embodiment 6 can be further stacked and packaged. FIG. 12 shows a stacking application of the semiconductor device packaging structure of the sixth embodiment. As shown in the figure, the semiconductor device packaging structure in FIG. 12 includes a top substrate 302 and two bottom substrates 303A and 303B, and a plurality of semiconductor packaging units 800 in between. The semiconductor packaging unit 800 is, for example, a semiconductor device packaging structure unit having the structure shown in FIG. 11, and each unit includes two semiconductor devices 301A and 301B. For the sake of clarity, each semiconductor packaging unit 800 is only represented by a dotted line in the figure, and its detailed structure is not shown. The stacking method of the plurality of semiconductor packaging units 800 is that the first base substrate 803A of all semiconductor packaging units 800 are located on the same side, and the second base substrate 803B is also on the same side. In this way, the first bottom substrates 803A of all the semiconductor packaging units 800 are connected in the same polarity direction, and the second bottom substrates 803B of all the semiconductor packaging units 800 are also connected in the same polarity direction. The two polarities are in opposite directions. But if it is a bipolar component, there is no such requirement.

The semiconductor device packaging structure 900 additionally includes conductive adhesive materials used to connect the first top block 801A and the second top block 801B of the uppermost semiconductor packaging unit 800 to the top substrate 302, such as solder paste 102A, 102C; The conductive adhesive material for the top block and the bottom substrate of two adjacent semiconductor packaging units 800, such as solder paste 102E, and the conductive adhesive material for connecting the two bottom substrates 803A, 803B of the lowest semiconductor packaging unit 800 to the bottom substrates 303A, 303B , Such as solder paste 102B, 102D. The bottom substrates 303A and 303B of the semiconductor device packaging structure 900 are separated by a partition 304, the spaces between the substrates are filled with insulating layers 305A-305C, and the top substrate 302 is applied with a solder resist layer 306. The surfaces of the bottom substrates 303A and 303B facing away from the semiconductor devices 301A and 301B (including the surface between the two substrates), depending on the application requirements, determine whether to apply a solder mask. The applied solder mask can be applied on the entire surface of the substrate, but can also be applied on part of the surface, exposing part of the shape of the electrode.

Although FIG. 12 shows a stack structure of a plurality of semiconductor packaging units 800, it is well known in the industry that the packaging structure 900 may also include only a single semiconductor packaging unit 800. In this application, since the semiconductor packaging unit 800 has been processed and packaged, better moisture isolation can be obtained by processing with this process.

Hereinafter, a method of manufacturing the semiconductor element packaging structure of FIG. 12 will be described. FIG. 13 shows a method flowchart of a preferred embodiment of the semiconductor device packaging method of the present invention. This method is mainly used to fabricate the semiconductor device packaging structure shown in FIG. 9.

As shown in the figure, in step 1001, a top substrate 302 is prepared. In the mass production process, the top substrate 302 is used to support most semiconductor device packaging structural units. In this embodiment, each semiconductor device packaging structure unit includes a structure formed by stacking a plurality of semiconductor packaging units 800. Each semiconductor packaging unit 800 contains two semiconductor elements. Each semiconductor package unit 800 may have, for example, the structure shown in FIG. 11. In step 1002, conductive adhesive materials, such as solder pastes 102A and 102C, are applied on the top substrate 302 to configure a predetermined position on the surface of the semiconductor package unit 800. In step 1003, a plurality of semiconductor package units 800 are arranged on the top substrate 302, so that the first top block 801A and the second top block 801B of each semiconductor package unit 800 are respectively disposed on the corresponding positions of the solder paste 102A and 102C , So as to fix the majority of semiconductor packaging units 800 and electrically connect to the top substrate 302. Thereafter, in step 1004, a conductive adhesive material, such as solder paste 102E, is applied to the first base substrate 803A and the second base substrate 303B of each semiconductor packaging unit 800, and then the same number of semiconductor packaging units 800 are respectively arranged in the step 1003 has been fixed to the semiconductor packaging unit 800 on the top substrate 302. The majority of semiconductor package units 800 become the second layer. Step 1004 is repeated until the predetermined number of layers of semiconductor packaging units 800 have been arranged on the top substrate 302.

Next, in step 1005, a base substrate is prepared. The top substrate is also used to support most semiconductor device packaging structural units. A conductive adhesive material, such as solder paste 102B and 102D, is applied to the predetermined position of the base substrate. The predetermined position of the bottom substrate corresponds to the predetermined position of the top substrate. In step 1006, the bottom substrate and the top substrate are combined, so that the individual solder pastes 102B and 102D on the bottom substrate electrically contact the top substrate 302, and the first top part on the semiconductor packaging unit 800 farthest from the top substrate 302 The block 801A and the second top block 801B are fixed.

In step 1007, the insulating layers 305A, 305B, and 305C are filled between the top substrate 302 and the bottom substrate, and the spaces between the semiconductor packaging units 800 and the two substrates. During application, capillary phenomenon, pressure pouring or vacuuming can be used to fill the gaps between substrates, semiconductor packaging units, and between substrates and semiconductor packaging units to form an insulating layer. The material of the insulating layers 305A, 305B, and 305C is preferably epoxy resin. After completion, the packaging structure with the insulating layer formed is baked in an oven to cure the insulating layer. In step 1008, a partition 304 is formed on the base substrate, so that the base substrate of each semiconductor packaging unit 800 forms a first base substrate 303A and a second base substrate 303B. The available processing method includes forming the partition 304 by a chemical etching method. Then, in step 1009, a solder mask layer 306 is applied to the surface of the top substrate 302 facing away from the semiconductor package unit 800, and the solder mask layer between the bottom substrates 303A and 303B and the bottom substrate is determined according to application requirements. Solder mask. Finally, in step 1010, a cutting operation is performed to form a semiconductor device packaging structure 900 of a plurality of units, and each unit includes a predetermined number of semiconductor packaging units 800.

100A: Semiconductor device stack structure 100B: Semiconductor device stack structure 101: Semiconductor device 101A~101N: Semiconductor device 102A~102(N-1), 04A~104(N-1): solder paste 103A~103(N-1): Copper grain 103: Conductive metal plate 103: Copper grain 111: Top first electrode 121: bottom second electrode 131: Semiconductor wafer 141: Sheath material 300: Semiconductor component packaging structure 301: Semiconductor components 301A: The first semiconductor component 301B: second semiconductor element 302: Top substrate 303A, 303B: bottom substrate 303A’: Part of the first electrode 303B’: Part of the second electrode 304: partition 304A: second compartment 305A, 305B, 305C: insulating layer 306, 307: solder mask 600: Semiconductor component packaging structure 700A: Semiconductor component packaging structure 700B: Semiconductor component packaging structure 701B, 702B: platform shape 800: Semiconductor packaging unit 801A: First top block 801B: second top block 803A: First bottom substrate 803B: second bottom substrate 900: Semiconductor component packaging structure 901: Top insulating substrate 902: bottom insulating substrate 901A: Fourth conductive film 901B: The first conductive film 901D: The first conductive pillar 902A: Fifth conductive film 902B: sixth conductive film 902C: second conductive film 902D: Third conductive film 902F: second conductive pillar 902G: third conductive pillar 1100A: Semiconductor component packaging structure 1100B: Semiconductor component packaging structure

FIG. 1 shows a common semiconductor device stack structure in the industry. FIG. 2 is another stacked structure suitable for the semiconductor device of the present invention. FIG. 3 shows a schematic diagram of an embodiment of the semiconductor device packaging structure of the present invention. FIG. 4 shows a schematic diagram of the structure of a single device semiconductor device applicable to the present invention. FIG. 5 shows a method flowchart of a preferred embodiment of the semiconductor device packaging method of the present invention. FIG. 6 shows a schematic structural view of a second embodiment of the semiconductor device packaging structure of the present invention. FIG. 7A shows a schematic diagram of a semiconductor device package structure of the present invention which is applicable to only a single or a few semiconductor devices. FIG. 7B shows a schematic structural diagram of a modification of Embodiment 3. FIG. FIG. 8 shows a schematic diagram of a modified example of the semiconductor device packaging structure of the second embodiment. FIG. 9 shows a flowchart of a manufacturing method of the semiconductor device packaging structure of FIG. 8. FIG. 10 is a structural diagram showing a variation of the semiconductor device packaging structure of the embodiment of FIG. 8. FIG. 11 shows a schematic structural view of another variation of the semiconductor device packaging structure of the embodiment in FIG. 3. FIG. 12 shows a schematic diagram of a stacked application structure of the semiconductor device packaging structure of the embodiment of FIG. 3. FIG. 13 shows a flowchart of the method in the embodiment of FIG. 12. FIG. 14 shows a schematic diagram of an implementation mode of applying a solder resist layer to the semiconductor device packaging structure of the present invention. Among them, Figure A shows its longitudinal section view, and Figure B shows its bottom view.

102A~102D: solder paste

301: Semiconductor components

301A: The first semiconductor component

301B: second semiconductor element

302: Top substrate

303A, 303B: bottom substrate

304: partition

305A, 305B, 305C: insulating layer

306: solder mask

Claims (32)

A semiconductor component packaging structure, including: The first and second semiconductor elements each have a first electrode and a second electrode, which are respectively arranged on the top surface and the bottom surface of the semiconductor element; A first substrate, where the second electrode of the first semiconductor element and the first electrode of the second semiconductor element are connected to the first substrate; The second substrate and the third substrate are respectively connected to the other electrodes of the two semiconductor elements; Wherein: the outer surface of the second substrate and the third substrate away from the semiconductor element are substantially on the same plane; and An insulator fills the space between the first substrate and the second and third substrates. For example, the semiconductor device packaging structure of the first item of the patent application, wherein the semiconductor device is a device containing a large number of semiconductor devices. For example, in the semiconductor device packaging structure of the first item of the patent application, the semiconductor device is a device that contains many semiconductor devices and is arranged in a vertical stack. For example, in the semiconductor device packaging structure of the first item of the patent application, one of the semiconductor devices is a simple conductive element or a simple insulating element. For example, in the semiconductor device packaging structure of the first item of the patent application, at least one substrate is an insulating substrate. For example, the semiconductor device packaging structure of the first item in the scope of the patent application, wherein at least one of the first, second, and third substrates provides mesa protrusions. A semiconductor component packaging structure, including: A plurality of semiconductor elements, each having a first electrode and a second electrode, which are respectively arranged on the top surface and the bottom surface of the semiconductor element; A plurality of first substrates with the same number of semiconductor elements, the plurality of semiconductor elements are respectively arranged on the plurality of first substrates, so that two adjacent semiconductor elements are connected to the first substrate with their first electrodes and second electrodes respectively; Most second substrates with the same number of semiconductor elements are respectively connected to the other electrodes of two adjacent semiconductor elements; Wherein: the distance between the first substrate and the second substrate is substantially the same; and The insulator fills the spaces between the first substrate and the second substrate, between the first substrate and the first substrate, and between the second substrate and the second substrate. For example, the semiconductor device packaging structure of the seventh item in the scope of the patent application, wherein the semiconductor device is a device containing many semiconductor devices. For example, in the semiconductor device packaging structure of the seventh item in the scope of patent application, the semiconductor device is a device that contains a large number of semiconductor devices and is arranged in a vertical stack. For example, in the semiconductor device packaging structure of the seventh item of the patent application, one of the semiconductor devices is a simple conductive element or a simple insulating element. For example, in the semiconductor device packaging structure of item 7 of the scope of patent application, at least one substrate is an insulating substrate. For example, the semiconductor device packaging structure of the seventh item of the patent application, wherein at least one of the first, second, and third substrates provides mesa protrusions. A semiconductor component packaging structure, including: A plurality of semiconductor elements, each having a first electrode and a second electrode, which are respectively arranged on the top surface and the bottom surface of the semiconductor element; A first substrate, where the plurality of semiconductor elements are arranged on the plurality of first substrates, so that two adjacent semiconductor elements are connected to the first substrate with their first electrodes and second electrodes respectively; A plurality of second substrates with the same number of semiconductor elements are respectively connected to another electrode of the plurality of semiconductor elements; Wherein: the distance between the first substrate and the second substrate is substantially the same; and The insulator fills the space between the first substrate and the second substrate and between the second substrate and the second substrate. A semiconductor component packaging structure, including: A plurality of semiconductor elements, each having a first electrode and a second electrode, which are respectively arranged on the top surface and the bottom surface of the semiconductor element; A first substrate, the plurality of semiconductor elements are arranged on the plurality of first substrates, so that two adjacent semiconductor elements are respectively connected to the first substrate with their first electrodes and second electrodes; A plurality of second substrates with the same number of semiconductor elements are respectively connected to another electrode of the plurality of semiconductor elements; Wherein: the distance between the first substrate and the second substrate is substantially the same; An insulator filling the space between the first substrate and the second substrate; and The separation area is located between the second substrate and the second substrate to form electrical insulation between adjacent second substrates. For example, the semiconductor device packaging structure of the 13th or 14th patent application, wherein the semiconductor device is a device containing a large number of semiconductor devices. For example, the semiconductor device package structure of item 13 or 14 of the scope of patent application, wherein the semiconductor device is a device that contains a large number of semiconductor devices and is arranged in a vertical stack. For example, the semiconductor device packaging structure of the 13th or 14th patent application, wherein one of the semiconductor devices is a simple conductive element or a simple insulating element. For example, the semiconductor device packaging structure of item 13 or 14 of the scope of patent application, wherein at least one substrate is an insulating substrate. For example, the semiconductor device packaging structure of item 13 or 14 of the scope of the patent application, wherein at least one of the first, second, and third substrates provides mesa-shaped protrusions. A semiconductor component packaging method includes the following steps: Preparing a large number of semiconductor elements, each having a first electrode and a second electrode; Provide a top substrate; Applying conductive material on the top substrate to configure a predetermined position on the surface of the semiconductor element; Placing the plurality of semiconductor elements on the corresponding conductive material of the top substrate, so that every two semiconductor elements are electrically connected to the top substrate by a first electrode and a second electrode; Provide a bottom substrate; Applying conductive material at a predetermined position of the bottom substrate; the predetermined position of the bottom substrate corresponds to the predetermined position of the top substrate; Combining the bottom substrate with the top substrate, so that the plurality of semiconductor elements contact the conductive material on the top substrate, and are fixed; Filling the space between the top substrate and the bottom substrate with an insulating layer; and A partition area is formed on the base substrate to partition the base substrate into a plurality of units connected to only a single semiconductor element. For example, the method of claim 20 further includes the step of applying heat or pressure after the step of combining the bottom substrate and the top substrate to make the conductive material adhere the semiconductor element on the top substrate and the bottom substrate. For example, in the method of claim 20, the insulating layer is formed by filling the gap between the two substrates with an insulator by one of methods such as capillary phenomenon, pressure potting, or vacuuming. Such as the method of claim 20, wherein the step of forming the partition includes a chemical etching method or a laser ablation method. For example, the method of claim 20 further includes the step of applying a solder resist layer on the surface of the top substrate and/or the bottom substrate facing away from the semiconductor device after the partition is formed. Such as the method of item 24 of the scope of patent application, wherein the solder mask covers a part of the surface. For example, the method of item 20 of the scope of the patent application also includes the step of cutting the completed structure to form a plurality of units, wherein each unit includes two adjacent units, and the first electrode and the second electrode are electrically connected respectively To the top substrate of the semiconductor element. For example, the method according to item 20 or 26 of the scope of patent application, wherein the semiconductor element is an element containing many semiconductor devices. For example, the method according to item 20 or 26 of the scope of the patent application, wherein the semiconductor device is a device that contains a large number of semiconductor devices and is arranged in a vertical stack. Such as the method of item 20 or 26 of the scope of patent application, wherein one of the semiconductor elements is a simple conductive element or a simple insulating element. For example, the method according to item 20 or 26 of the scope of patent application, wherein the at least one substrate is an insulating substrate. For example, the method of item 20 or 26 of the scope of the patent application further includes a step of forming a mesa-shaped protrusion at a predetermined position of the top substrate or a predetermined position of the bottom substrate. For example, the method of item 20 or 26 of the scope of the patent application includes a method of forming a partition on the top substrate before, after or at the same time as forming a partition on the bottom substrate, so as to partition the top substrate into a plurality of connecting only a single semiconductor Elements of the steps.

Images