TWI704628B - Semiconductor element package structure and method - Google Patents
Semiconductor element package structure and method Download PDFInfo
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- TWI704628B TWI704628B TW108114148A TW108114148A TWI704628B TW I704628 B TWI704628 B TW I704628B TW 108114148 A TW108114148 A TW 108114148A TW 108114148 A TW108114148 A TW 108114148A TW I704628 B TWI704628 B TW I704628B
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
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Abstract
Description
本發明是關於半導體元件封裝結構與半導體元件封裝方法,特別是關於一種含多數半導體元件的半導體元件封裝結構,以及用來製作這種半導體元件封裝結構的方法。 The present invention relates to a semiconductor element packaging structure and a semiconductor element packaging method, in particular to a semiconductor element packaging structure containing many semiconductor elements, and a method for manufacturing such a semiconductor element packaging structure.
在半導體元件的製造行業中,半導體元件的封裝技術,尤其用來封裝多數半導體元件的技術,乃是一種重要的技術。良好的封裝結構可以提供縮小裝置體積,節省成本,簡化生產,以及便利存放、運送及應用的優點。此外,半導體元件封裝結構的可擴充性,更是現今業界所追求的目標。特別是應用在電力供應、資料儲存等領域的半導體元件,需要有能夠配合裝置所需的規模,任意縮減或增加半導體元件個數的封裝技術。 In the semiconductor component manufacturing industry, the packaging technology of semiconductor components, especially the technology used to encapsulate most semiconductor components, is an important technology. A good packaging structure can provide advantages such as reduced device volume, cost savings, simplified production, and convenient storage, transportation and application. In addition, the scalability of the semiconductor device packaging structure is a goal pursued by the industry today. Especially semiconductor components used in the fields of power supply, data storage, etc., require packaging technology that can arbitrarily reduce or increase the number of semiconductor components to match the scale required by the device.
多數半導體元件可以利用垂直堆疊的方式封裝。 Most semiconductor components can be packaged in a vertical stack.
中國實用新型專利CN 204991698U揭示一種「半導體芯片集成元件」。所揭示的結構包括第一引線結構,第二引線結構及堆疊在兩者之間的N個第三引線結構。相鄰兩個引線結構之間連接一片半導體芯片。如此堆疊成為半導體元件封裝結構。 Chinese utility model patent CN 204991698U discloses a "semiconductor chip integrated component". The disclosed structure includes a first lead structure, a second lead structure, and N third lead structures stacked between the two. A piece of semiconductor chip is connected between two adjacent lead structures. Such stacking becomes a semiconductor device packaging structure.
中國實用新型專利CN 206505909U揭示一種「雙晶片垂直並聯方式的二極體封裝結構」。該結構包括由外引線A與B及載片台組成的引線框架,框架內配置內引線A、B以及垂直堆疊的第一與第二芯片。 Chinese utility model patent CN 206505909U discloses a "two-chip vertical parallel diode package structure". The structure includes a lead frame composed of outer leads A and B and a mounting table, and inner leads A, B and vertically stacked first and second chips are arranged in the frame.
除了垂直堆疊的封裝結構外,尚可使用水平排列的封裝結構。 In addition to vertically stacked packaging structures, horizontally arranged packaging structures can also be used.
美國專利公開案US 2004/041230公開一種「串聯二極管的半導體封裝」,用來將兩個串連的二極管封裝在一個電力封裝中。其中,第一二極管的負極是以共用導電板電性連接到第二二極管的正極。該共用導電板與連接兩二極管其餘電極的導電板,向側方延伸出接腳。 The US Patent Publication US 2004/041230 discloses a "semiconductor package with series diodes", which is used to package two series connected diodes in one power package. Wherein, the cathode of the first diode is electrically connected to the anode of the second diode by a common conductive plate. The common conductive plate and the conductive plate connecting the remaining electrodes of the two diodes have pins extending laterally.
美國專利US 4,047,197A揭示一種「串聯半導體整流器配置的外殼與導線結構」。其中,兩個整流器固定在共用金屬基底的一側,兩者為電性隔離但熱性導通。兩個整流器連接成串聯電路,以形成結構單元,並收容在該外殼內。該專利使用一片Z型的金屬板,串聯兩個整流器。 US Patent No. 4,047,197A discloses a "casing and wire structure of a series semiconductor rectifier configuration". Among them, two rectifiers are fixed on one side of the common metal base, and the two are electrically isolated but thermally conductive. Two rectifiers are connected into a series circuit to form a structural unit, and are accommodated in the casing. This patent uses a Z-shaped metal plate to connect two rectifiers in series.
美國專利US 6,031,279A揭示一種「電源用半導體元件」,其中有兩個分別具有第三垂直電晶體與第四垂直電晶體的第二晶片,安裝在一個第一晶片上方。該第一晶片具有兩個水平排列的第一垂直電晶體與第二垂直電晶體。使得四個電晶體的負載路徑形成串聯。該串聯電路的電極以引線連接至導線架。導線架外露於封裝結構的部分形成接腳。 US Patent 6,031,279A discloses a "semiconductor device for power supply", in which there are two second chips with a third vertical transistor and a fourth vertical transistor, respectively, mounted on a first chip. The first chip has two horizontally arranged first vertical transistors and second vertical transistors. The load paths of the four transistors are connected in series. The electrodes of the series circuit are connected to the lead frame by leads. The part of the lead frame exposed to the package structure forms a pin.
由以上對現有技術的觀察可以得知,習知技術的半導體元件封裝結構試圖將多數的半導體元件以垂直堆疊或水平排列,甚至垂直堆疊結合水平排列的方式封裝。但是所形成的封裝結構需要使用特殊設計的導電板,連接相關的電極。使得半導體元件的封裝製程複雜化,並提高封裝的成本。此外,習 知技術的封裝結構欠缺擴充性。無法隨系統所需的規模縮小或放大封裝中的半導體元件數量。 From the above observation of the prior art, it can be known that the semiconductor device packaging structure of the prior art attempts to package most semiconductor devices in a vertical stack or a horizontal arrangement, or even a combination of a vertical stack and a horizontal arrangement. However, the formed package structure requires the use of specially designed conductive plates to connect related electrodes. This complicates the packaging process of the semiconductor element and increases the packaging cost. In addition, Xi The packaging structure of the known technology lacks scalability. The number of semiconductor components in the package cannot be reduced or enlarged with the scale required by the system.
因此,目前業界亟需一種新穎的半導體元件封裝技術,應用在含多數半導體元件的結構,可以縮小裝置體積,節省封裝成本,簡化生產流程,並形成存放、運送及應用均便利的封裝結構。 Therefore, there is an urgent need for a novel semiconductor device packaging technology in the industry, which can be applied to structures containing most semiconductor devices, which can reduce the size of the device, save packaging costs, simplify the production process, and form a packaging structure that is convenient for storage, transportation, and application.
此外,目前業界也需要有一種創新的半導體元件封裝技術,可以提供高度的擴充性,應用在對不同數量的半導體元件的封裝。 In addition, the industry also needs an innovative semiconductor device packaging technology that can provide a high degree of scalability and is applied to the packaging of different numbers of semiconductor devices.
本發明的目的乃在提供一種新穎的半導體元件封裝技術,用來封裝含多數半導體元件的結構。 The purpose of the present invention is to provide a novel semiconductor device packaging technology for packaging structures containing many semiconductor devices.
本發明的目的也在提供一種半導體元件封裝結構,可以縮小裝置體積,節省封裝成本,簡化生產流程,並便利存放、運送及應用。 The purpose of the present invention is also to provide a semiconductor element packaging structure, which can reduce the volume of the device, save packaging costs, simplify the production process, and facilitate storage, transportation and application.
本發明的目的也在提供一種半導體元件封裝結構,以提供高度的擴充性,而可以用來封裝不同數量的半導體元件。 The object of the present invention is also to provide a semiconductor device packaging structure to provide a high degree of scalability, which can be used to package different numbers of semiconductor devices.
本發明的目的也在提供上述半導體元件封裝結構的封裝方法。 The object of the present invention is also to provide a packaging method of the above-mentioned semiconductor element packaging structure.
根據本發明的基本設計,半導體元件封裝結構包含:第一及第二半導體元件,各具有第一電極與第二電極,分別配置在半導體元件的頂面與底面。第一半導體元件的第二電極與第二半導元件的第一電極連接在第一基板上,第一半導體元件的第一電極與第二半導體元件的第二電極分別連接第二基板與第三基板。第二基板與第三基板的外表面實質上位於同一平面。在該第一 基板與該第二及第三基板之間的空間,以絕緣體填充。所稱之外表面指該基板離開該第一及第二半導體元件的表面。 According to the basic design of the present invention, the semiconductor device packaging structure includes: first and second semiconductor devices, each having a first electrode and a second electrode, which are respectively disposed on the top surface and the bottom surface of the semiconductor device. The second electrode of the first semiconductor element and the first electrode of the second semiconductor element are connected to the first substrate, and the first electrode of the first semiconductor element and the second electrode of the second semiconductor element are respectively connected to the second substrate and the third Substrate. The outer surfaces of the second substrate and the third substrate are substantially on the same plane. In the first The space between the substrate and the second and third substrates is filled with an insulator. The so-called outer surface refers to the surface of the substrate away from the first and second semiconductor elements.
該第一電極與該第二電極極性可為相同或不同。例如,在雙極性半導體元件的情形,該半導體元件的頂面電極與底面電極極性相同。該第一電極與該第二電極極性即為相同。 The polarity of the first electrode and the second electrode may be the same or different. For example, in the case of a bipolar semiconductor element, the top electrode and the bottom electrode of the semiconductor element have the same polarity. The first electrode and the second electrode have the same polarity.
在本發明的某些實施例中,該半導體元件是含有單一半導體裝置的元件,例如含有單一二極管、整流器、電晶體、瞬態電壓抑制二極體(TVS)、發光二極體等裝置的元件。但在本發明其他實施例中,該半導體元件是含有多數半導體裝置的元件,例如垂直堆疊、水平排列或垂直堆疊/水平排列多數半導體裝置所形成的半導體元件。 In some embodiments of the present invention, the semiconductor device is a device containing a single semiconductor device, such as a device containing a single diode, rectifier, transistor, transient voltage suppression diode (TVS), light emitting diode, etc. . However, in other embodiments of the present invention, the semiconductor device is a device containing a plurality of semiconductor devices, for example, a semiconductor device formed by a vertical stack, a horizontal arrangement, or a vertical stack/horizontal arrangement of a plurality of semiconductor devices.
在本發明的某些特定實施例中,該兩個半導體元件中的一個,可為單純的導電元件或單純的絕緣元件。 In some specific embodiments of the present invention, one of the two semiconductor elements may be a simple conductive element or a simple insulating element.
本發明的第一、第二、第三基板,通常為導電基板。但在特定的實施例中,至少一個基板可為絕緣基板。 The first, second, and third substrates of the present invention are usually conductive substrates. However, in certain embodiments, at least one substrate may be an insulating substrate.
在本發明的較佳實施例中,該第一、第二、第三基板中至少一基板可以提供台形突出。該台形突出可用以形成穩定的電性接觸。但在本發明的某些實施例中,該台形突出可用以調整第二基板及/或第三基板與第一基板的間距。 In a preferred embodiment of the present invention, at least one of the first, second, and third substrates may provide mesa-shaped protrusions. The mesa protrusion can be used to form a stable electrical contact. However, in some embodiments of the present invention, the mesa protrusion can be used to adjust the distance between the second substrate and/or the third substrate and the first substrate.
在本發明的特定實施例中,半導體元件封裝結構包括:多個半導體元件,與該半導體元件數量相同的多數第一基板,及與該半導體元件數量相同的多數第二基板。該多數半導體元件分別配置在該多數第一基板上,使相鄰兩個半導體元件分別以其第一電極及第二電極,連接在該第一基板,並使該多 數第二基板分別連接該多數半導體元件的另一電極;其中:該第一基板與第二基板的距離實質相同;及絕緣體,填充在第一基板與該第二基板之間,以及第一基板與第一基板之間,及第二基板與該第二基板之間的空間。該第一電極與該第二電極極性可為相同或不同。 In a specific embodiment of the present invention, the semiconductor device packaging structure includes a plurality of semiconductor devices, a plurality of first substrates having the same number of semiconductor devices, and a plurality of second substrates having the same number of semiconductor devices. The plurality of semiconductor elements are respectively arranged on the plurality of first substrates, so that two adjacent semiconductor elements are connected to the first substrate with their first electrodes and second electrodes respectively, and the plurality of semiconductor elements are connected to the first substrate. The second substrates are respectively connected to the other electrode of the plurality of semiconductor elements; wherein: the distance between the first substrate and the second substrate is substantially the same; and an insulator filled between the first substrate and the second substrate, and the first substrate The space between the first substrate and the second substrate and the second substrate. The polarity of the first electrode and the second electrode may be the same or different.
本發明的設計具有擴充性。在一些較佳實施例中,以第一及第二半導體元件為一單元,該半導體元件封裝結構可以含有多數單元的半導體元件。該多數單元的半導體元件可以垂直堆疊、水平排列、垂直堆疊及水平排列等方式配置。如以垂直堆疊,在垂直相鄰的兩半導體元件間,可提供導電片連接兩者的不同電極。如以水平排列,在水平鄰近的兩半導體元件間,可提供導電片連接兩者的不同電極。該導電片也可以形成台形突出。 The design of the present invention is expandable. In some preferred embodiments, the first and second semiconductor devices are used as a unit, and the semiconductor device package structure may include a plurality of semiconductor devices. The semiconductor elements of the plurality of units can be arranged vertically, horizontally, vertically stacked, and horizontally arranged. If stacked vertically, between two vertically adjacent semiconductor elements, a conductive sheet can be provided to connect the two different electrodes. If arranged horizontally, a conductive sheet can be provided between two adjacent semiconductor elements to connect different electrodes of the two. The conductive sheet may also form a mesa-shaped protrusion.
本發明也提供一種半導體元件封裝方法。該方法包括:製備一片頂部基板。將導電材料施用在該頂部基板上,用來配置半導體元件的表面上的預定位置。將多數半導體元件布放在頂部基板對應的導電材料置上,使每兩個半導體元件以不同電極電性連接到該頂部基板。製備一片底部基板。在該底部基板的預定位置施用導電材料。該底部基板的預定位置對應於該頂部基板的預定位置。將該底部基板與該頂部基板結合,使該多數半導體元件接觸該頂部基板上的導電材料,並予固定。如有必要,可施加熱或壓力,使導電材料將半導體元件黏附在頂部基板與底部基板上。 The present invention also provides a method for packaging semiconductor elements. The method includes preparing a top substrate. A conductive material is applied on the top substrate to configure a predetermined position on the surface of the semiconductor element. Most semiconductor elements are placed on the corresponding conductive material of the top substrate, so that every two semiconductor elements are electrically connected to the top substrate with different electrodes. Prepare a piece of bottom substrate. A conductive material is applied to a predetermined position of the base substrate. The predetermined position of the bottom substrate corresponds to the predetermined position of the top substrate. The bottom substrate and the top substrate are combined, so that the plurality of semiconductor elements contact the conductive material on the top substrate and are fixed. If necessary, heat or pressure can be applied to make the conductive material adhere the semiconductor element on the top substrate and the bottom substrate.
接著,在該頂部基板與底部基板之間的空間中填充絕緣體。施作時可藉由毛細現象,或壓力灌膠或抽真空等方式,從兩基板間的空隙進行填膠,以形成絕緣層。在該底部基板上形成分隔區,以使每單位的底部基板形成第一底部基板及第二底部基板。其中,每一單位可包含兩個相鄰,並以不同極性電 性連接到該頂部基板的半導體元件。形成分隔區的方法可採用化學蝕刻方法或雷射切除方法。如有必要,可在該頂部基板背向該半導體元件的表面施以防焊層。 Next, an insulator is filled in the space between the top substrate and the bottom substrate. The gap between the two substrates can be filled by capillary phenomenon, pressure pouring or vacuuming to form an insulating layer. A partition is formed on the base substrate so that each unit of the base substrate forms a first base substrate and a second base substrate. Among them, each unit can contain two adjacent units with different polarities. Sexually connected to the semiconductor element of the top substrate. The method of forming the partition can be a chemical etching method or a laser ablation method. If necessary, a solder resist layer can be applied to the surface of the top substrate away from the semiconductor element.
以上所封裝完成的結構,具有多數的半導體封裝結構單元。整體結構中,除了頂部基板與底部基板之間的空間中填充絕緣體外,在每兩個底部基板之間也可填充絕緣體。但也可保留分隔區。如此完成的封裝結構適於存放、運送及交易。該結構體最後可經切割作業,形成多數單元的半導體元件封裝結構,每單元包含兩個相鄰,並以不同極性電性連接到該頂部基板的半導體元件。 The structure completed above has a large number of semiconductor packaging structural units. In the overall structure, in addition to filling the insulator in the space between the top substrate and the bottom substrate, an insulator can also be filled between every two bottom substrates. However, the partition can also be reserved. The package structure thus completed is suitable for storage, transportation and transaction. Finally, the structure can be cut to form a semiconductor device packaging structure with multiple units, each unit includes two adjacent semiconductor devices electrically connected to the top substrate with different polarities.
在上述步驟中,該形成絕緣層之封裝結構可另以高溫烘烤,使該絕緣層固化。 In the above steps, the package structure forming the insulating layer can be baked at a high temperature to cure the insulating layer.
上述及其他本發明的目的及優點,可從以下詳細說明並參考下列圖式,而更形清楚。 The above and other objectives and advantages of the present invention can be more clearly illustrated from the following detailed description and with reference to the following drawings.
100A:半導體裝置堆疊結構 100A: Semiconductor device stack structure
100B:半導體裝置堆疊結構 100B: Semiconductor device stack structure
101:半導體裝置 101: Semiconductor device
101A~101N:半導體裝置 101A~101N: Semiconductor device
102A~102(N-1)、04A~104(N-1):錫膏 102A~102(N-1), 04A~104(N-1): solder paste
103A~103(N-1):銅粒 103A~103(N-1): Copper grain
103:導電金屬板 103: Conductive metal plate
103:銅粒 103: Copper grain
111:頂面第一電極 111: Top first electrode
121:底面第二電極 121: bottom second electrode
131:半導體晶片 131: Semiconductor wafer
141:護封材料 141: Sheath material
300:半導體元件封裝結構 300: Semiconductor component packaging structure
301:半導體元件 301: Semiconductor components
301A:第一半導體元件 301A: The first semiconductor component
301B:第二半導體元件 301B: second semiconductor element
302:頂部基板 302: Top substrate
303A、303B:底部基板 303A, 303B: bottom substrate
303A’:第一電極的一部份 303A’: Part of the first electrode
303B’:第二電極的一部份 303B’: Part of the second electrode
304:分隔區 304: partition
304A:第二分隔區 304A: second compartment
305A、305B、305C:絕緣層 305A, 305B, 305C: insulating layer
306:防焊層 306: solder mask
600:半導體元件封裝結構 600: Semiconductor component packaging structure
700A:半導體元件封裝結構 700A: Semiconductor component packaging structure
700B:半導體元件封裝結構 700B: Semiconductor component packaging structure
701B、702B:台形 701B, 702B: platform shape
800:半導體封裝單元 800: Semiconductor packaging unit
801A:第一頂部區塊 801A: First top block
801B:第二頂部區塊 801B: second top block
803A:第一底部基板 803A: First bottom substrate
803B:第二底部基板 803B: second bottom substrate
900:半導體元件封裝結構 900: Semiconductor component packaging structure
901:頂部絕緣基板 901: Top insulating substrate
902:底部絕緣基板 902: bottom insulating substrate
901A:第四導電膜 901A: Fourth conductive film
901B:第一導電膜 901B: The first conductive film
901D:第一導電柱 901D: The first conductive pillar
902A:第五導電膜 902A: Fifth conductive film
902B:第六導電膜 902B: sixth conductive film
902C:第二導電膜 902C: second conductive film
902D:第三導電膜 902D: Third conductive film
902F:第二導電柱 902F: second conductive pillar
902G:第三導電柱 902G: third conductive pillar
1100A:半導體元件封裝結構 1100A: Semiconductor component packaging structure
1100B:半導體元件封裝結構 1100B: Semiconductor component packaging structure
圖1顯示一種業界常見的半導體裝置堆疊結構。 FIG. 1 shows a common semiconductor device stack structure in the industry.
圖2另一種適用於本發明的半導體裝置的堆疊結構。 FIG. 2 is another stacked structure suitable for the semiconductor device of the present invention.
圖3顯示本發明半導體元件封裝結構的一種實施方式示意圖。 FIG. 3 shows a schematic diagram of an embodiment of the semiconductor device packaging structure of the present invention.
圖4顯示一種適用在本發明的單一裝置半導體元件結構示意圖。 FIG. 4 shows a schematic diagram of the structure of a single device semiconductor device applicable to the present invention.
圖5顯示本發明半導體元件封裝方法一種較佳實施例的方法流程圖。 FIG. 5 shows a method flowchart of a preferred embodiment of the semiconductor device packaging method of the present invention.
圖6顯示本發明半導體元件封裝結構第二種實施方式結構示意圖。 FIG. 6 shows a schematic structural view of a second embodiment of the semiconductor device packaging structure of the present invention.
圖7A顯示本發明一種適用在僅含單一或少數半導體裝置的半導體元件封裝結構示意圖。圖7B顯示實施例3的一種變化例的結構示意圖。 FIG. 7A shows a schematic diagram of a semiconductor device package structure of the present invention which is applicable to only a single or a few semiconductor devices. FIG. 7B shows a schematic structural diagram of a modification of Embodiment 3. FIG.
圖8顯示實施例2的半導體元件封裝結構的變化例示意圖。 FIG. 8 shows a schematic diagram of a modification of the semiconductor device packaging structure of the second embodiment.
圖9顯示圖8的半導體元件封裝結構的製作方法流程圖。 FIG. 9 shows a flowchart of a manufacturing method of the semiconductor device packaging structure of FIG. 8.
圖10即顯示圖8的實施例半導體元件封裝結構一種變化例的結構示意圖。 FIG. 10 is a structural diagram showing a variation of the semiconductor device packaging structure of the embodiment of FIG. 8.
圖11顯示圖3實施例的半導體元件封裝結構另一種變化例的結構示意圖。 FIG. 11 shows a schematic structural view of another variation of the semiconductor device packaging structure of the embodiment in FIG. 3.
圖12顯示圖3實施例的半導體元件封裝結構的一種堆疊應用結構示意圖。 FIG. 12 shows a schematic diagram of a stacked application structure of the semiconductor device packaging structure of the embodiment of FIG. 3.
圖13顯示圖12實施例的方法流程圖。 FIG. 13 shows a flowchart of the method in the embodiment of FIG. 12.
圖14表示本發明半導體元件封裝結構施加防焊層的一種實施型態示意圖。其中,圖A表示其縱切面圖,圖B表示其底視圖。 FIG. 14 shows a schematic diagram of an implementation mode of applying a solder resist layer to the semiconductor device packaging structure of the present invention. Among them, Figure A shows its longitudinal section view, and Figure B shows its bottom view.
本發明提供一種新穎的半導體元件封裝結構,以及用來形成新發明結構的半導體元件封裝方法。以下將以實施例說明本發明半導體元件封裝結構與半導體元件封裝方法的幾種較佳實施型態,藉使讀者容易理解本發明的主要技術特徵。但實施例的說明內容,尚不得用來限制本發明的範圍。本行業具有相當知識、技術的人士,當可從實施例的說明,掌握本發明的精神,並做出各種可能的變化與衍伸。這些變化與衍伸仍然屬於本發明的專利範圍。 The present invention provides a novel semiconductor element packaging structure and a semiconductor element packaging method for forming the new invention structure. Hereinafter, embodiments will be used to illustrate several preferred implementations of the semiconductor device packaging structure and semiconductor device packaging method of the present invention, so that the reader can easily understand the main technical features of the present invention. However, the description content of the embodiments shall not be used to limit the scope of the present invention. Those with considerable knowledge and skills in the industry can grasp the spirit of the invention from the description of the embodiments and make various possible changes and extensions. These changes and extensions still belong to the patent scope of the present invention.
實施例1 Example 1
圖3顯示本發明半導體元件封裝結構的一種實施方式示意圖。圖中所示的半導體元件封裝結構300基本上具有一個頂部基板302,兩個底部基板303A、303B,以及兩個半導體元件301,即第一半導體元件301A與第二半導體元件301B。在這種基本結構中,該頂部基板302與該底部基板303A、303B為電導體。該半導體元
件301、301個別包含至少一個半導體裝置。每個半導體裝置具有一個頂面第一電極及一個底面第二電極。該第一電極與該第二電極極性相反,並以該頂部基板302串接該兩個半導體元件301。
FIG. 3 shows a schematic diagram of an embodiment of the semiconductor device packaging structure of the present invention. The semiconductor
此行業人士均知,該第一電極與該第二電極極性也可為相同。例如,在雙極性半導體元件的情形,該半導體元件的頂面電極與底面電極極性相同。該第一電極與該第二電極極性即為相同。因此,在本說明書以下的說明中,雖然主要以第一電極與該第二電極極性相反的半導體元件為實例,但任何雙極性半導體元件均可應用到本發明。在這種情形,如為特別說明,在各該實施例中,該第一電極與該第二電極極性可為相同或不同。 Those in the industry know that the polarity of the first electrode and the second electrode can also be the same. For example, in the case of a bipolar semiconductor element, the top electrode and the bottom electrode of the semiconductor element have the same polarity. The first electrode and the second electrode have the same polarity. Therefore, in the following description of this specification, although a semiconductor element in which the first electrode and the second electrode have opposite polarities is mainly taken as an example, any bipolar semiconductor element can be applied to the present invention. In this case, if specified, in each of the embodiments, the polarity of the first electrode and the second electrode may be the same or different.
圖4顯示一種適用在本發明半導體元件封裝結構的半導體元件301結構示意圖。如圖所示,該半導體元件具有單一的半導體裝置101。該半導體裝置101包含一個頂面第一電極111及一個底面第二電極121,以及介於該頂面第一電極111和底面第二電極121之間,並電性連接該頂面第一電極111和底面第二電極121的半導體晶片131。該第一電極111與該第二電極極性121相反,亦即,其中一者為陽極,另一者為陰極。但若為雙極性元件則第一電性與第二電極極性相同。圖中也顯示在該半導體裝置101的側邊具有護封材料141。
FIG. 4 shows a schematic structural diagram of a
該半導體裝置101可以為任何半導體電氣或電路裝置。在本發明的較佳實施例中,該半導體裝置101為二極管裝置,亦即該半導體晶片131單純僅是二極管裝置。但其他半導體裝置,例如整流器、電晶體、瞬態電壓抑制二極體(TVS)、發光二極體等裝置,也可以應用在本發明。
The
該頂面第一電極111和底面第二電極121通常是以導電材料的薄板製成。較佳的實例為在半導體晶片131兩面鍍上金屬薄膜。但其他可以應用在
半導體裝置101的任何導電材質金屬薄膜,都可以應用在本發明。該頂面第一電極111和底面第二電極121可以使用導電金屬薄膜,接觸並夾持該半導體裝置101。也可使用導電材料膏劑直接塗布該半導體裝置101頂面及底面而形成。該護封材料141通常是電絕緣材料,例如塑膠材料、樹脂材料、含矽材料、玻璃材料、陶瓷材料等。以適用的方式包圍該半導體裝置101的周緣。
The top
該半導體元件301也可包含多數的半導體裝置。其中一種適用的實例就是半導體裝置的堆疊結構。一種業界常見的半導體裝置堆疊結構,顯示於圖1。圖中所顯示的半導體裝置堆疊結構100A包含多個(N個,N為正整數)半導體裝置101A~101N,形成堆疊。導電黏著材料例如錫膏102A~102(N-1)則介於每兩個半導體裝置之間。該半導體裝置101A~101N的每一個都具有與前述圖4所示半導體裝置101相同的結構,亦即具有頂面第一電極111、底面第二電極121,介於頂面第一電極111和底面第二電極121之間,並電性連接該頂面第一電極111和底面第二電極121的半導體晶片131,以及護封材料141,但其電路、功能可為相同或不同。所有的半導體裝置101A~101N的極性方向相同,堆疊後形成串接。但也可安排其堆疊方式,使得堆疊結構的頂面電極與底面電極極性相同。所使用的半導體裝置101A~101N數量N並無特別限制,但考慮所形成的半導體裝置堆疊結構100A厚度,該半導體裝置101A~101N的數量N通常在10以下,較佳在5以下,並與該半導體裝置101A~101N本身的厚度有關。在這種半導體裝置堆疊結構中,第一半導體裝置101A的頂面第一電極和第N半導體裝置101N的底面第二電極,即成為該半導體裝置堆疊結構100A的頂面第一電極111和底面第二電極121。
The
另一種適用的半導體裝置的堆疊結構顯示於圖2。圖中所顯示的半導體裝置堆疊結構100B也包含N個半導體裝置101A~101N,形成堆疊。但介於每兩個半導體裝置之間的材料是導電金屬板,例如銅粒103A~103(N-1)。該半導體裝置101A~101N的每一個都具有與前述圖4所示半導體裝置101相同的結構,亦即具有頂面第一電極111、底面第二電極121,介於頂面第一電極111和底面第二電極121之間,並電性連接該頂面第一電極111和底面第二電極121的半導體晶片131,以及護封材料141,但其電路、功能可為相同或不同。該導電金屬板103A~103(N-1)可以直接與個別對應的半導體裝置101A~101N的頂面第一電極和底面第二電極接觸,也可透過導電黏著材料,例如錫膏102A~102(N-1)及104A~104(N-1),才與該頂面第一電極和底面第二電極接觸。在這種半導體裝置堆疊結構中,第一半導體裝置101A的頂面第一電極和第N半導體裝置101N的底面第二電極,即成為該半導體裝置堆疊結構100B的頂面第一電極111和底面第二電極121。
Another suitable stacked structure of semiconductor devices is shown in FIG. 2. The semiconductor
在該半導體裝置堆疊結構100B中,導電黏著材料是作為半導體裝置與導電金屬板的連接媒介,而導電金屬板則可提供半導體裝置之間的緩衝,減少半導體裝置在堆疊過程中因為應力造成損傷,達到半導體元件的保護效果。此外,如果以銅粒製作該導電金屬板,則在大電流應用時可提升散熱效應,對半導體元件作用時產生的熱能提供良好的散熱空間。
In the semiconductor
上述兩種半導體裝置堆疊結構100A與100B各有優缺點。半導體裝置堆疊結構100A因為未使用導電金屬板103,優點為可堆疊的半導裝置101數量較多,獲得較高的使用功率。缺點則是因為未使用導電金屬板103作為應力緩衝及散熱媒介,故在堆疊過中半導體裝置101易因應力而受到損傷,且散熱效果則
較差。半導體裝置堆疊結構100B因為透過導電金屬板103進行堆疊,在堆疊過程中較不易因應力受損,散熱性較佳。但缺點為半導體裝置101堆疊數量較少,無法獲得較高的使用功率。
The above two semiconductor
除了上述3種型態的半導體元件301之外,其他型態或結構的半導體元件,均可利用本發明的封裝方法,形成本發明的封裝結構。
In addition to the above-mentioned three types of
請參考圖3。圖3所示的半導體元件封裝結構中,頂部基板302連接兩個半導體元件301。亦即,使第一半導體元件301A的極性方向與第二半導體元件301B的極性方向相反(亦可具雙極性特性),並使第一半導體元件301A的底面第二電極及第二半導體元件301B的頂面第一電極均與該頂部基板302電性接觸。此外,使第一半導體元件301A的頂面第一電極與該底部基板中的第一底部基板303A電性接觸,並使第二半導體元件301B的底面第二電極與底部基板中的第二底部基板303B電性接觸。該頂部基板302與兩底部基板303A、303B形成電性絕緣,且該第一底部基板303A與該底部基板303B也形成電性絕緣。如此形成的電路結構,該第一底部基板303A即表現該電路的第一極性,而該第二底部基板303B則表現該電路的第二極性。且該第一底部基板303A與該第二底部基板303B朝向實質相同的方向。
Please refer to Figure 3. In the semiconductor device packaging structure shown in FIG. 3, the
該頂部基板302與該底部基板303A、303B可使用任何導電材料製作。與前述相同,該頂部基板302與該底部基板303A、303B可以導電材料的薄板製成。較佳的實例包括銅箔、鋁板等常見的導電材料薄板。但其他可以應用在半導體元件封裝的導電材料,無論其形式為薄板或膏劑,都可以應用在本發明。
The
較好使該頂部基板302與該底部基板303A、303B面對該半導體元件301A、301B的表面形成突起或台狀,以使基板與半導體元件電極之間的接觸
更形穩固。但該突起或台狀並非任何技術限制。此外,較好使用導電黏著材料,例如錫膏102A~102D,將該半導體元件301A、301B固著在該頂部基板302與該底部基板303A、303B上。
Preferably, the surfaces of the
在該頂部基板302與該底部基板303A、303B之間的空間,填充絕緣層305A~305C。該絕緣層305A~305C可使用任何電性絕緣材料。較佳的實例包括塑膠材料、樹脂材料、含矽材料、玻璃材料、陶瓷材料等不導電,固化前容易流動的材料。較佳為環氧樹脂材料。在兩個底部基板303A、303B之間,通常會形成分隔區304。該分隔區304可以該絕緣層305A~305C的材料填充,也可以其他絕緣材料填充,以使結構更為完整。但不填充材料也無不可。
The spaces between the
為應用便利,可在該頂部基板302上表面施用防焊層306。防焊層306可以保護該頂部基板302,避免該頂部基板302與其他物件形成電性接觸。底部基板303A、303B則視情況需求可不施用防焊層,亦可於表面施用防焊層,利用防焊層覆蓋出第一電極及第二電極的露出形狀及外形,因此,該防焊層306可使用電性絕緣材料。適用的材料已如上述。該防焊層306較好使用固化後能產生堅硬表面的絕緣材料。
For application convenience, a
在上述的半導體元件封裝結構中,頂部基板302及底部基板303A、303B提供電特性傳遞並保護半導體元件或半導體裝置堆疊結構301。絕緣層可包覆半導體元件,達到隔絕水氣、避免與外物碰觸等保護功用。
In the semiconductor device packaging structure described above, the
以下說明圖3所示的半導體元件封裝結構的封裝方法。圖5顯示本發明半導體元件封裝方法一種較佳實施例的方法流程圖。該方法主要是用來製作如圖3所示的半導體元件封裝結構。 The packaging method of the semiconductor element packaging structure shown in FIG. 3 will be described below. FIG. 5 shows a method flowchart of a preferred embodiment of the semiconductor device packaging method of the present invention. This method is mainly used to manufacture the semiconductor device packaging structure as shown in FIG. 3.
如圖所示,於步驟501,製備一片頂部基板302。在大量生產的程序中,該頂部基板302是用來支援多數的半導體元件封裝結構單元。在本實施例中,每一個半導體元件封裝結構單元包含兩個半導體元件。於步驟502,將導電黏著材料,例如錫膏102A及102C以點附或印刷等方法,施加在該頂部基板302上,用來配置半導體元件301的表面上的預定位置。於步驟503將半導體元件301布放在對應的錫膏102A及102C位置上,以將半導體元件301固定,並電性連接到該頂部基板302。在此步驟應該注意,使每單位的兩個半導體元件301A、301B位在相鄰的錫膏102A及102C點,並使其極性方向相反。但如為雙極性元件,則無極性方向配置的問題。
As shown in the figure, in
接著,在步驟504製備一片底部基板。該底部基板也是用來支援多數的半導體元件封裝結構單元。在該底部基板的預定位置施加導電黏著材料,例如錫膏102B及102D。該底部基板的預定位置對應於該頂部基板的預定位置。於步驟505將該底部基板與該頂部基板結合,使底部基板上的個別錫膏102B電性接觸該頂部基板上的第一半導體元件301A,並使底部基板上的個別錫膏102D電性接觸該頂部基板上的第二半導體元件301B,並予固定。如有必要,可施加熱或壓力,使導電黏著材料102A、102B、102C、102D將半導體元件301A、301B牢牢黏附在頂部基板302與底部基板上。
Next, in
於步驟506在該頂部基板302與底部基板之間的空間中填充絕緣層305A、305B、305C。施作時可藉由毛細現象,或壓力灌膠或抽真空等方式從兩基板間的空隙進行填膠,以形成絕緣層。完成後將該已經形成絕緣層之封裝結構,以烤箱進行烘烤,使該絕緣層固化。於步驟507,在該底部基板上形成分隔區304,以使每單位的底部基板形成第一底部基板303A及第二底部基板
303B。所可採用的加工方式包括以化學蝕刻方法形成該分隔區304。之後,於步驟508,在該頂部基板302背向該半導體元件301A、301B的表面施以防焊層306,底部基板303A、303B背向該半導體元件301A、301B的表面(含兩基板間表面),則視需求而施以防焊層306,並依應用的需求露出電極形狀。最後於步驟509進行切割作業,形成多數單元的半導體元件封裝結構300,每單元包括預訂的半導體元件301A、301B。
In
以上述方法所製成的半導體元件封裝結構300即如圖3所示。該結構與習知的半導體元件封裝結構完全不同。習知的半導體元件封裝結構中僅包含一個半導體元件或半導體裝置堆疊結構。但本發明的半導體元件封裝結構在相同高度下可以包含兩個半導體元件或半導體裝置堆疊結構,故可獲得較高的功率瓦數。使用在封裝半導體裝置堆疊時,本發明使用層數減少的兩個半導體裝置堆疊結構,但仍能提供原來的功率能力。亦即,在相同功率瓦數之下,本發明可以大大降低半導體元件封裝結構的厚度。此外,本發明的半導體元件封裝結構雖然使結構變長,但該封裝結構的第一與第二電極已經朝向實質相同的方向。習知的封裝結構如果要達成這種應用,必須加設導電引腳。所形成的結構長度實質上與本發明並無顯著差異。
The semiconductor
實施例2 Example 2
圖6顯示本發明半導體元件封裝結構第二種實施方式結構示意圖。圖6所示的實施例中,每單元的半導體元件封裝結構也是包括兩個元件,但兩者為不同性質的元件。例如,可為一個半導體元件與一個導電元件。 FIG. 6 shows a schematic structural view of a second embodiment of the semiconductor device packaging structure of the present invention. In the embodiment shown in FIG. 6, the semiconductor device packaging structure of each unit also includes two components, but the two are components of different properties. For example, it can be a semiconductor element and a conductive element.
如圖6所示,本實施例的半導體元件封裝結構600也是包含一個頂部基板302和兩個底部基板303A及303B。但介於其間的是半導體元件301與導電
元件,例如單純的銅粒103。該半導體元件封裝結構600另外還包括用來將半導體元件301與導電元件連接到頂部基板302和兩個底部基板303A、303B的導電黏著材料,例如錫膏102A~102D,分隔底部基板303A及303B的分隔區304,填充在基板之間空間的絕緣層305A~305C,以及頂部基板302的防焊層306。
As shown in FIG. 6, the semiconductor
圖6所示結構較適用於半導體裝置堆疊結構。換言之,該半導體元件301較好是一個半導體裝置堆疊結構,可為半導體裝置堆疊結構100A或半導體裝置堆疊結構100B。這種半導體裝置堆疊結構具有相當的厚度,如果應用在例如表面黏著工法,需使其兩電極均位在同一方向。習知技術乃使用導電引腳將上方電極延伸到下方。但如果利用本發明的半導體元件封裝結構,則只要將圖3所示的結構中的第二半導體元件301B以導電元件,例如銅粒103代替,就可輕易完成兩電極均位在同一方向的半導體元件封裝結構。
The structure shown in FIG. 6 is more suitable for a stacked structure of a semiconductor device. In other words, the
圖6所示的半導體元件封裝結構基本上與圖3的實施例相同。只是將圖3所示的結構中的第二半導體元件301B以導電元件,例如銅粒103代替。該半導體元件封裝結構的製作方法,也與圖5所示的方法步驟相同。只是在該頂部基板302上配布多數半導體元件301時,是兩兩交替的配布半導體元件301與銅粒103或適用的導電元件。其詳細應不須在此贅述。
The semiconductor device package structure shown in FIG. 6 is basically the same as the embodiment of FIG. 3. It is just that the
圖6所示的半導體元件封裝結構600與習知半導體元件封裝結構完全不同。習知技術必須使用導線架製程(Lead Frame),製造程序較為繁瑣。但本實施例的半導體元件封裝結構600則是採用上下兩片金屬板陣列大量生產,再予切割的方式,可以大幅簡化生產程序。此外,本發明使用簡單的金屬基板,可以形成較薄的外型尺寸。該半導體元件封裝結構600採用填膠方式,較之習知結構的模塑方式,可以大量減少膠材的浪費。
The semiconductor
實施例3 Example 3
實施例2的結構稍經修改,即可使用在單一半導體裝置的封裝。如前所述,半導體裝置堆疊結構具有相當的高度。在將本發明的半導體元件封裝結構使用在僅包含單一或少數半導體裝置的半導體元件時,可以根據需要改變該頂部基板302及/或底部基板303A、303B上的突起或台形的高度或有無,以順應需求。圖7A即顯示本發明一種適用在僅含單一或少數半導體裝置的半導體元件封裝結構示意圖。如圖所示,在本實施例中,該半導體元件封裝結構700A也是具有一個頂部基板302和兩個底部基板303A及303B,以及介於其間的半導體元件301與導電黏著材料,例如錫膏102B。該半導體元件封裝結構700A還包括用來將半導體元件301連接到頂部基板302和底部基板303A的錫膏102A、102C,分隔底部基板303A及303B的分隔區304,填充在基板之間空間的絕緣層305A~305C,以及頂部基板302的防焊層,或另有視需求施加的底部基板303A、303B的防焊層。
The structure of the second embodiment can be used in the package of a single semiconductor device with slight modification. As mentioned above, the stacked structure of semiconductor devices has a considerable height. When the semiconductor device packaging structure of the present invention is used for semiconductor devices containing only a single or a few semiconductor devices, the height or presence or absence of protrusions or mesas on the
該防焊層的覆蓋範圍不限於覆蓋基板的全部面積。圖14顯示這類實施例另一種實施型態半導體元件封裝結構示意圖。圖中,上方圖A表示其縱切面圖,圖B表示其底視圖。圖中顯示,底部基板303A、303B背向該半導體元件301A、301B的外側表面(含兩基板間表面),視需要施用防焊層306,並依應用需求使防焊層的覆蓋部分形成圖形,露出第一電極的一部份303A’,以及第二電極的一部份303B’。
The coverage of the solder mask is not limited to covering the entire area of the substrate. FIG. 14 shows a schematic diagram of a semiconductor device package structure of another implementation type of this type of embodiment. In the figure, the upper figure A shows the longitudinal section view, and the figure B shows the bottom view. As shown in the figure, the
承上說明。圖7A中的結構與圖6不同的是,第一底部基板303A並沒有提供突起或台形,而頂部基板302則在與半導體元件301的接觸區提供台形701A,在與該錫膏102B的接觸區提供台形701B,且該第二底部基板303B也在與該錫膏102B的接觸區提供台形702B。在這種設計下,兩台形701B與702B的高度
使得兩基板在該部分的距離縮小,只需在其中填充導電黏著材料,就可使兩基板形成電性接觸。
Follow the instructions. The structure in FIG. 7A is different from FIG. 6 in that the first
在本實施例中,除了以台形的有無調整兩基板間距之外,也可以台形的高度調整兩基板間距。例如,台形701B及/或台形702B的高度,可以略高於台形701A的高度。也可在第一底部基板303A也提供台形,但使台形701B與台形702B的高度和大於台形701A與該第一底部基板303A的台形的高度和。
In this embodiment, in addition to adjusting the distance between the two substrates by the presence or absence of the mesa shape, the distance between the two substrates may also be adjusted by the height of the mesa shape. For example, the height of the
此外,圖7B另外顯示實施例3的一種變化例的結構示意圖。圖7A中的半導體元件封裝結構700B僅在頂部基板302及在第二底部基板303B與該錫膏102B的接觸區提供台形701B、702B。這種結構同樣可以達成調整兩基板間距的目的。
In addition, FIG. 7B additionally shows a schematic structural diagram of a modification of Embodiment 3. The semiconductor
此外,在台形701B、702B之間提供導電元件(材料),例如銅粒,也可達成額外調整兩基板間距的目的。該銅粒可以與台形合併應用,達成精確的間距調整。
In addition, providing conductive elements (materials) between the
本實施例的半導體元件封裝結構與前述兩種時施例相同。其封裝方法也是相同,但須在製備該頂部基板302與底部基板303A、303B的步驟中,選擇特定的區域形成上述台形。形成台形的方法包括模塑、焊接、熔接、蝕刻等,不一而足。此行業人士均可視應用需要選用。
The semiconductor device packaging structure of this embodiment is the same as the foregoing two embodiments. The packaging method is also the same, but in the steps of preparing the
實施例4 Example 4
實施例2顯示一種包含一個半導體元件與一個導電元件的半導體元件封裝結構。在實施例2中,該半導體元件封裝結構600是使用金屬薄板作為其頂部基板302與底部基板303A、303B。不過,該頂部基板302與該底部基板303A、303B
事實上可以絕緣基板取代,以降低生產成本。圖8即顯示這種應用實例的半導體元件封裝結構示意圖。
Embodiment 2 shows a semiconductor device package structure including a semiconductor device and a conductive device. In the second embodiment, the semiconductor
如圖8所示,該半導體元件封裝結構包含一片頂部絕緣基板901和一片底部絕緣基板902,以及介於兩者之間的半導體元件301與導電元件,例如單純的銅粒103。在該頂部絕緣基板901的內側,亦即接近該半導體元件301與銅粒103的一側,形成第一導電膜901B。該第一導電膜901B通常為導電金屬膜,以塗布、黏貼、蝕刻成形等方式,形成在該頂部絕緣基板901的內側。在該頂部絕緣基板901的外側,對應於該第一導電膜901B的區域,還可以形成第四導電膜901A。該第四導電膜901A的材質與製作方式與該第一導電膜901B相同或類似。導電黏著材料,例如錫膏102A與102C將該半導體元件301與銅粒103與該第一導電膜901B做電性連接。
As shown in FIG. 8, the semiconductor device packaging structure includes a top insulating
在該底部絕緣基板902的內側,亦即接近該半導體元件301與銅粒103的一側,對應於該半導體元件301與該銅粒103的區域,分別形成第二導電膜902C與第三導電膜902D。在該底部絕緣基板902的外側還可以形成第五及第六導電膜902A、902B。該第五導電膜902A位在該底部絕緣基板902外側,對應於該第二導電膜902C的區域。該第六導電膜902B位在該底部絕緣基板902外側,對應於該第三導電膜902D的區域。該第二導電膜902C與第三導電膜902D電性隔絕,且該第五導電膜902A與第六導電膜902B電性隔絕。該第二、第三、第五、第六導電膜902C、902D、902A、902B的材質與製作方式與該第一導電膜901B相同或類似。導電黏著材料,例如錫膏102B與102D將該半導體元件301與銅粒103分別與該第三導電膜902D及第二導電膜902C做電性連接。
On the inner side of the
該頂部絕緣基板901、底部絕緣基板902可為玻璃纖維基板或任何容易加工的絕緣材料。為降低成本,通常可使用塑膠、樹脂、紙類等材料製作。其中以環氧樹脂為較佳材質,因其成本低廉,容易取得。由於頂部絕緣基板901、底部絕緣基板902為絕緣體,故在該第一導電膜901B與該第四導電膜901A重疊的位置,形成穿越該頂部絕緣基板901的孔洞,並在孔洞內充填導電材料或在孔壁上形成導電金屬薄膜,例如金屬材料、導電膏,以形成第一導電柱901D。在該第二導電膜902C與該第五導電膜902A重疊的位置,形成穿越該底部絕緣基板902的孔洞,並在孔洞內充填導電材料或在孔壁上形成導電金屬薄膜,例如金屬材料、導電膏,以形成第二導電柱902F。此外,並在該第三導電膜902D與該第六導電膜902B重疊的位置,形成穿越該底部絕緣基板902的孔洞,並在孔洞內充填導電材料或在孔壁上形成導電金屬薄膜,例如金屬材料、導電膏,以形成第三導電柱902G。
The top insulating
該半導體元件封裝結構1100A另外還包括用來填充兩絕緣基板之間空間的絕緣層305A~305C。如有必要還可包括頂部絕緣基板901與底部絕緣基板902外側表面上的防焊層306。
The semiconductor
如此形成的半導體元件封裝結構,該第六導電膜902B即成為其第一電極,而該第五導電膜902A即成為其第二電極。這種結構可以利用本發明的半導體元件封裝結構,取代實施例2的結構。
In the semiconductor device package structure formed in this way, the sixth
以下說明圖8所示半導體元件封裝結構的製作方法。圖9顯示本發明半導體元件封裝方法另一種較佳實施例的方法流程圖。該方法主要是用來製作如圖8所示的半導體元件封裝結構。 The manufacturing method of the semiconductor element package structure shown in FIG. 8 will be described below. FIG. 9 shows a method flowchart of another preferred embodiment of the semiconductor device packaging method of the present invention. This method is mainly used to manufacture the semiconductor device packaging structure as shown in FIG. 8.
如圖所示,於步驟1201,製備一片頂部絕緣基板901。在大量生產的程序中,該頂部絕緣基板901是用來支援多數的半導體元件封裝結構單元。在本實施例中,每一個半導體元件封裝結構單元包含一個半導體元件301以及一個導電元件,例如銅粒103。於步驟1202在該頂部絕緣基板901的內側表面,亦即用來配置半導體元件301與銅粒103的表面上,形成一層第一導電層901B。並在該頂部絕緣基板901的外側表面選定區域,形成第四導電層901A。形成該導電層901B、901A的方法包括以印刷、塗布、黏貼、蝕刻成形等方法,形成導電金屬薄層。於步驟1203,將導電黏著材料,例如錫膏102A及102C施加在該導電層901B上的預定位置。於步驟1204將多數的半導體元件301布放在對應的錫膏102C的位置上,並將多數的銅粒103布放在對應的錫膏102A的位置上,以將半導體元件301與銅粒103固定,並電性連接到該頂部絕緣基板901。
As shown in the figure, in
接著,在步驟1205製備一片底部絕緣基板902。該底部絕緣基板902也是用來支援多數的半導體元件封裝結構單元。於步驟1206在該底部絕緣基板902的內側表面,亦即用來配置半導體元件301與銅粒103的表面上,形成多數第二導電層902C及第三導電層902D。並在該底部絕緣基板902的外側表面,形成多數第五導電層902A及第六導電層902B。形成該金屬層的方法已如前述。於步驟1207,在該底部絕緣基板902的導電層上預定位置施加導電黏著材料,例如錫膏102B及102D。該底部絕緣基板導電層的預定位置對應於該頂部絕緣基板導電層的預定位置。於步驟1208將該底部絕緣基板902與該頂部絕緣基板901結合,使底部絕緣基板上902的個別錫膏102D電性接觸該頂部絕緣基板901上的半導體元件301,並使底部絕緣基板902上的個別錫膏102B電性接觸該頂部基板上的銅
粒103,並予固定。如有必要,可施加熱或壓力,使導電黏著材料102A、102B、102C、102D將半導體元件301A、301B牢牢黏附在頂部基板302與底部基板上。
Next, in
於步驟1209在該頂部絕緣基板901與底部絕緣基板902之間的空間中填充絕緣層305A、305B、305C。施作時可藉由毛細現象,或壓力灌膠或抽真空等方式,從兩基板間的空隙進行填膠,以形成絕緣層。完成後將該已經形成絕緣層之封裝結構,以烤箱進行烘烤,使該絕緣層固化。於步驟1210,在該第一導電膜901B與該第四導電膜901A重疊的位置,形成穿越該頂部絕緣基板901的孔洞,並在孔洞內充填導電材料,以形成第一導電柱901D。在該第二導電膜902C與該第五導電膜902A重疊的位置,形成穿越該底部絕緣基板902的孔洞,並在孔洞內充填導電材料或在孔壁上形成導電金屬薄膜,以形成第二導電柱902F。並在該第三導電膜902D與該第六導電膜902B重疊的位置,形成穿越該底部絕緣基板902的孔洞,並在孔洞內充填導電材料或在孔壁上形成導電金屬薄膜,以形成第三導電柱902G。形成孔洞的方法可以使用任何已知的方法,例如鑽孔、雷射切割或蝕刻等。所填充的導電材料也可為任何適用的材料,例如錫膏、銀膏、銅膏等。
In
如此即形成具有多數單元的半導體元件封裝結構,每個單元包括一個半導體元件301以及一個銅粒103。封裝結構的第一電極即第六導電膜902B經由第三導電柱902G,第三導電膜902D,導電材料102D電性連接至半導體元件301的第一電極。再從半導體元件301的第二電極經由導電材料102C、第一導電膜901B、導電材料102A、銅粒103、導電材料102B、第二導電膜902C、第二導電柱902F電形連接到封裝結構的第二電極,即第五導電膜902A。
In this way, a semiconductor device packaging structure with multiple units is formed, and each unit includes a
如有必要,可於步驟1211,在該頂部絕緣基板901與該底部絕緣基板902的外側表面,分別施以防焊層306。最後於步驟1212進行切割作業,形成多數單元的半導體元件封裝結構1100A。
If necessary, in
實施例5 Example 5
實施例4的封裝結構因使用絕緣基板,而可降低製作成本。雖然製程的半導體元件封裝結構體積較大,但結構也相對穩固。這種結構還可以透過不使用導電材料,例如銅粒的方式,進一步節省成本,但仍提供相當穩固的結構。圖10即顯示這種變化結構的結構示意圖。 The packaging structure of Embodiment 4 uses an insulating substrate, which can reduce the manufacturing cost. Although the semiconductor device package structure of the process is relatively large, the structure is relatively stable. This structure can further save costs by not using conductive materials, such as copper particles, but still provide a fairly stable structure. Figure 10 shows the structure diagram of this change structure.
如圖所示,本實施例的半導體元件封裝結構1100B與圖8的結構1100A相似,但免除該導電元件,例如銅粒103。圖10的半導體元件封裝結構1100B包含一片頂部絕緣基板901和一片底部絕緣基板902,以及介於兩者之間的半導體元件301。在該頂部絕緣基板901的內側,亦即接近該半導體元件301的一側,形成第一導電膜901B。在該頂部絕緣基板901的外側,離開該半導體元件301的位置,對應於該第一導電膜901B的區域,形成第四導電膜901A。導電黏著材料,例如錫膏102A將該半導體元件301與該第一導電膜901B做電性連接。
As shown in the figure, the semiconductor
在該底部絕緣基板902的內側,亦即接近該半導體元件301的一側,對應於該半導體元件301的區域,形成第三導電膜902D。在該底部絕緣基板902的內側,對應於該第四導電膜901A的區域,形成第二導電膜902C。在該底部絕緣基板902的外側,分別形成對應於該第二導電膜902C的第五導電膜902A,以及對應於該第三導電膜902D的第六導電膜902B。該第二導電膜902C與第三導電膜902D電性隔絕,且該第五導電膜902A與第六導電膜902B電性隔絕。導電黏著材料,例如錫膏102B將該半導體元件301與該第三導電膜902D做電性連接。
On the inner side of the
該半導體元件封裝結構1100B另外還包括用來填充兩絕緣基板之間空間的絕緣層305A~305C。如有必要還可包括頂部絕緣基板901與底部絕緣基板902外側表面上的防焊層306。
The semiconductor
在該第一導電膜901B與該第四導電膜901A重疊的位置,朝向該第二導電膜902C與該第五導電膜902A重疊的位置,形成穿越該頂部絕緣基板901、該絕緣層305A、305B,以及底部絕緣基板902的孔洞,並在孔洞內充填導電材料或在孔壁上形成導電金屬薄膜,例如金屬材料、導電膏,以形成第一導電柱901D。此外,並在該第三導電膜902D與該第六導電膜902B重疊的位置,形成穿越該底部絕緣基板902的孔洞,並在孔洞內充填導電材料,例如金屬材料,以形成第三導電柱902G。
At the position where the first
如此形成的半導體元件封裝結構,該第六導電膜902B即成為其第一電極,而該第五導電膜902A即成為其第二電極。這種結構可以利用本發明的半導體元件封裝結構,取代實施例6的結構。在這種結構中,每個單元包括一個半導體元件301。封裝結構的第一電極即第六導電膜902B經由第三導電柱902G,第三導電膜902D,導電材料102B電性連接至半導體元件301的第一電極。再從半導體元件301的第二電極經由導電材料102A、第一導電膜901B、第一導電柱901D電形連接到封裝結構的第二電極,即第五導電膜902A。
In the semiconductor device package structure formed in this way, the sixth
本實施例的半導體元件封裝結構的製作方法與實施例4大致相同,但省卻配置銅粒及其相關導電黏著材料的步驟。此外,在形成導電柱的步驟中,除了形成該第三導電柱902G之外,另外形成貫穿該頂部絕緣基板901、該絕緣層305A、305B,以及底部絕緣基板902的導電柱901D。
The manufacturing method of the semiconductor device packaging structure of this embodiment is substantially the same as that of Embodiment 4, but the step of disposing copper particles and related conductive adhesive materials is omitted. In addition, in the step of forming a conductive pillar, in addition to forming the third
實施例6 Example 6
在實施例1~3中,半導體元件封裝結構中的頂部基板302是形成一體,用來串接半導體元件301A和301B。但在特定的應用中,該頂部基板302也可以使用一個第二分隔區304A,分隔成電性隔離的第一頂部區塊801A與第二頂部區塊801B。
In
圖11即顯示本發明的半導體元件封裝結構一種適用在上述用途的實施例示意圖。如圖所示,本實施例的半導體封裝單元800在對應於前述實施例的頂部基板302的部分,包括第一頂部區塊801A與第二頂部區塊801B。其餘結構與實施例1相同,也是包括兩個底部基板303A及303B,介於第一頂部區塊801A與第二頂部區塊801B以及兩個底部基板303A及303B之間的半導體元件301。該半導體元件封裝單元800另外還包括用來將兩個半導體元件301連接到第一頂部區塊801A與第二頂部區塊801B,以及兩個底部基板303A、303B的導電黏著材料,例如錫膏102A~102D,分隔底部基板303A及303B的分隔區304,分隔兩個頂部區塊801A及801B的第二分隔區304A,填充在基板之間空間的絕緣層305A~305C。但在多數的應用中,並不需要在頂部基板(第一頂部區塊801A與第二頂部區塊801B)上施加防焊層。
FIG. 11 is a schematic diagram showing an embodiment of the semiconductor device packaging structure of the present invention suitable for the above-mentioned application. As shown in the figure, the
具有上述結構的半導體元件封裝結構,可以應用在多種特殊用途。舉例而言: The semiconductor device packaging structure with the above structure can be applied to a variety of special purposes. For example:
1.單純提供半導體的封裝-本實施例可以應用在對半導體裝置的堆疊結構提供封裝保護。習知的半導體裝置的堆疊結構在堆疊完成後,其多個半導體裝置都裸露在外,在保存及移動過程中易受外力碰撞或環境影響,造成單一或多個半導體元件受損。存放過程中也易受濕氣影響。本發明的半導體元件封裝結構及半導體元件封裝方法在半導體裝置堆 疊結構堆疊完後,以陣列形式在堆疊結構之外,加上一層絕緣層的保護,但仍提供頂部與底部兩電極,作為上下側的電極接點,並不會改變原來電性傳導的形式。本發明可以改良習知技術的堆疊方式,有效防止碰撞對堆疊元件造成的損傷,隔絕水氣的不良影響。 1. Simply provide semiconductor packaging-this embodiment can be applied to provide packaging protection for the stacked structure of semiconductor devices. After the stacking structure of the conventional semiconductor device is completed, a plurality of semiconductor devices are exposed to the outside, which is susceptible to external force impact or environmental impact during storage and movement, causing damage to a single or multiple semiconductor devices. It is also susceptible to moisture during storage. The semiconductor element packaging structure and the semiconductor element packaging method of the present invention are used in a semiconductor device stack After the stacked structure is stacked, add an insulating layer to the stacked structure in the form of an array, but still provide the top and bottom electrodes as the upper and lower electrode contacts, and will not change the original electrical conduction form . The invention can improve the stacking method of the conventional technology, effectively prevent damage to the stacking element caused by collision, and isolate the adverse effects of moisture.
須說明的是,如果只是利用本發明的新穎結構與製程,對半導體元件或半導體裝置的堆疊結構提供封裝保護,則在製程中配置多數半導體裝置或半導體元件時,若採用單一單元的半導體堆疊裝置進行切割應用時並不須特別注意使相鄰兩半導體裝置或半導體元件的極性方向朝向相反。若有後續應用的極性或線路搭配考量時,則相鄰單元的半導體堆疊裝置必須特別注意使相鄰兩半導體裝置的極性方向,需依要求決定放置。 It should be noted that if only the novel structure and process of the present invention are used to provide packaging protection for the stacked structure of semiconductor elements or semiconductor devices, when multiple semiconductor devices or semiconductor elements are arranged in the process, if a single-unit semiconductor stacked device is used It is not necessary to pay special attention to making the polar directions of two adjacent semiconductor devices or semiconductor elements opposite when performing cutting applications. If there are considerations for polarity or circuit matching for subsequent applications, the semiconductor stack devices of adjacent cells must pay special attention to the polarity directions of the two adjacent semiconductor devices, and the placement must be determined according to requirements.
此外,經封裝完成的半導體元件封裝結構在切割之前,將會包含多數的半導體元件封裝結構單元。這種半導體元件封裝結構適合儲存及運送。在應用之前才需要進行切割,也可先安排切割。 In addition, the packaged semiconductor device package structure will include most semiconductor device package structure units before being cut. This semiconductor device packaging structure is suitable for storage and transportation. Cutting is required before application, or cutting can be arranged first.
2.大量半導體元件的堆疊-目前已知技術的半導體裝置堆疊結構所能堆疊的半導體裝置或半導體元件數量有其極限。習知技術的半導體裝置堆疊結構也不適合互相堆疊,形成大量的堆疊結構。本實施例所提出的半導體元件封裝結構則可以應用在將2個以上的半導體裝置堆疊結構,進行堆疊,達到更大的應用功率。 2. Stacking of a large number of semiconductor elements-The number of semiconductor devices or semiconductor elements that can be stacked in the semiconductor device stack structure of the current known technology has its limit. The conventional semiconductor device stack structure is not suitable for stacking on each other, forming a large number of stack structures. The semiconductor device packaging structure proposed in this embodiment can be applied to stacking more than two semiconductor devices to achieve greater application power.
須說明的是,如果要利用本發明的半導體元件封裝結構進行多數封裝結構的堆疊,則在製程中配置多數半導體裝置或半導體元件時,必須特別注意使相鄰兩半導體裝置或半導體元件的極性方向朝向相反。若為雙極性半導體元件,則無極性方向要求。 It should be noted that if the semiconductor device packaging structure of the present invention is to be used for stacking a large number of packaging structures, when placing a large number of semiconductor devices or semiconductor elements in the manufacturing process, special attention must be paid to the polarity direction of two adjacent semiconductor devices or semiconductor elements. Facing the opposite. If it is a bipolar semiconductor device, there is no requirement for polarity direction.
本實施例的半導體元件封裝結構與圖3所示的結構相同,但圖3中的頂部基板302是由第一頂部區塊801A與第二頂部區塊801B替代。該半導體元件封裝結構的製程也與圖5所示相同,但在步驟507,在該底部基板上形成分隔區304之前、之後或同時,在該頂部底板形成第二分隔區,以將該頂部基板302分隔成第一頂部區塊801A與第二頂部區塊801B。在該步驟503可使兩兩相臨的半導體元件301的極性方向朝向相反,也可不使兩兩相臨的半導體元件301的極性方向朝向相反。該半導體元件封裝方法可包括分割步驟,也可不包括該分割步驟。該半導體元件301可為單一半導體裝置,也可以是包括多數半導體裝置的半導體元件,例如半導體裝置堆疊。
The semiconductor device packaging structure of this embodiment is the same as that shown in FIG. 3, but the
實施例7 Example 7
實施例6所製得的半導體元件封裝結構可以進一步進行堆疊、封裝。圖12即顯示一種實施例6的半導體元件封裝結構的堆疊應用。如圖所示,圖12中的半導體元件封裝結構包括一個頂部基板302和兩個底部基板303A及303B,以及介於其間的多數半導體封裝單元800。該半導體封裝單元800例如為具有圖11所示結構,每個單元包括兩個半導體元件301A與301B的半導體元件封裝結構單元。為顯示清楚起見,圖中將每個半導體封裝單元800僅以虛線表示,而未顯示其詳細結構。該多數半導體封裝單元800的堆疊方式為:所有的半導體封裝單元800的第一底部基板803A都位在同一側,第二底部基板803B也為在同一側。如此使得所有的半導體封裝單元800的第一底部基板803A連成同一極性方向,且所有的半導體封裝單元800的第二底部基板803B也連成同一極性方向。兩極性方向相反。但若為雙極性元件,則無此要求。
The semiconductor device packaging structure prepared in Embodiment 6 can be further stacked and packaged. FIG. 12 shows a stacked application of the semiconductor device packaging structure of the sixth embodiment. As shown in the figure, the semiconductor device packaging structure in FIG. 12 includes a
該半導體元件封裝結構900另外還包括用來將最上方半導體封裝單元800的第一頂部區塊801A及第二頂部區塊801B連接到頂部基板302的導電黏著材料,例如錫膏102A、102C;連接兩相鄰半導體封裝單元800的頂部區塊與底部基板的導電黏著材料,例如錫膏102E,和將最下方半導體封裝單元800兩個底部基板803A、803B連接到底部基板303A、303B的導電黏著材料,例如錫膏102B、102D。該半導體元件封裝結構900的底部基板303A及303B是以分隔區304分隔,填充在基板之間空間的是絕緣層305A~305C,頂部基板302上方並施以防焊層306。底部基板303A及303B背向該半導體元件301A、301B的表面(含兩基板間表面),可視應用的需求而決定是否施以防焊層。所施加的防焊層可施加在基板全表面,但也可施加在部分表面,而露出電極的部分外形。
The semiconductor device packaging structure 900 additionally includes conductive adhesive materials used to connect the first
圖12雖然顯示一種多數半導體封裝單元800的堆疊結構,但本行業人士均知,該封裝結構900也可以只包括單一的半導體封裝單元800。在這種應用中,由於半導體封裝單元800已加工封裝過,再以此製程加工可以獲得更好的水氣隔絕。
Although FIG. 12 shows a stacked structure of a plurality of
以下說明圖12的半導體元件封裝結構的製作方法。圖13顯示本發明半導體元件封裝方法一種較佳實施例的方法流程圖。該方法主要是用來製作如圖9所示的半導體元件封裝結構。 Hereinafter, a method of manufacturing the semiconductor element packaging structure of FIG. 12 will be described. FIG. 13 shows a method flowchart of a preferred embodiment of the semiconductor device packaging method of the present invention. This method is mainly used to manufacture the semiconductor device packaging structure as shown in FIG. 9.
如圖所示,於步驟1001,製備一片頂部基板302。在大量生產的程序中,該頂部基板302是用來支援多數的半導體元件封裝結構單元。在本實施例中,每一個半導體元件封裝結構單元包含以多數半導體封裝單元800堆疊而成的結構。每個半導體封裝單元800都含有兩個半導體元件。每個半導體封裝單元800都可具有例如圖11所示的結構。於步驟1002,將導電黏著材料,例如錫膏102A
及102C施加在該頂部基板302上,用來配置半導體封裝單元800的表面上的預定位置。於步驟1003將多數半導體封裝單元800配置在該頂部基板302上,使每個半導體封裝單元800的第一頂部區塊801A與第二頂部區塊801B分別配置在對應的錫膏102A及102C位置上,以將該多數半導體封裝單元800固定,並電性連接到該頂部基板302。其後,在步驟1004,在各個半導體封裝單元800的第一底部基板803A、第二底部基板803B上施加導電黏著材料,例如錫膏102E,再將相同數量的半導體封裝單元800分別配置到於步驟1003中已經固定到該頂部基板302上的半導體封裝單元800上。成為第二層的多數半導體封裝單元800。重複步驟1004,直到預定層數的半導體封裝單元800已經配置到該頂部基板302上為止。
As shown in the figure, in
接著,在步驟1005製備一片底部基板。該底部基板也是用來支援多數的半導體元件封裝結構單元。在該底部基板的預定位置施加導電黏著材料,例如錫膏102B及102D。該底部基板的預定位置對應於該頂部基板的預定位置。於步驟1006將該底部基板與該頂部基板結合,使底部基板上的個別錫膏102B、102D電性接觸該頂部基板302上,距離該頂部基板302最遠的半導體封裝單元800上的第一底部區塊303A與第二底部區塊303B,並予固定。
Next, in
於步驟1007在該頂部基板302與底部基板之間,以及各個半導體封裝單元800互相間及與兩基板間的空間中,填充絕緣層305A、305B、305C。施作時可藉由毛細現象,或壓力灌膠或抽真空等方式,從基板間、半導體封裝單元間及基板與半導體封裝單元間的空隙進行填膠,以形成絕緣層。該絕緣層305A、305B、305C的材料較佳為環氧樹脂。完成後將該已經形成絕緣層之封裝結構,以烤箱進行烘烤,使該絕緣層固化。於步驟1008,在該底部基板上形成分隔區304,以使每半導體封裝單元800的底部基板形成第一底部基板303A及第
二底部基板303B。所可採用的加工方式包括以化學蝕刻方法形成該分隔區304。之後,於步驟1009,在該頂部基板302背向該半導體封裝單元800的表面施以防焊層306,底部基板303A及303B及底部基板間的防焊層則視應用的需求而決定是否施以防焊層。最後於步驟1010進行切割作業,形成多數單元的半導體元件封裝結構900,每單元包括預訂層數的半導體封裝單元800。
In
102A~102D:錫膏 102A~102D: solder paste
301:半導體元件 301: Semiconductor components
301A:第一半導體元件 301A: The first semiconductor component
301B:第二半導體元件 301B: second semiconductor element
302:頂部基板 302: Top substrate
303A、303B:底部基板 303A, 303B: bottom substrate
304:分隔區 304: partition
305A、305B、305C:絕緣層 305A, 305B, 305C: insulating layer
306:防焊層 306: solder mask
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