CN103489790A - Encapsulation method for chip fan-out encapsulation structure - Google Patents
Encapsulation method for chip fan-out encapsulation structure Download PDFInfo
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- CN103489790A CN103489790A CN201210195439.5A CN201210195439A CN103489790A CN 103489790 A CN103489790 A CN 103489790A CN 201210195439 A CN201210195439 A CN 201210195439A CN 103489790 A CN103489790 A CN 103489790A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
Abstract
The invention relates to an encapsulation method for a chip fan-out encapsulation structure. The encapsulation method includes the following steps that S1, a chip assembly is provided and comprises a chip and a plastic package shell encapsulated on the chip, the chip comprises a first surface, a second surface and an electrode bonding pad, the first surface and the second surface are oppositely arranged, the electrode bonding pad is exposed outwards from the second surface, the plastic package shell at least encapsulates the first surface, and the electrode bonding pad is not encapsulated by the plastic package shell; S3, a substrate ink line is formed and provided with an electrical connecting end connected with the electrode bonding pad; S4, a first thin film dielectric layer is formed, covers the substrate ink line and is provided with a first opening part enabling the substrate ink line to be partially exposed. Ink leading is adopted in the encapsulation method, so chip encapsulation is achieved. Compared with the prior art, the encapsulation method has the advantages of being simple in process, low in manufacturing cost and short in production cycle and protecting the environment, and meanwhile the problem of current leakage can be solved.
Description
Technical field
The present invention relates to the semiconductor packages field, relate in particular to a kind of method for packing of chip fan-out packaging structure.
Background technology
The miniaturization of electronic product, multifunction and update fast and integrated antenna package has been proposed to the requirement of light, thin, short, little, low priceization and flexibility, greatly promoted the development of Advanced Packaging.Therefore for little chip, the many pins of thin space and the encapsulation technology that can adapt to multiple encapsulation situation, be the focus of current encapsulation field and the trend of future development.The chip fan-out packaging structure is exactly that the thin space pin on little chip is amplified and arranges by rewiring, and this encapsulating structure can dwindle chip size greatly.And because the chip that can realize different designs by connecting up again shares same substrate and lead frame, so the package area increase can be arranged more pin.And Embedded chip package makes the side of chip, front and back all be subject to protection.Meanwhile, some passive devices also can form the packaging bodies such as a large ball grid array, grid array together with this encapsulating structure compact package with chip.Thereby reduced packaging cost, improved package reliability and realize encapsulation situation flexibility.
Current typical chip fan-out-type encapsulating structure technique is, adopts coating photoetching development method to prepare the thin film dielectrics layer, electroplates, chemistry crosses or the sputter mode realizes connecting up conducting wire again, with the injection sealed material, whole chip encapsulated.
But there are the following problems for said chip fan-out-type encapsulating structure technique:
1, complex process, the cycle is long
The thin film dielectrics layer need to pass through the wet techniques such as coating, photoetching and development, and conducting wire needs the wet techniques such as plating, sputter and corrosion.These complex process, flow process is more, and needs corresponding supporting tool, so the preparatory period is longer.
2, waste material, high pollution
Development and etch process need to be removed unnecessary thin film dielectrics layer and electric conducting material, cause the lot of materials waste; Development, plating or chemistry cross, used a large amount of chemical reagent in etching process, cause environmental pollution.
3, leakage problem
The more difficult corrosion of metal on the thin film dielectrics layer, easily cause metal residual and have leakage problem.
In view of this, be necessary the method for packing of existing fan-out chip packaging structure is improved to address the above problem.
Summary of the invention
The object of the present invention is to provide a kind of method for packing of chip fan-out packaging structure, its technique is simple, low cost of manufacture, with short production cycle and environmental protection and can solve leaky.
For realizing aforementioned purpose, the present invention adopts following technical scheme: a kind of method for packing of chip fan-out packaging structure comprises the steps:
S1: chip assembly is provided, described chip assembly comprises chip and is encapsulated in the plastic packaging housing on chip, the electrode pad that described chip has the first surface that is oppositely arranged and second surface and outwards exposes from described second surface, described plastic packaging housing is at least sealed residence and is stated first surface, and described electrode pad is not by described plastic packaging shell encapsulated;
S3: form basic unit's printing ink cabling, described basic unit printing ink cabling is formed with the electricity connection end be connected with electrode pad; And
S4: form the first film dielectric layer, cover on described basic unit printing ink cabling, described the first film dielectric layer has makes barish the first peristome of described basic unit printing ink cabling.
As a further improvement on the present invention, after described S4 step, also comprise the steps:
S5: form by electrically conductive ink being pasted on described the first film dielectric layer the printing ink cabling that is positioned at basic unit's printing ink cabling upper strata, the printing ink cabling on this upper strata is connected by the printing ink cabling of described the first peristome and the lower floor be adjacent; And
S6: cover and form another the first film dielectric layer at the described printing ink cabling that is positioned at upper strata, this another the first film dielectric layer also is formed with the first peristome that the printing ink cabling that will form in the S5 step partly exposes.
As a further improvement on the present invention, described printing ink cabling is: metal or alloy printing ink or conduct electricity inorganic matter or organic printing ink that conducts electricity.
As a further improvement on the present invention, between described S1 step and S3 step, also comprise S2: form the second thin film dielectrics layer, described the second thin film dielectrics layer covers the second surface of chip or covers the chip second surface and extend to the plastic packaging housing, and described the second thin film dielectrics layer has the second peristome that electrode pad is exposed.
As a further improvement on the present invention, described printing ink cabling, the first film dielectric layer and the second thin film dielectrics layer are all by ink-jet or printing moulding.
As a further improvement on the present invention, described the first film dielectric layer and the second thin film dielectrics layer are: polyimides or phenylpropyl alcohol cyclobutane or epoxy resin.
As a further improvement on the present invention, described printing ink cabling thickness several microns between the hundreds of micron, width at several microns between the hundreds of micron.
The method for packing of the chip assembly provided in described S1 step as a further improvement on the present invention, comprises the steps:
S11 a: support plate is provided;
S12: on described support plate, form peelable film;
S13: chip is provided, described chip has first surface and the second surface be oppositely arranged and is arranged on the electrode pad on described second surface, by described flip-chip, on described peelable film, described second surface and described peelable film recline;
S14: form the plastic packaging housing, at described chip periphery injection mo(u)lding plastic packaging housing, to form described chip assembly, described electrode pad is not by described plastic packaging shell encapsulated; And
S15: peelable film and support plate are peeled off from chip assembly by peelable film.
The present invention is by adopting the printing ink lead-in wire to realize chip package, compared with prior art, has advantages of that technique is simple, low cost of manufacture, with short production cycle and environmental protection, also can solve leakage problem simultaneously.
The accompanying drawing explanation
The cutaway view that Fig. 1 is the chip fan-out packaging structure in one embodiment of the invention.
The structural representation that Fig. 2 is Fig. 1 chips fan-out packaging structure chips.
The vertical view that Fig. 3 is Fig. 1 chips fan-out packaging structure.
The method for packing flow chart that Fig. 4 is Fig. 1 chips fan-out packaging structure chips assembly.
The flow chart of the method for packing that Fig. 5 is Fig. 1 chips fan-out packaging structure.
The enforcement structure chart that the method for packing flow chart that Fig. 6 to Figure 13 is Fig. 3 chips fan-out packaging structure is corresponding.
Embodiment
Refer to Fig. 1 to 3, the chip fan-out packaging structure in one embodiment of the invention comprises chip 2, be encapsulated in plastic packaging housing 1 on chip 2, be arranged on the second insulating medium layer 3 on chip 2 and plastic packaging housing 1, be arranged on the some printing ink cablings 4 on the second insulating medium layer 3 and be arranged on the first insulating medium layer 5 on printing ink cabling 4.Below the correlation between each part mentioned above and each several part is described in detail.
The second thin film dielectrics layer 3 is arranged on the second surface 22 of chip 2 and extends to the end face (indicating) that is positioned at the plastic packaging housing 1 on same level with chip 2 second surfaces 22.The second thin film dielectrics layer 3 has the second peristome 31 that electrode pad 24 is exposed.The thickness of the second thin film dielectrics layer 3 is at several microns to tens microns.At this, the second thin film dielectrics layer 3 is formed by polyimides or phenylpropyl alcohol cyclobutane or epoxy resin.This second thin film dielectrics layer 3 is formed on chip 2 and plastic packaging housing 1 by methods such as ink-jet or printings.Except the second thin film dielectrics layer 3 being arranged on to chip 2 and plastic packaging housing 1 is upper outside, the second thin film dielectrics layer 3 also can only be arranged on (not shown) on chip 2.
The first film dielectric layer 5 covers on above-mentioned printing ink cabling 4, and has barish the first peristome 51 of the printing ink of making cabling 4.The thickness of the first film dielectric layer 5 is between several microns to tens microns.Identical with the second thin film dielectrics layer 3, the first film dielectric layer 5 is formed by polyimides or phenylpropyl alcohol cyclobutane or epoxy resin.The first film dielectric layer 5 is formed on printing ink cabling 4 by methods such as ink-jet or printings.
The present embodiment provides individual layer printing ink cabling, forms the structure of one deck printing ink cabling 4 and the first film dielectric layer 5 corresponding with this layer of printing ink cabling 4 on chip 2 that is:.Except this structure, also can adopt the multilayer setting, form multilayer printing ink cabling and with the first film dielectric layer of every layer of corresponding setting of printing ink cabling, every layer of printing ink cabling and to cover the forming method of every layer of the first film dielectric layer on the printing ink cabling all identical.At this, for the ease of statement, will be connected directly to the printing ink cabling 4 of electrode pad 24 as basic unit's printing ink cabling (being the printing ink cabling shown in Fig. 1).And the printing ink cabling on every layer all has the identical electricity connection end of same basic unit's printing ink cabling, be positioned at every layer of the first film dielectric layer on the printing ink cabling also have be located on basic unit's printing ink cabling on the first film dielectric layer identical will be positioned at the first peristome that its adjacent lower floor's printing ink cabling partly exposes.
The concrete structure of above-mentioned multilayer setting is: basic unit's printing ink cabling is molded on the second thin film dielectrics layer by modes such as ink-jet or printings, remainder layer printing ink cabling is on the printing ink cabling of the lower floor that it is adjacent by mode moulding such as ink-jet or printings, basic unit's printing ink cabling is connected directly to the electrode pad of substrate, first peristome of the electricity connection end of remainder layer printing ink cabling by the first film dielectric layer of the lower floor that is adjacent be connected with the printing ink cabling of lower floor (not shown).At this, it should be noted that: because basic unit's printing ink cabling is connected with electrode pad, and the printing ink cabling of every layer (comprising basic unit's printing ink cabling) is connected, so the printing ink cabling of every layer all is electrically connected with electrode pad.In addition, because above-mentioned having mentioned can not arrange the first film dielectric layer, so the basic unit printing ink cabling of multilayer in the case in arranging is molded directly within on chip and plastic packaging housing by modes such as ink-jet or printings.
Below please in conjunction with the structure chart of seeing the process chart shown in Fig. 4 to Figure 13 and concrete forming step, the method for packing to the chip fan-out packaging structure in above-described embodiment is described in detail.Please be simultaneously in conjunction with Fig. 2.
Please, in conjunction with Fig. 6, provide a support plate 101(S11 step).This support plate 101 can be any one in metal, glass, silicon crystal unit, epoxy resin base plate.
Please, in conjunction with Fig. 7, form peelable film 102 (S12 step) on support plate 101.
Please in conjunction with Fig. 8, chip 2 is provided, chip 2 have the first surface 21 that is oppositely arranged with second surface 22, be connected the 3rd surface 23 of first surface 21 and second surface 22 and be arranged on the electrode pad 24 on second surface 22, by chip 2 upside-down mountings on peelable film 102, second surface 22 and peelable film 102 recline (S13 step).This chip 2 also can be replaced by the combination of chip and passive device.
Please, in conjunction with Fig. 9, form plastic packaging housing 1, at the peripheral injection mo(u)lding plastic packaging of chip 2 housing 1, to form chip assembly 103, described electrode pad 24 is not sealed (S14 step) by plastic packaging housing 1.Plastic packaging housing 1 is epoxy resin.
Please, in conjunction with Figure 10, peelable film 102 and support plate 101 are peeled off to (S15 step) by peelable film 102 from chip assembly 103.The mode of peeling off above-mentioned peelable film 102 and support plate 101 on chip assembly 103 adopts the mode of ultraviolet ray irradiation or high-temperature heating.
Chip assembly 103(S1 step is provided), this chip assembly 103 is to the prepared chip assembly 103 of S15 step by above-mentioned S11 step.And known from the above-mentioned method for packing for preparing chip assembly 103: this chip assembly 103 comprises chip 2 and is encapsulated in the plastic packaging housing 1 on chip 2, chip 2 have the first surface 21 that is oppositely arranged with second surface 22, be connected the 3rd surface 23 of first surface 21 and second surface 22 and be arranged on the electrode pad 24 on second surface 22, plastic packaging housing 1 is sealed first surface 21 and the 3rd surface 23 of this chip 2, and electrode pad 24 is not sealed by this plastic packaging housing 1.
Please, in conjunction with Figure 11, form the second thin film dielectrics layer 3(S2 step), it covers on the second surface 22 of chip 2 and extends to the end face that is positioned at the plastic packaging housing 1 of same level with second surface 22.The second thin film dielectrics layer 3 has the second peristome 31 that electrode pad 24 is exposed.These the second thin film dielectrics layer 3 thickness are between several microns to tens microns.First by methods such as ink-jet or printings, form, then by toasting (temperature: 100-400 degree centigrade) or the technology such as UV-irradiation established the first film dielectric layer 3 is done to the acceleration forming processes.The second thin film dielectrics layer 3 can be polyimides or phenylpropyl alcohol cyclobutane or epoxy resin.In this step, this second thin film dielectrics layer 3 also can only be formed on chip 2.
Please, in conjunction with Figure 12, form printing ink cabling 4(S3 step).By electrically conductive ink being pasted on the first film dielectric layer 3 to form printing ink cabling 4, this printing ink cabling 4 is formed with the electricity connection end 41 be connected with electrode pad 24.The thickness of printing ink cabling 4 several microns between the hundreds of micron, width at several microns between the hundreds of micron.Described printing ink cabling is by forming by methods such as ink-jet or printings on the respective regions of the first film dielectric layer 3, and then by toasting (temperature: 50-500 degree centigrade) or the method such as UV-irradiation established printing ink cabling 4 is done to the acceleration forming processes.Printing ink cabling 4 is metal or alloy printing ink or conduction inorganic matter or conductive organic matter printing ink.In this step, because the electricity connection end 41 of this printing ink cabling 4 is connected with electrode pad 24, therefore this printing ink cabling 4 can be used as basic unit's printing ink cabling.In addition, as another embodiment of the present invention, also can omit the S2 step, thus, this step (S3 step) is and directly forms this printing ink cabling 4 by electrically conductive ink on chip assembly 103.
Please, in conjunction with Figure 13, form the first film dielectric layer 5(S4 step).Cover on above-mentioned basic unit printing ink cabling, the first film dielectric layer 5 has makes barish the first peristome 51 of above-mentioned basic unit printing ink cabling.5 layers, the first film medium forms by methods such as ink-jet or printings, then by toasting (temperature: 100-400 degree centigrade) or the method such as UV-irradiation established the first film dielectric layer 5 is done to the acceleration forming processes.The first film dielectric layer 5 can be polyimides or phenylpropyl alcohol cyclobutane or epoxy resin.
Only there is one deck printing ink cabling by above-mentioned S11 step to the prepared chip fan-out packaging structure of S4, but in addition, it can be also the multilayer setting.If needs formation multilayer, be repeated below the S5 step and the S6 step can realize.At this, it should be noted that: the forming method that the printing ink cabling of every layer is used with the first insulating medium layer on every layer of printing ink cabling and material and basic unit's printing ink cabling are identical with the first film dielectric layer be formed on basic unit's printing ink cabling, simultaneously, printing ink cabling on every layer all has the identical electricity connection end of same basic unit's printing ink cabling, be positioned at every layer of the first film dielectric layer on the printing ink cabling also have be located on basic unit's printing ink cabling on the first film dielectric layer identical will be positioned at the first peristome that its adjacent lower floor's printing ink cabling partly exposes.It is below the embodiment of S5 step and S6 step.
S5: form by electrically conductive ink being pasted on described the first film dielectric layer the printing ink cabling that is positioned at basic unit's printing ink cabling upper strata, the printing ink cabling on this upper strata is connected by the printing ink cabling of the first peristome and the lower floor be adjacent.
S6: form another the first film dielectric layer on the printing ink cabling that is positioned at upper strata covers, this another the first film dielectric layer also is formed with and will forms barish the first peristome of printing ink cabling in the S5 step.
The present embodiment chips fan-out packaging structure is by adopting printing ink lead-in wire 4 to realize chip package, many expensive technical processs such as photoetching, plating and corrosion have been avoided, technology difficulty and manufacturing cost have been reduced, shortened the production cycle, reduce the pollution to environment, solved leakage problem simultaneously.
Although be the example purpose, the preferred embodiment of the present invention is disclosed, but those of ordinary skill in the art will recognize, in the situation that do not break away from by the disclosed scope and spirit of the present invention of appending claims, various improvement, increase and replacement are possible.
Claims (8)
1. the method for packing of a chip fan-out packaging structure, it is characterized in that: described method for packing comprises the steps:
S1: chip assembly is provided, described chip assembly comprises chip and is encapsulated in the plastic packaging housing on chip, the electrode pad that described chip has the first surface that is oppositely arranged and second surface and outwards exposes from described second surface, described plastic packaging housing is at least sealed residence and is stated first surface, and described electrode pad is not by described plastic packaging shell encapsulated;
S3: form basic unit's printing ink cabling, described basic unit printing ink cabling is formed with the electricity connection end be connected with electrode pad; And
S4: form the first film dielectric layer, cover on described basic unit printing ink cabling, described the first film dielectric layer has makes barish the first peristome of described basic unit printing ink cabling.
2. the method for packing of chip fan-out packaging structure according to claim 1, is characterized in that: after described S4 step, also comprise the steps:
S5: form by electrically conductive ink being pasted on described the first film dielectric layer the printing ink cabling that is positioned at basic unit's printing ink cabling upper strata, the printing ink cabling on this upper strata is connected by the printing ink cabling of described the first peristome and the lower floor be adjacent; And
S6: cover and form another the first film dielectric layer at the described printing ink cabling that is positioned at upper strata, this another the first film dielectric layer also is formed with the first peristome that the printing ink cabling that will form in the S5 step partly exposes.
3. the method for packing of chip fan-out packaging structure according to claim 1 and 2, it is characterized in that: described printing ink cabling is: metal or alloy printing ink or conduct electricity inorganic matter or organic printing ink that conducts electricity.
4. the method for packing of chip fan-out packaging structure according to claim 1 and 2, it is characterized in that: between described S1 step and S3 step, also comprise S2: form the second thin film dielectrics layer, described the second thin film dielectrics layer covers the second surface of chip or covers the chip second surface and extend to the plastic packaging housing, and described the second thin film dielectrics layer has the second peristome that electrode pad is exposed.
5. the method for packing of chip fan-out packaging structure according to claim 4 is characterized in that: described printing ink cabling, the first film dielectric layer and the second thin film dielectrics layer are all by ink-jet or printing moulding.
6. the method for packing of chip fan-out packaging structure according to claim 4, it is characterized in that: described the first film dielectric layer and the second thin film dielectrics layer are: polyimides or phenylpropyl alcohol cyclobutane or epoxy resin.
7. the method for packing of chip fan-out packaging structure according to claim 1 and 2 is characterized in that: described printing ink cabling thickness several microns between the hundreds of micron, width at several microns between the hundreds of micron.
8. the method for packing of chip fan-out packaging structure according to claim 1, it is characterized in that: the method for packing of the chip assembly provided in described S1 step comprises the steps:
S11 a: support plate is provided;
S12: on described support plate, form peelable film;
S13: chip is provided, described chip has first surface and the second surface be oppositely arranged and is arranged on the electrode pad on described second surface, by described flip-chip, on described peelable film, described second surface and described peelable film recline;
S14: form the plastic packaging housing, at described chip periphery injection mo(u)lding plastic packaging housing, to form described chip assembly, described electrode pad is not by described plastic packaging shell encapsulated; And
S15: peelable film and support plate are peeled off from chip assembly by peelable film.
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| CN113725097A (en) * | 2020-03-27 | 2021-11-30 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
| CN111341672A (en) * | 2020-05-15 | 2020-06-26 | 深圳市汇顶科技股份有限公司 | Semiconductor packaging method and packaging structure thereof |
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