CN208767298U - Sensor encapsulation - Google Patents
Sensor encapsulation Download PDFInfo
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- CN208767298U CN208767298U CN201790000502.1U CN201790000502U CN208767298U CN 208767298 U CN208767298 U CN 208767298U CN 201790000502 U CN201790000502 U CN 201790000502U CN 208767298 U CN208767298 U CN 208767298U
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- feed throughs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/82005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
Abstract
The utility model discloses a kind of encapsulation of sensor and its manufacturing method.The sensor package of an embodiment according to the present utility model includes: semiconductor chip, comprising being exposed to external sensor patterns；Substrate, the receiving portion comprising accommodating the semiconductor chip；Encapsulating material, by make the semiconductor chip and the substrate it is integrated in a manner of plastic packaging；Feed throughs run through the substrate in above-below direction；Wiring portion is electrically connected the semiconductor chip and the feed throughs, and makes the sensor patterns exposure of the semiconductor chip；And external connecting, it is electrically connected with the other side of the feed throughs, and can be with external electrical connections.
Description
Technical field
The present invention relates to a kind of encapsulation of sensor and its manufacturing methods, more specifically, are related to reducing sensor encapsulation
Thickness improves the sensitivity of sensor, the sensor of the conductive channel including the upper and lower part electrical connection for encapsulating sensor
Encapsulation.
Background technique
With the continuous development of semiconductor chip fabrication process, the size of semiconductor chip also constantly reduces.Currently, partly leading
The size of body chip is substantially reduced, so that occurring to need to increase package dimension to be electrically connected when forming semiconductor packages
The case where.In this development process, the semiconductor packaging that is proposed first is that fan-out package (Fan-out
Package)。
Also, the patterning of upper and lower vertical transfer signal is formed along with the lateral area in fan-out package, and on
The encapsulation or different types of encapsulation of lower stacking same type, thus extension storage capacity or raising half in same package area
The technology of the operating characteristics of conductor is researching and developing various types of semiconductor packagings.
In the case where existing fan-out package, there is following encapsulating structure, that is, semiconductor chip is pasted by adhesive
It is attached on PCB substrate or lead frame, and the metal framework in the PCB substrate or the side of lead frame passes through wire bonding
It is electrically connected with semiconductor chip, and the semiconductor chip and conducting wire is protected by plastic packaging.
Exposure is needed to be arranged in the sensor envelope of the semiconductor chip of the top of semiconductor packages in semiconductor packages
In the case where dress, the existing fan-out package being electrically connected by wire bonding due to having sensitivity deterioration and most separated by a distance
The shortcomings that thickness encapsulated eventually thickens, also, exist with the loop-length of conducting wire it is elongated, electric property reduce the shortcomings that.
Korean Patent Laid 10-2015-0090705 (publication date: on August 6th, 2015) is disclosed in encapsulating sheet
The sensor encapsulation and preparation method thereof of exposure sensing unit on face.
(existing technical literature)
(patent document)
Korean Patent Laid 10-2015-0090705 (publication date: on August 6th, 2015)
Summary of the invention
Technical problem
The embodiment of the present invention offer may be produced that sensor encapsulation that is slim, and having the transducer sensitivity improved.
Also, the embodiment of the present invention, which is provided, is not inserted into individual gold between the feed throughs and wiring layer through substrate
The manufacturing method of sensor encapsulation of wiring layer can be also laminated by belonging to pad etc..
Solution to problem
The sensor package of an embodiment according to the present invention includes: semiconductor chip, comprising being exposed to external sensing
Device pattern；Substrate, the receiving portion comprising accommodating the semiconductor chip；Encapsulating material, so that the semiconductor chip and described
The integrated mode plastic packaging of substrate；Feed throughs run through the substrate in above-below direction；Wiring portion makes the semiconductor chip
It is electrically connected with the feed throughs, and makes the sensor patterns exposure of the semiconductor chip；And external connecting, with institute
The other side electrical connection of feed throughs is stated, and can be with external electrical connections.
Also, an embodiment according to the present invention, the semiconductor chip, the substrate and the encapsulating material can be set
It sets in the same plane, the wiring portion can be layered on the semiconductor chip, the substrate and the encapsulating material.
Also, an embodiment according to the present invention, the wiring portion may include: the first insulating layer, make the semiconductor
The signal pad of chip and feed throughs exposure；Wiring layer, setting on the first insulating layer, and make the signal pad and
The feed throughs electrical connection；And second insulating layer, it is arranged on first insulating layer and the wiring layer, described in covering
Wiring layer, and make the sensor patterns exposure of the semiconductor chip.
Also, an embodiment according to the present invention, first insulating layer may include opening portion, and the opening portion makes institute
State signal pad and the feed throughs expose respectively, the wiring layer can by fill the opening portion of first insulating layer come
It is connected to the signal pad and the feed throughs.
Also, an embodiment according to the present invention, the substrate could be formed with perforative through-hole in above-below direction, described
Feed throughs can be formed by the conductive material for filling in the through hole.
Also, an embodiment according to the present invention, the feed throughs can be formed by conducting resinl.
Also, an embodiment according to the present invention, the sensor, which encapsulates, may also include welding disk, and the one of the welding disk
Face is attached to the feed throughs, and another side is attached to the external connecting, and the welding disk is formed by conductive material.
Also, an embodiment according to the present invention, the end for adhering to the feed throughs of the welding disk can be from the base
Plate is prominent and extends to outside.
Also, an embodiment according to the present invention, metal layer can be between the ends of the substrate and the feed throughs
Between.
Also, an embodiment according to the present invention, the substrate could be formed with perforative through-hole in above-below direction, described
Feed throughs can surround the inner peripheral surface of the through-hole, and through-Penetration portion can be filled with by being formed in the through-hole of the feed throughs
Part.
Also, an embodiment according to the present invention, it is described to be formed by nonconductive resin through component.
The manufacturing method of the sensor encapsulation of an embodiment according to the present invention includes: base the step of providing substrate
Plate is formed with the receiving portion for accommodating semiconductor chip and the outside through-hole perforative along the vertical direction in described accommodation section；Described in
The up and down direction of through-hole forms the step of feed throughs；Partly leading comprising signal pad and sensor patterns is accommodated in described accommodation section
The step of body chip；So that the institute of the feed throughs, the semiconductor chip on the semiconductor chip and the substrate
State the step of insulating layer is laminated in the mode that signal pad and the sensor patterns expose；And so that the letter on the insulating layer
Mode the step of forming wiring layer of number pad and feed throughs electrical connection.
Also, deposition or electricity can be used as the method for forming the feed throughs in an embodiment according to the present invention
Depositing process surrounds the inner peripheral surface of the through-hole.
Also, an embodiment according to the present invention, the feed throughs can be by depositing or being electroplated in the substrate
It is formed on two sides, the feed throughs that the two sides of the substrate is arranged in can be connected by the inner peripheral surface of the through-hole.
Also, an embodiment according to the present invention, the through-hole can be filled by the feed throughs.
Also, an embodiment according to the present invention, be arranged on the feed throughs of the one side of the substrate can be laminated by
The welding disk that conductive material is formed.
Also, an embodiment according to the present invention can be filled in the hollow portion of the feed throughs through component, setting
The one side of the substrate feed throughs and described the welding disk formed by conductive material can be laminated on the component.
Also, an embodiment according to the present invention, the manufacturing method of the sensor encapsulation, which may also include, adheres to dry film
To the one side that the substrate is set the welding disk and patterned, and except eliminate adhere to the dry film part it
The welding disk of outer rest part and the etch process of the feed throughs.
Also, an embodiment according to the present invention, the manufacturing method of sensor encapsulation may also include by with pass through institute
State patterning and the welding disk existing for the technique that is planarized of the opposite face in face.
Also, an embodiment according to the present invention, the substrate and the feed throughs can pass through the flat chemical industry
Skill is disposed on the same plane.
The effect of invention
The sensor of embodiment according to the present invention, which encapsulates its manufacturing method, can make setting in semiconductor chip and wiring
Insulating layer between layer it is thinner, slim encapsulation can be manufactured, and make the active surface of semiconductor chip and entire
The minimizing thickness between layer is assembled, so as to improve induction sensitivity.
Detailed description of the invention
Fig. 1 is the sectional view encapsulated according to the sensor of one embodiment of the invention.
Fig. 2 is the plan view that the sensor encapsulation of Fig. 1 is intercepted along A-A' line.
Fig. 3 to Figure 16 is the sectional view for showing the manufacturing process of sensor encapsulation of an embodiment according to the present invention.
Figure 17 is the sectional view encapsulated according to the sensor of one embodiment of the invention.
Figure 18 is the sectional view that the packaging body lamination (Package-on-Package) of sensor encapsulation of Fig. 1 is laminated.
Symbol description
| 100: sensor encapsulation | 110: semiconductor chip |
| 111: active surface | 112: inactive surface |
| 113: signal pad | 114: sensor patterns |
| 120: substrate | 121: receiving portion |
| 122: through-hole | 123: feed throughs |
| 124: running through component | 125: welding disk |
| 130: wiring portion | 131: the first insulating layers |
| 132: wiring layer | 133: second insulating layer |
| 140: encapsulating material | 150: external connecting |
| 160: first vector | 161: the first bonding parts |
| 170: Second support | 171: the second bonding parts |
Specific embodiment
Hereinafter, the embodiment of the present invention is described in detail referring to attached drawing.Multiple embodiments of the invention are in order to more
Add site preparation to general technical staff of the technical field of the invention illustrate the present invention and provide, embodiment below can
A variety of different forms are deformed into, the scope of the invention is not limited to embodiment below, the present invention can also be with other shapes
Formula embodies.In order to illustrate more clearly of the present invention, the part unrelated with explanation of the invention is omitted in attached drawing, for the ease of
Understand, amplitude, length, the thickness etc. for indicating construction package can be amplified.In the description, identical appended drawing reference indicates same
Component part.In the accompanying drawings, identical appended drawing reference censures identical element.Use such as in the present specification, term " and/
Or " it include one of corresponding project enumerated and more than one all combinations.
Fig. 1 is the sectional view encapsulated according to the sensor of one embodiment of the invention.Fig. 2 is to intercept Fig. 1's along A-A' line
The plan view of sensor encapsulation.The sensor encapsulation 100 of embodiment according to the present invention is illustrated referring to Figures 1 and 2.
The sensor encapsulation 100 of an embodiment according to the present invention includes: semiconductor chip 110, comprising being exposed to outside
Sensor patterns 114；Substrate 120, the receiving portion 121 comprising accommodating the semiconductor chip 110；Encapsulating material 140, with
Make the semiconductor chip 110 and the integrated mode plastic packaging of the substrate 120；Feed throughs 123 run through institute in above-below direction
State substrate 120；Wiring portion 130 is electrically connected the semiconductor chip 110 and the feed throughs 123, and makes the semiconductor
The exposure of the sensor patterns 114 of chip 110；And external connecting 150, it is electrically connected with the other side of the feed throughs 123
It connects, and can be with external electrical connections.
For example, the substrate 120 can be set to insulating substrate.Insulating substrate may include insulating materials, for example, can
To include silicon, glass, ceramics, plastics or polymer.The substrate 120 can be in writing board shape, can also be in such as round or more
The various shapes such as side shape.
The substrate 120 may include the receiving portion 121 for accommodating the semiconductor chip 110.Described accommodation section 121 can be with
Through the substrate 120, and the central part of substrate 120 can be located at.The width of described accommodation section 121 can be greater than described half
The width of conductor chip 110 enables described accommodation section 121 to accommodate the semiconductor chip 110.
At this point, following encapsulating materials 140 can be filled between the semiconductor chip 110 and described accommodation section 121.
In contrast, described accommodation section 121 can differently be configured to the nonopen groove of one side of the substrate 120 with diagram.And
And described accommodation section 121 can be in shape identical with the width direction shape of semiconductor chip 110, so that semiconductor chip
110 are press-fitted in described accommodation section 121.
The semiconductor chip 110, which can be, to sense outside by being exposed to the external sensor patterns 111
Various types of sensor chips of stimulation.For example, the semiconductor chip 110 can be image sensor chip, for referring to
Sensor chip, the sensor chip for thermal sensing or the sensor chip for humidity etc. of line identification.More preferably
Ground, the semiconductor chip 110 can be the sensor chip for fingerprint recognition, the sheet including above-mentioned semiconductor chip 110
The sensor encapsulation 100 of invention can be used in sensor device, in particular, can be used in fingerprint sensor.
The active surface 111 that can be the active region including forming circuit on one side of the semiconductor chip 110.It is another
The back side of aspect, the semiconductor chip 110 can be inactive surface 112.
The work in the semiconductor chip 110 can be set in multiple signal pads 113 for exchanging signal with outside
On property surface 111, the signal pad 113 can be formed by conductive material membranes such as such as aluminium.The signal pad 113 can be with described half
Conductor chip 110 is integrally formed.
Although fig 1 illustrate that a semiconductor chip 110, but in contrast, it can have two or more semiconductors
The form that chip is stacked.At this point, the semiconductor chip of stacking may be different types of product.For example, a semiconductor core
Piece can be sensor chip, another semiconductor chip can be memory chip or logic chip.Two or more are laminated
The encapsulation of sensor made of a semiconductor chip can be system on chip (SOC) or system in package (SIP).Also, multiple half
Conductor chip can be adjacent to each other in the direction of the width or be contiguously arranged.
In order to be mounted in main substrate (not shown) or be electrically connected to another chip or envelope for sensor encapsulation 100
Dress, needs the electrical connection section for being electrically connected semiconductor chip 110 and main substrate etc..On the other hand, in order to sensor is encapsulated
100 are mounted in the main substrate join domain in the region of the wider interval of the signal pad 113 than semiconductor chip 110, Ke Yishe
Circuits extend to the fan-out package form of the periphery of semiconductor chip 110.
Although it is not shown in the diagrams, main substrate includes the printed circuit board or lead frame for including printed circuit.In addition, printing
Circuit board includes film, glass or adhesive tape etc..
In order to form fan-out package form, the sensor encapsulation 100 of embodiment according to the present invention may include running through
Wiring 123, the feed throughs 123 can be set in the outside of the signal pad 113 of semiconductor chip 110, and can be upper and lower
Transmission telecommunications number on direction.The side of feed throughs 123 may be electrically connected to semiconductor chip 110, and the other side can be electrically connected
To external connection part 150, external connection part 150 may be electrically connected to main substrate or another chip or encapsulation.
The feed throughs 123 can arrange along the vertical direction by the through-hole 122 being formed in the substrate 120, with
Data-signal or electric power signal are transmitted between the semiconductor chip 110 and main substrate etc..The through-hole 122 can be formed as
Through the substrate 120, and multiple through-holes 122 can be along the periphery of the described accommodation section 121 of the substrate 120
Setting.Referring to Fig. 2, it is seen that the feed throughs 123 are in a row along the periphery setting of described accommodation section 121.Alternatively, can also be with
The feed throughs 123 of two column or more are set, feed throughs 123 only can also be set in the side of described accommodation section 121.
An embodiment according to the present invention, the feed throughs 123 can be the conduction material being filled in the through-hole 122
Material.The feed throughs 123 can be formed as cylindrical.
On the other hand, the feed throughs 123 can be setting and break-through through-hole 122 in the form of soldered ball etc., or can be
The solder mask being filled in through-hole 122.
The forming method of the feed throughs 123 includes electroless plating, electrolysis plating, sputtering or printing etc..
The side (upside in Fig. 1) of the feed throughs 123 can be set on 120 same plane of substrate,
And the other side (downside in Fig. 1) can be set to prominent from the substrate 120.
The flange shape extended outward can be set into from 120 other side outstanding (or downside) of substrate, also,
Between the flange part that metal layer 120a can extend between the substrate 120 and outward.One as the metal layer 120a
A example may include copper foil.
The side of feed throughs 123 may be electrically connected to the wiring layer 132 of wiring portion 130, and the other side can be electrically connected
It is connected to external connecting 150.On the other hand, welding disk 125 can be between feed throughs 123 and external connecting 150.
Welding disk 125 can be made of an electrically conducting material to be electrically connected feed throughs 123 and external connecting 150, and make external connection
Portion 150 is securely adhered to feed throughs 123.The method for forming welding disk 125 includes electroless plating, electrolysis plating, sputtering
Or printing etc..
Wiring portion 130 can be set such that the signal pad 113 of semiconductor chip 110 and the side of feed throughs 123
Electrical connection.
For example, wiring portion 130 may include the first insulating layer 131, second insulating layer 133 and wiring layer 132.First absolutely
Edge layer 131 and second insulating layer 133 are made of insulating material so that wiring layer 132 insulate.
First insulating layer 131 can be stacked on the active surface 111, encapsulating material 140 and substrate of semiconductor chip 110
In 120 one side.Also, the first insulating layer 131 can be by making the signal pad 113 and feed throughs 123 of semiconductor chip 110
Exposure comes so that the wiring layer 132 being stacked on the first insulating layer 131 is connected to signal pad 113 and feed throughs 123.Another party
Face, when encapsulating material 140 is arranged to cover the one side of semiconductor chip 110 and/or substrate 120, the first insulating layer 131 can
Not to be laminated on the semiconductor chip 110 and/or on substrate 120.
Wiring layer 132 includes conductive material, and can be stacked on the first insulating layer 131 by resetting technique.Wiring
Layer 132 can be such that the input/output terminal of semiconductor chip 110 miniaturize by forming rewiring pattern, and increase defeated
Enter/the quantity of output terminal, and fan-out-type structure may be implemented.Conductive material may include metal, for example, may include copper,
Copper alloy, aluminum or aluminum alloy.
On the other hand, wiring layer 132 can be previously fabricated structural body, and can pass through crimping, bonding or reflux
Semiconductor chip 110, encapsulating material 140 and substrate 120 are adhered to Deng by above described structure.
Second insulating layer 133 is layered on the first insulating layer 131 and wiring layer 132, so that wiring layer 132 and outside are exhausted
Edge.Although showing second insulating layer 133 in figure seals wiring layer 132, in contrast, second insulating layer 133 can be set
Be set to a part exposure so that wiring layer 132, and by the wiring layer 132 of exposure and it is external (main substrate, semiconductor chip or
Encapsulation etc.) electrical connection.
In the sensor encapsulation 100 of embodiment according to the present invention, one end of feed throughs 123 can not be protruded in base
On plate 120.Also, feed throughs 123 and wiring layer 132 can be directly connected to be electrically connected.At this point, " connection " refers not only to object
Reason contact also refers to and clips conductive adhesive layer (for example, seed layer) bonding therebetween.
In general, the sensitivity for improving sensor is important in the case where sensor device.In particular, can be by making
The sensitivity of sensor is improved to the minimizing thickness of entire assembly layer from the active surface 111 of semiconductor chip 110.
In the encapsulation of existing sensor, the metal framework of semiconductor chip and side is connected using conducting wire by wire bonding
Connect, therefore, sensor encapsulation thickness due to thickeing for protecting the plastic packaging of conducting wire, sensor encapsulation upper side with partly lead
The problem of the distance between the sensor patterns of body chip are elongated, lead to the sensitivity decrease of sensor.
As described above, when semiconductor chip 110 is connected with the metal framework of side by wire bonding, sensor encapsulation
100 thickness thickens, this violates the purpose for pursuing light and short product.In order to form thicker insulating layer, to insulating materials
Selection there is limitation, and there is also limitations for fine pitch pattern.
The sensor encapsulation 100 of embodiment according to the present invention does not need the side for connection PCB substrate or lead frame
The conducting wire of the signal pad 113 of the metal framework and semiconductor chip 110 in portion.
In the case where the sensor of an embodiment according to the present invention encapsulates 100, due to the thickness of the first insulating layer 131
It can reduce, sensor device can be highly applicable to.
External connecting 150 may be coupled to the other side of feed throughs 123 and be mounted on external substrate (not to be shown in figure
On out), or may be electrically connected to another semiconductor chip or encapsulation etc..External connecting 150 can be by soldered ball, solder
The formation such as convex block or conducting sphere.Conducting sphere by copper, gold, nickel, aluminium, silver or can include the alloy of at least one of these metals
It is made.
Encapsulating material 140 can be with hermetic sealing substrate 120 and semiconductor chip 110 by substrate 120 and semiconductor chip 110
It is integrally formed.Encapsulating material 140 may include insulator, for example, may include epoxy molding compounds (EMC) or sealing
Agent.Encapsulating material 140 can be with the space between filling semiconductor chip 110 and substrate 120, and can be set to surround base
The lateral surface of plate 120 is with can be from outer protection substrate 120.
Encapsulating material 140 can be injected in the state of with mobility, then be solidified under high temperature environment.For example,
It may include the process for being heated and pressing simultaneously encapsulating material 140, at this point it is possible to increase vacuum process to remove encapsulating material
Gas etc. in 140.Also, encapsulating material 140 can be arranged by the method for being coated with or printing etc., and as encapsulating material
Various technologies usually used in the related technical field can be used in 140 plastic package method.
The signal pad that can be set such that semiconductor chip 110 on one side of encapsulating material 140 and feed throughs 123
End exposure.The active surface 111 of the one side and semiconductor chip 110 that have been shown in figure encapsulating material 140 is arranged same
In plane.The flatening process of encapsulating material 140 includes grinding, polishing or etching etc..
Moreover, the another side of encapsulating material 140 is arranged to cover the inactive surface 112 of semiconductor chip 110, with energy
Enough airtight and sealing semiconductor chips 110 securely.In contrast, it can be set according to the characteristic that required sensor encapsulates 100
It is set to the inactive surface exposure for making semiconductor chip 110.For example, encapsulating material 140 one side and semiconductor chip 110 it is non-
Active surface 112 is disposed on the same plane, thus, the thickness of sensor encapsulation 100 can be reduced, and for semiconductor chip
110 heat release may be advantageous.
Fig. 3 to Figure 16 is the sectional view for showing the manufacturing process of sensor encapsulation of an embodiment according to the present invention.
Referring to Fig. 3 to Figure 16, the manufacturing method of the sensor encapsulation of an embodiment according to the present invention includes: offer substrate
120 the step of, the substrate 120 are formed with the receiving portion 121 for accommodating semiconductor chip 110 and in the outer of described accommodation section 121
The perforative through-hole 122 of lateral edge up and down direction；The step of forming feed throughs 123 along the up and down direction of the through-hole 122；Described
Receiving portion 121 accommodates the step of including semiconductor chip 110 of signal pad 113 and sensor patterns 114；In the semiconductor core
So that the feed throughs 123, the signal pad 113 of the semiconductor chip 110 and institute on piece 110 and the substrate 120
State the step of insulating layer 131 are laminated in the mode that sensor patterns 114 expose；And so that the signal on the insulating layer 131
The step of mode that pad 113 and the feed throughs 123 are electrically connected forms wiring layer 132.
Fig. 3, which is shown, provides the process for the substrate 120 for being formed with described accommodation section 121.The substrate 120 may include
Insulating materials, for example, may include silicon, glass, ceramics, plastics or polymer etc..The substrate 120 can be configured to plate
Shape, but round or polygonal shape can be configured to.
Described accommodation section 121 forms the space for accommodating semiconductor chip 110, and can be configured to and semiconductor
The corresponding shape of the shape of chip 110.For example, described accommodation section 121 can when accommodating the semiconductor chip 110 of rectangle
To have rectangular shape in the direction of the width.Also, described accommodation section 121 can be set to through the substrate 120, or
Person can be set to the nonopen groove of one side.
The metal layer 120a can be stacked on the two sides of the substrate 120.For example, the metal layer 120a can be by
Copper foil is formed.
Fig. 4 shows the process to form the through-hole 122.The through-hole 122 is arranged to along the vertical direction through the base
Plate 120, and can be set in the periphery of described accommodation section 121.The section of the through-hole 122 can be circle, but can also be with
It is set as different shapes.The through-hole 122 can be set as multiple around described accommodation section 121, alternatively, and Fig. 4
Differently, two or more through-holes 122 can be extended upward through in a side of the periphery of described accommodation section 121.
The process of the formation through-hole 122 of the process and Fig. 4 of the formation receiving portion 121 of Fig. 3 may be performed simultaneously, and can also appoint
One first carries out.Also, it differently with attached drawing, can be initially formed the through-hole 122, then form described accommodation section 121.
Wiring technique, metal cutting processes, erosion can be used in the technique for forming described accommodation section 121 and the through-hole 122
Carving technology, bore process or laser ablation process execute.
Fig. 5 shows the process that the feed throughs 123 are formed in the through-hole 122.The feed throughs 123 can be by leading
Electric material is formed, it may include metal.Such as, it may include copper, copper alloy, aluminium or aluminium alloy.The feed throughs 123 can be with
It is deposited or is filled by techniques such as electroless plating, electrolysis plating, sputtering or printings and lead in the through-hole 122.As one
Example can be the metal coating for coating 122 inner face of through-hole, inside can form through hole.As another example,
It can be the conducting resinl or solder mask being filled into the through-hole 122.
The two sides that the feed throughs 123 are shown in Fig. 5 cover the two sides of the substrate 120.This is because utilizing electricity
On the face for the exposure that the feed throughs 123 can be layered in the substrate 120 when the techniques such as plating or sputtering.
The two sides that Fig. 6 shows the feed throughs 123 form the process of welding disk 125 (125a, 125b).The welding disk
125 may include conductive material, such as, it may include metal.The welding disk 125 can be configured to improve the feed throughs 123
With the electrical contact of the external connecting 150, such as contact angle and wetability can be improved.The welding disk 125 is available
The techniques such as deposition, electroless plating, electrolysis plating, sputtering or printing are layered on the feed throughs 123.
It is passed through as shown in figure 5, the welding disk 125 can all be layered in be laminated on the two sides of the substrate 120 described
It wears in wiring 123, the feed throughs being laminated in certain one side that can also be only layered in the two sides of the substrate 120
On 123.On the other hand, formed the welding disk 125 technique be it is selective, can according to circumstances omit.
Fig. 7 shows the process for removing a part of the feed throughs 123 and the welding disk 125a.In the substrate
It can only stay described through component 124 on the upper surface of 120, removal is covered with the upper of the welding disk 125a and the substrate 120
The feed throughs 123 in face and the metal layer 120a.Also, a certain range can be left below the substrate 120,
Removal is covered with the feed throughs 123 and the metal layer 120a of the upper surface of the welding disk 125b and described substrate 120.
It as an example, can be by only at the position that leave the welding disk 125b below the substrate 120
Adhere to dry film (not shown), and patterned, then pass through pattern etch process, removes the position without adhering to dry film
The welding disk 125b and the feed throughs 123 and the metal layer 120a.
Fig. 8 shows the process for planarizing the upper surface of described substrate 120.Grinding, polishing or etching can be used in flatening process
Deng.The substrate 120 can be formed in the same plane with the feed throughs 123 above by flatening process.With Fig. 7
Shown difference, there are the feed throughs 123, the metal layer 120a and/or the welding disks on the substrate 120
125b part or all when, can be also removed by flatening process.
Fig. 9 shows the process for adhering to the external connecting 150.The external connecting 150, which is attached to, stays in the base
On the welding disk 125 below plate 120, can be electrically connected with the feed throughs 123.The external connecting 150 with
The feed throughs 123 are connected and are installed on external substrate (not shown in figure), or can be with other semiconductor chips or encapsulation
Deng electrical connection.The external connecting 150 can be solder ball, solder projection or conducting sphere.Conducting sphere can by copper, gold, nickel,
Aluminium, silver or the alloy including one or more of these metals metal are formed.
Figure 10 shows the process for adhering to the substrate 120 and the semiconductor chip 110 in first vector 160.As
One example can be laminated first bonding part 161 in 160 upper surface of first vector, thus fix the substrate 120
With the semiconductor chip 110.The first vector 160 may include silicon, glass, ceramics, plastics or polymer etc..Described first
Bonding part 161 can be liquid adhesive or adhesive tape.
The face (the upper surface of substrate 120 in Fig. 9) of the planarization of the substrate 120 can adhere to the first vector 160
On, the external connecting 150 can be located above.The semiconductor chip 110 is inserted into the receiving of the substrate 120
Portion 121 is attached to the active surface 111 in the first vector 160.The formation of the semiconductor chip 110 has signal
The active surface 111 of pad 113 and sensor patterns 114 is attached on first bonding part 161, the nonactive table
Expose to top in face 112.
On the other hand, the semiconductor chip 110 can be separated with 121 medial surface of described accommodation section of the substrate 120 and be set
It sets and is fixed.That is, the area of plane of described accommodation section 121 can be greater than the area of plane of the semiconductor chip 110.With this phase
Instead, the side of the semiconductor chip 110 can contact with each other setting with the medial surface of the described accommodation section 121 of the substrate 120.
For example, the area of plane of described accommodation section 121 can be essentially identical with the area of plane of the semiconductor chip 110.
It is identical with the thickness of the semiconductor chip 110 shown in the drawings of the substrate 120, when being attached to described first
When on carrier 160, so that the one side of the substrate 120 and the inactive surface 112 of the semiconductor chip 110 have
Identical height.In contrast, the height of semiconductor chip 110 can be lower than the height of substrate 120, in the case, semiconductor core
The upper side of piece 110 can have segment difference relative to the upper side of substrate 120.
Figure 11 shows the process of plastic packaging encapsulating material 140.The salable substrate 120 of the encapsulating material 140 and described
Semiconductor chip 110, and it is integrally-formed.The encapsulating material 140 may include insulating materials, such as may include epoxy-plastic packaging material
(EMC) or sealant.
The encapsulating material 140 can be filled between the semiconductor chip 110 and the substrate 120, and be arranged to
The lateral surface of the substrate 120 is coated, so as to from substrate described in outer protection.Also, the encapsulating material 140 can quilt
It is arranged to it and is higher than the inactive surface 112 of the upper surface of described substrate 120 He the semiconductor chip 110 above, and exposes institute
State the end of external connecting 150.The encapsulating material 140 can be formed by mode of printing or compression forming mode.
As an example of the method for encapsulating material 140 described in plastic packaging, it may be used at the packet of mould inside injection liquid
By heating process come cured method after closure material 140.The encapsulating material 140 of liquid can be flowed into upper die and lower die
Between tool, fill between the semiconductor chip 110 and the substrate 120.In attached drawing, it is omitted for plastic packaging encapsulating material
140 mold.
Figure 12, which is shown, removes the first vector 160 and first bonding part 161, and by the encapsulating material 140
The process being attached on Second support 170 above.The packaging semi-finished product being integrated by the encapsulating material 140, can make institute
External connecting 150 is stated to getting off to be fixed in the Second support 170.As an example, on the Second support 170
The second bonding part 171 can be laminated in face, thus the fixed packaging semi-finished product being integrated by the encapsulating material 140.Another party
Face is exposed the active surface 111 of the semiconductor chip 110 by removing the first vector 160 and described is run through
Wiring 123.The Second support 170 may include silicon, glass, ceramics, plastics or polymer etc..Second bonding part 171 can
To be liquid adhesive or adhesive tape.
Second bonding part 171 can adhere to the one side of the encapsulating material 140, and accommodate from the encapsulating material 140
The external connecting 150 outstanding.As an example, second bonding part 171 can have elasticity.
Figure 13 shows the process to form first insulating layer 131.First insulating layer 131 can be to cover described half
The mode of conductor chip 110, the substrate 120 and the encapsulating material 140 is laminated.At this point, first insulating layer 131 can
Expose the feed throughs 123, the signal pad 113 and the sensor patterns 114.Remove first insulating layer 131
The process of a part can utilize etch process or laser ablation process.First insulating layer 131 may include insulating materials,
Such as, it may include oxide, nitride or epoxy-plastic packaging material etc..
Figure 14 shows the process to form wiring layer 132.The wiring layer 132 can be layered in first insulating layer 131
On, form the wiring pattern again for being electrically connected the signal pad 113 and the feed throughs 123.The wiring layer 132 can be filled
The part of the opening of first insulating layer 131 can connect in the process with the signal pad 113 and the feed throughs 123
It connects.
The wiring layer 132 may include conductive material, such as may include metal, such as copper, copper alloy, aluminium or aluminium alloy.
The wiring layer 132 can be formed by a variety of methods such as deposition, plating, printing.In contrast, the wiring layer 132 can be by pre-
First manufacture structural body composition, and technical idea of the invention further include by this structural body by roll-in, paste or
The modes such as reflux paste the situation on the signal pad 113 and the feed throughs 123.
Figure 15 shows the process to form second insulating layer 133.The second insulating layer 133 can be layered in first insulation
The face of the exposure of layer 131 and the wiring layer 132.The wiring layer 132 is covered shown in the drawings of the second insulating layer 133
And make the wiring layer 132 not to exposing outside, however can also unlike this, a part of the removal second insulating layer 133
And make the wiring layer 132 to exposing outside.At this point, the wiring layer 132 of exposure can be used as the path with external electrical connections.Institute
Stating second insulating layer 133 may include insulating materials, such as may include oxide, nitride or epoxy-plastic packaging material etc..
Figure 16, which is shown, removes the Second support 170 and second bonding part 171 to provide reality according to the present invention
Apply the process of the sensor encapsulation 100 of example.It removes the Second support 170 and exposes the external connecting 150.
Figure 17 is the sectional view encapsulated according to the sensor of one embodiment of the invention.
The sensor encapsulation 100 of 7 pairs of embodiment according to the present invention is illustrated referring to Fig.1.Referring to Fig.1 7, in addition to running through
Be routed and be formed on rest part except the component in the through-hole of feed throughs with according to described Fig. 1 and
The sensor encapsulation of Fig. 2 is identical, therefore, repeat description is abridged or is omitted.
The sensor encapsulation 100 of an embodiment according to the present invention includes: semiconductor chip 110, comprising being exposed to outside
Sensor patterns 114；Substrate 120, the receiving portion 121 comprising accommodating the semiconductor chip 110；Encapsulating material 140, so that
The semiconductor chip 110 and the integrated mode plastic packaging of the substrate 120；Feed throughs 123, in above-below direction through described
Substrate 120；Through component 124, it is filled in the through-hole formed in the feed throughs 123；Wiring portion 130 makes described partly to lead
Body chip 110 and the feed throughs 123 are electrically connected, and keep the sensor patterns 114 of the semiconductor chip 110 sudden and violent
Dew；And external connecting 150, it is electrically connected with the other side of the feed throughs 123, and can be with external electrical connections.
That is, an embodiment according to the present invention, the feed throughs 123, which can be, surrounds the through-hole 122
The conductive material of inner peripheral surface is also possible to the metal layer being coated on the through-hole 122.The feed throughs 123 can be in circle
Post shapes can be filled in the through-hole for being formed in the feed throughs 123 through component 124.It is described can be with through component 124
It is nonconductive resin, the through-hole of the feed throughs 123 can also be filled in, that is, hollow portion.On the other hand, the through-Penetration portion
Part 124 can be formed from conductive materials.
Figure 18 is the sectional view of the packaging body lamination of stacking sensor encapsulation shown in FIG. 1.Figure 18 is the multiple Fig. 1 of stacking
Shown in sensor encapsulation 100 packaging body lamination (Package-on-Package, POP) sectional view.
Packaging body lamination can have the form of two or more semiconductor packages stacking.At this point, what is be laminated partly leads
Body encapsulation can be different types of product.Packaging body lamination can have sensor encapsulation 100-2 and partly leading unlike this
Body encapsulates 100-1, for example, the structure of memory or logic semiconductor encapsulation stacked vertical.
The external connecting 150 of the sensor encapsulation 100-2 and the wiring portion 130 of other semiconductor packages 100-1 can
To be electrically connected to each other.
Specifically, can be equipped with upper sensor on lower semiconductor encapsulation 100-1 encapsulates 100-2, lower semiconductor envelope
The second insulating layer 133 of dress 100-1 can make a part exposure of wiring layer 132, and upper sensor encapsulates the external connection of 100-2
Portion 150 is attached to the wiring layer 132 of the lower semiconductor encapsulation 100-1 of exposing.
The present invention is illustrated with reference to the embodiment illustrated in attached drawing, but this is merely possible to illustrate, as long as institute
Category field technical staff will readily appreciate that through these and carry out the other embodiments of various deformation and equalization.Therefore, of the invention
Real protection scope should be determined by claim.
Claims (9)
1. a kind of sensor encapsulation characterized by comprising
Semiconductor chip, comprising being exposed to external sensor patterns；
Substrate, the receiving portion comprising accommodating the semiconductor chip；
Encapsulating material, by make the semiconductor chip and the substrate it is integrated in a manner of plastic packaging；
Feed throughs run through the substrate in above-below direction；
Wiring portion is electrically connected the semiconductor chip and the feed throughs, and makes the sensing of the semiconductor chip
The exposure of device pattern；And
External connecting is electrically connected with the other side of the feed throughs, and can be with external electrical connections；
The semiconductor chip, the substrate and the encapsulating material are disposed on the same plane,
The wiring portion is layered on the semiconductor chip, the substrate and the encapsulating material；
The wiring portion includes:
First insulating layer makes signal pad and the feed throughs exposure of the semiconductor chip；
Wiring layer, setting on the first insulating layer, and are electrically connected the signal pad and the feed throughs；And
Second insulating layer is arranged on first insulating layer and the wiring layer, to cover the wiring layer, and makes described half
The sensor patterns exposure of conductor chip.
2. sensor encapsulation according to claim 1, which is characterized in that first insulating layer includes opening portion, described
Opening portion exposes the signal pad and the feed throughs respectively,
The wiring layer is connected to the signal pad and the feed throughs by filling the opening portion of first insulating layer.
3. sensor encapsulation according to claim 1, which is characterized in that the substrate is formed with perforative in above-below direction
Through-hole,
The feed throughs are formed by the conductive material for filling in the through hole.
4. sensor encapsulation according to claim 3, which is characterized in that the feed throughs are formed by conducting resinl.
5. sensor encapsulation according to claim 1, which is characterized in that it further include welding disk, the one side of the welding disk
The feed throughs are attached to, and another side is attached to the external connecting, the welding disk is formed by conductive material.
6. sensor encapsulation according to claim 5, which is characterized in that adhere to the end of the feed throughs of the welding disk
It is configured to prominent from the substrate and extends to outside.
7. sensor encapsulation according to claim 6, which is characterized in that adhere to the end of the feed throughs of the welding disk
It is configured to prominent from the substrate and extends to outside.
8. sensor encapsulation according to claim 1, which is characterized in that the substrate is formed with perforative in above-below direction
Through-hole,
The feed throughs surround the inner peripheral surface of the through-hole,
It is formed in the through-hole of the feed throughs filled with through component.
9. sensor encapsulation according to claim 8, which is characterized in that
It is described to be formed through component by nonconductive resin.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2016-0013959 | 2016-02-04 | ||
| KR1020160013959A KR20170093277A (en) | 2016-02-04 | 2016-02-04 | Sensor package and method of manufacturinng the same |
| PCT/KR2017/000802 WO2017135624A1 (en) | 2016-02-04 | 2017-01-24 | Sensor package and method for preparing same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208767298U true CN208767298U (en) | 2019-04-19 |
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|---|---|---|---|
| CN201790000502.1U Active CN208767298U (en) | 2016-02-04 | 2017-01-24 | Sensor encapsulation |
Country Status (3)
| Country | Link |
|---|---|
| KR (1) | KR20170093277A (en) |
| CN (1) | CN208767298U (en) |
| WO (1) | WO2017135624A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111354652A (en) * | 2019-12-17 | 2020-06-30 | 华天科技（昆山）电子有限公司 | High-reliability image sensor wafer-level fan-out packaging structure and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102052804B1 (en) | 2017-12-15 | 2019-12-05 | 삼성전기주식회사 | Fan-out sensor package |
| KR20190088812A (en) | 2018-01-19 | 2019-07-29 | 삼성전자주식회사 | Fan-out sensor package |
| KR102015910B1 (en) * | 2018-01-24 | 2019-10-23 | 삼성전자주식회사 | Electronic component package |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001237337A (en) * | 2000-02-23 | 2001-08-31 | Sumitomo Metal Electronics Devices Inc | Plastic package and method of manufacturing the same |
| TWI474447B (en) * | 2009-06-29 | 2015-02-21 | Advanced Semiconductor Eng | Semiconductor package structure and enveloping method thereof |
| KR101059629B1 (en) * | 2009-12-29 | 2011-08-25 | 하나 마이크론(주) | Semiconductor Package Manufacturing Method |
| KR101362714B1 (en) * | 2012-05-25 | 2014-02-13 | 주식회사 네패스 | Semiconductor package, method of manufacturing the same and package-on-package |
| KR101419600B1 (en) * | 2012-11-20 | 2014-07-17 | 앰코 테크놀로지 코리아 주식회사 | Package of finger print sensor and fabricating method thereof |
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2016
- 2016-02-04 KR KR1020160013959A patent/KR20170093277A/en active Search and Examination
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111354652A (en) * | 2019-12-17 | 2020-06-30 | 华天科技（昆山）电子有限公司 | High-reliability image sensor wafer-level fan-out packaging structure and method |
| CN111354652B (en) * | 2019-12-17 | 2022-03-08 | 华天科技（昆山）电子有限公司 | High-reliability image sensor wafer-level fan-out packaging structure and method |
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| WO2017135624A1 (en) | 2017-08-10 |
| KR20170093277A (en) | 2017-08-16 |
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