201036113 • « 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種無基板晶片封裝及其製造方法，特 別係關於一種移除基板之晶片封裝及其製造方法。 【先前技術】 基板係習知封裝技術中用來承載晶粒之載體，並且電 性連接至晶粒之焊墊（bonding pad)。除了基板之厚度會 〇 使得封裝件之整體厚度增加，另外電氣特性（electrical characteristics)也會受到基板之電路層佈置的影響。亦即 傳遞電氣訊號之路徑會太長而電阻增加。 此外，基板之絕緣層多為導熱不佳之高分子材料，例 如·環氧樹脂及聚亞醯胺（P〇lyimi(Je)，因此會影響封裝 件之散熱。 此外，基板之膨脹係數均和封裝膠體不同或不匹配。 因此當受到溫昇後，例如：加熱固化或迴焊（ren〇w)，會 〇 在二者之結合界面間產生殘留應力，甚至因應力產生裂縫 之破壞。 近來電子封裝領域之發展趨勢，多要求電子封裝件能 夠輕、薄、短、小。為滿足此一需求，或可採取晶圓級封 裝技術將外部電路及1/0接點直接形成在晶片上，但相對製 造成本就會增高很多。為此本發明提出一種封裝結構，不 但能符合電子封裝領域之發展趨勢，而且也是採成本較低 之製程製造。 【發明内容】 137400(20081 〇〇〇 1 ).〇〇ς 201036113 本發明之一範例係提供一種無基板晶片封裝及其製造 方法，藉由一般電路板之製程就能完成無基板之晶片封裝 ’因此製造成本低廉》 本發明之一範例係提供一種整體厚度薄之晶片封裝結 構。藉由一暫時金屬板完成前半部份之製程，再將暫時金 屬板以蝕刻去除，如此就能得到無基板之薄型晶片封裝件 0201036113 • «6. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a substrateless wafer package and a method of fabricating the same, and more particularly to a wafer package for removing a substrate and a method of fabricating the same. [Prior Art] A substrate is a carrier used to carry a die in a conventional packaging technique, and is electrically connected to a bonding pad of a die. In addition to the thickness of the substrate, the overall thickness of the package is increased, and electrical characteristics are also affected by the circuit layer arrangement of the substrate. That is, the path for transmitting electrical signals will be too long and the resistance will increase. In addition, the insulating layer of the substrate is mostly a poorly conductive polymer material, such as epoxy resin and polyamidamine (Pelyimi (Je), thus affecting the heat dissipation of the package. In addition, the expansion coefficient of the substrate is equal to the package. Colloids are different or do not match. Therefore, when subjected to temperature rise, for example, heat curing or reflowing, residual stress is generated between the bonding interface of the two, and even cracks are caused by stress. The development trend of the field requires electronic packages to be light, thin, short and small. To meet this demand, wafer-level packaging technology can be used to form external circuits and 1/0 contacts directly on the wafer, but The manufacturing cost is much higher. Therefore, the present invention proposes a package structure that not only conforms to the development trend of the electronic packaging field, but also is a process manufacturing process with a lower cost. [Abstract] 137400(20081 〇〇〇1 ).〇 〇ς 201036113 An example of the present invention provides a substrateless chip package and a method of fabricating the same, which can be completed by a general circuit board process. 'Therefore, the manufacturing cost is low.' An example of the present invention provides a chip package structure having a thin overall thickness. The process of the first half of the process is completed by a temporary metal plate, and the temporary metal plate is removed by etching, so that no substrate can be obtained. Thin chip package 0
Ο 綜上所述，本發明揭露一種無基板晶片封裝，其包含 一圖案化線路層、複數個連接柱、複數個第二接點、一曰 曰曰 片、一黏膠層、複數個金屬導線及封裝膠體。該圖案化線 路層包含複數個接墊、複數個第一接點及複數個連接至少 -該接墊與至少-該第—接點之連接線。該複數個連接柱 係設置於圖案化線路層之至少一該第一接點上。該複數個 第二接點係設置於至少一該連接柱上。該晶片包含一主動 面及複數個設置於主動面上之銲墊。該黏膠層黏著結合於 該晶片之主動面及圖案化線路層之間。該複數個金屬導線 電性連接該晶片之銲墊及該複數個第二接點^該封裝膠體 至少覆蓋該晶片、該圖案化線路層、該複數個連接柱、該 複數個第二接點及該複數個金屬導線之一部份。 本發明另揭露-種無基板晶片封裝之製造方法，其包 含下列步驟··提供—金屬板，其包含-第-表面及一第二 表面’其中該第一表面具有複數個第一凸部、複數個第一 凹部及至少-第二凹部，又該第二表面上具有一對應第二 凹部之第三凹部，該第三凹料具—與該第二凹部相連通In summary, the present invention discloses a substrateless chip package including a patterned circuit layer, a plurality of connecting posts, a plurality of second contacts, a die, an adhesive layer, and a plurality of metal wires. And encapsulation colloid. The patterned circuit layer includes a plurality of pads, a plurality of first contacts, and a plurality of connections connecting at least the pads to at least the first contacts. The plurality of connection pillars are disposed on at least one of the first contacts of the patterned circuit layer. The plurality of second contacts are disposed on at least one of the connecting posts. The wafer includes an active surface and a plurality of pads disposed on the active surface. The adhesive layer is adhesively bonded between the active surface of the wafer and the patterned wiring layer. The plurality of metal wires are electrically connected to the pad of the chip and the plurality of second contacts, the package encapsulation covering at least the wafer, the patterned circuit layer, the plurality of connection posts, the plurality of second contacts, and One of the plurality of metal wires. The present invention further discloses a method for manufacturing a substrateless wafer package, comprising the steps of: providing a metal plate comprising a first surface and a second surface, wherein the first surface has a plurality of first protrusions, a plurality of first recesses and at least a second recess, the second surface having a third recess corresponding to the second recess, the third recessed material being in communication with the second recess
137400(2008I0001).D〇C 201036113 * a 之通孔；形成複數個接墊及複數個第一接點於該金屬板上 之複數個第一凸部與第二凹部上，其中該至少一接墊與至 少第一接點彼此連接；形成複數個第二接點於該第三凹部 上，&供一晶片’其具有一主動面’及複數個設置於主動 面上之銲墊，並黏置該晶片於該金屬板之第一表面上，及 藉由該金屬板之通孔曝露出該晶片之主動面之銲墊；藉由 複數個金屬導線穿過該金屬板之通孔電性連接該主動面之 ❹ 銲墊及該複數個第二接點；以封裝膠體覆蓋該晶片、該金 屬板之第一表面及該複數個金屬導線；以及選擇性蝕刻該 金屬板之第二表面直至該複數個接墊露出。 本發明另揭露一種無基板晶片封裝之製造方法，其包 含下列步驟：提供一金屬板，其包含一第一表面及一第二 表面’又該第二表面上具有一凹部，該凹部中具一和該第 一表面相接之通孔；形成複數個接墊及複數個第一接點於 該金屬板之該第一表面，其中該至少一接整與至少第一接 〇 點彼此連接；形成複數個第二接點於該凹部上；提供一晶 片’其具有一主動面’及複數個設置於主動面上之銲墊， 並黏置該晶片於該金屬板之第一表面上，及藉由該金屬板 之通孔曝露出該晶片之主動面之銲墊；藉由複數個金屬導 線穿過該金屬板之通孔電性連接該主動面之銲墊及該複數 個第二接點；以封裝膠體覆蓋該晶片、該金屬板之第一表 面及該複數個金屬導線；以及選擇性蝕刻該金屬板之第二 表面直至該複數個接墊露出。 【實施方式】137400(2008I0001).D〇C 201036113 * a through hole; forming a plurality of pads and a plurality of first contacts on the plurality of first protrusions and second recesses on the metal plate, wherein the at least one connection The pad is connected to at least the first contact; the plurality of second contacts are formed on the third recess, and a wafer is provided with an active surface and a plurality of pads disposed on the active surface, and is adhered Depositing the wafer on the first surface of the metal plate, and exposing the active surface pad of the wafer through the through hole of the metal plate; electrically connecting through the through holes of the metal plate through the plurality of metal wires a pad of the active surface and the plurality of second contacts; covering the wafer, the first surface of the metal plate and the plurality of metal wires with an encapsulant; and selectively etching the second surface of the metal plate until the A plurality of pads are exposed. The invention further discloses a method for manufacturing a substrateless wafer package, comprising the steps of: providing a metal plate comprising a first surface and a second surface; and the second surface has a concave portion, the concave portion having a a through hole connected to the first surface; forming a plurality of pads and a plurality of first contacts on the first surface of the metal plate, wherein the at least one alignment and at least the first connection points are connected to each other; forming a plurality of second contacts are disposed on the recess; a wafer is provided having an active surface and a plurality of pads disposed on the active surface, and the wafer is adhered to the first surface of the metal plate, and Exposing the active surface of the wafer to the through hole of the metal plate; electrically connecting the active surface pad and the plurality of second contacts through a plurality of metal wires through the through hole of the metal plate; Covering the wafer, the first surface of the metal plate and the plurality of metal wires with an encapsulant; and selectively etching the second surface of the metal plate until the plurality of pads are exposed. [Embodiment]
137400(200810001).DOC -6· 201036113 ® 1A〜1E係本發明一實施例之無基板晶片封裝製造 方法之示意圖。如圖1A所示，提供一金屬板18，其包含一 第一表面181及一第二表面182。於此實施例中，該第一表 面181具有複數個第一凸部Ian、第一凹部1812及至少一第 二凹部1813 ^然於其他實施例中，該第一表面181不需要設 有該第一凸部1811、第一凹部1812及第二凹部1813，亦即 第一表面181仍維持一完整之平面。又該第二表面182上具 〇 有一對應第二凹部丨8丨3之第三凹部18η，該第三凹部1821 中具有一與該第二凹部1813相連通之通孔141。該第一凹部 1812、第二凹部1813、第三凹部1821及通孔141可藉由蝕刻 製程形成於原本為平板狀之金屬板18上。該金屬板18可以 是銅、鐵或紹之金屬材料。 參見圖1A ’於此實施例中，繼續形成複數個接墊u1 於該金屬板18上之複數個第一凸部1811，及形成複數個第 一接點112於該金屬板18上之第二凹部1813上，例如：以链 Ο 金之電鍍（或喷印、印刷等製程）製程形成接墊111及第一接 點112於銅材之金屬板18上，或者電鍍（或喷印、印刷等製 程）鈀、銀、鎳金合金或錫鉛合金等焊接性較佳之金屬材料 。然於前述其他實施例中，該複數個接墊ln可以直接形成 於一凡整平面之第一表面181上，因此該複數個接墊ln係 凸設於該第一表面181。接著，於該複數個第一凹部1812 及該第二凹部1813内形成複數個連接線113，如此使得該至 少一接墊ill與至少第一接點112彼此相連接。該連接線113 也可採用電鍍方式形成。相似地，形成複數個第二接點13 137400(20081000t).DOC 7 201036113 « « 於該第二凹部1821上’亦即於第三凹部1821之四周底面電 鐘衩數個第二接點13 ’例如：電鍍金、纪、銀、鎳金合金 或錫錯合金。該複數個接墊111、複數個第一接點U2及複 數個連接線113構成圖案化線路層u。 如圖1B所示，提供一晶片12,其具有一主動面121及複 數個設置於主動面121上之銲墊122。並藉由一黏膠層15黏 置該晶片12於該金屬板18之第一表面181上，且該金屬板18 ❹ 之通孔141使該晶片丨2之主動面121之銲墊122露出。經過通 孔141可以完成銲墊122和該複數個第二接點13間電性連接 ，亦即藉由複數個金屬導線16穿過金屬板18之通孔141，從 而電性連接該主動面121之銲墊122及該複數個第二接點13 。該黏膠層15可以藉由塗佈或印刷等方式覆蓋於金屬板18 之第一表面181上對應於晶片12之主動面121處，亦即覆蓋 於第一表面181上有主動面121疊置之區域。 為保護晶片12及金屬導線16不受外力破壞，可以封裝 © 膠體19覆蓋該晶片12、該金屬板18之第一表面181及該複數 個金屬導線16，參見圖1C。該封裝膠體19可採轉注模（ transfer molding )或壓縮模（c〇mpressi〇n m〇lding)方式填充 於第二凹部1813、通孔141及第三凹部1821内，及覆蓋該晶 片I2之背面及該金屬板18之第一表面181上。 由於金屬板18之第二表面182除第三凹部1821為凹入 部分，其他部分均為-平坦之板面。於模封（m〇lding)時 ，可使用習用之平底下模具抵靠於第二表面182之平坦部分 ，並使封裝膠體19充填於第三凹部1821中，無需另外製作137400 (200810001).DOC -6·201036113® 1A to 1E are schematic views of a method of manufacturing a substrateless wafer package according to an embodiment of the present invention. As shown in FIG. 1A, a metal plate 18 is provided which includes a first surface 181 and a second surface 182. In this embodiment, the first surface 181 has a plurality of first protrusions Ian, a first recess 1812, and at least a second recess 1813. In other embodiments, the first surface 181 does not need to be provided. A convex portion 1811, a first concave portion 1812, and a second concave portion 1813, that is, the first surface 181 still maintain a complete plane. Further, the second surface 182 has a third recess 18n corresponding to the second recess 丨8丨3, and the third recess 1821 has a through hole 141 communicating with the second recess 1813. The first concave portion 1812, the second concave portion 1813, the third concave portion 1821, and the through hole 141 can be formed on the original flat metal plate 18 by an etching process. The metal plate 18 may be copper, iron or a metal material. Referring to FIG. 1A, in this embodiment, a plurality of first protrusions 1811 of a plurality of pads u1 on the metal plate 18 are formed, and a plurality of first contacts 112 are formed on the metal plate 18. On the recess 1813, for example, the pad 111 and the first contact 112 are formed on the metal plate 18 of the copper material by electroplating (or printing, printing, etc.) processes, or electroplating (or printing, printing, etc.) Process) Palladium, silver, nickel-gold alloy or tin-lead alloy and other metal materials with better weldability. In the foregoing other embodiments, the plurality of pads ln may be directly formed on the first surface 181 of the planar surface, so that the plurality of pads LM are protruded from the first surface 181. Then, a plurality of connecting lines 113 are formed in the plurality of first recesses 1812 and the second recesses 1813 such that at least one of the pads ill and at least the first contacts 112 are connected to each other. The connection line 113 can also be formed by electroplating. Similarly, a plurality of second contacts 13 137400 (20081000t) are formed. DOC 7 201036113 «The upper portion of the second recess 1821 is electrically connected to the bottom surface of the third recess 1821. For example: electroplated gold, gold, silver, nickel alloy or tin alloy. The plurality of pads 111, the plurality of first contacts U2, and the plurality of connecting lines 113 constitute a patterned wiring layer u. As shown in FIG. 1B, a wafer 12 is provided having an active surface 121 and a plurality of pads 122 disposed on the active surface 121. The wafer 12 is adhered to the first surface 181 of the metal plate 18 by an adhesive layer 15, and the through hole 141 of the metal plate 18 exposes the pad 122 of the active surface 121 of the wafer cassette 2. The electrical connection between the bonding pad 122 and the plurality of second contacts 13 is performed through the through holes 141, that is, the plurality of metal wires 16 pass through the through holes 141 of the metal plate 18 to electrically connect the active surface 121. a pad 122 and the plurality of second contacts 13 . The adhesive layer 15 may be coated on the first surface 181 of the metal plate 18 by coating or printing, corresponding to the active surface 121 of the wafer 12, that is, the first surface 181 is covered with the active surface 121. The area. In order to protect the wafer 12 and the metal wires 16 from external force damage, a package 19 may be applied to cover the wafer 12, the first surface 181 of the metal plate 18, and the plurality of metal wires 16, see FIG. 1C. The encapsulant 19 can be filled in the second recess 1813, the through hole 141 and the third recess 1821 by means of a transfer molding or a compression mold, and covers the back surface of the wafer I2. The first surface 181 of the metal plate 18 is on the surface. Since the second surface 182 of the metal plate 18 is a concave portion except for the third concave portion 1821, the other portions are all - flat plate faces. In the case of molding, a flat bottom mold can be used to abut against the flat portion of the second surface 182, and the encapsulant 19 is filled in the third recess 1821 without additional fabrication.
137400(2008l0001).D〇C 201036113 « · 專用模具’就能大幅節省成本。 如圖1D所示，藉由蝕刻製程將大部份金屬板18移除， 僅留下位於複數個第一接點112及複數個第二接點13間之 複數個連接柱14。亦即，選擇性蝕刻該金屬板18之第二表 面182直至該複數個接墊u露出，且連接線113及第一接點 112也會露出。 如圖1E所示，於該複數個接墊1U表面分別固定複數個 ❹ 錫球17，如此無基板晶片封裝10就具有外部I/O接點，並可 供焊接於其他電路板上。錫球17之最底處可較封裝膠體19 之下表面更低，如此有利於焊接至平板狀之電路板。 圖2係圖1D中尚未固定複數個錫球17之無基板晶片封 裝之仰視圖。如圖所示，該封裝膠體19環繞圖案化線路層 11，又可清楚見到該圖案化線路層〗丨包含複數個接塾丨1 ^、 複數個第一接點112及複數個連接至少一該接墊η〗與至少 連接該第一接點112之連接線113。兩個區域之黏膠層15 G 也因金屬板18之移除而露出，當然該黏膠層15也以加熱而 固化。中間長條狀之封裝膠體19將複數個金屬導線16及第 二接點13覆蓋並保護。圖1A〜1E中之截面圖係對應至圖2 中A — A剖面線。 圖3係本發明一實施例之無基板晶片封裝件之剖面示 意圖。無基板晶片封裝10包含一圖案化線路層1]L、複數個 連接柱14、複數個第二接點13、一晶片12、一黏膠層μ、 複數個金屬導線16及一封裝膠體19。該一圖案化線路層u 包含複數個接墊111、複數個第一接點112及複數個連接至 137400(2008|〇〇〇l).D〇c -9- 201036113137400 (2008l0001).D〇C 201036113 « · Special molds can save a lot of money. As shown in FIG. 1D, most of the metal plates 18 are removed by an etching process, leaving only a plurality of connecting posts 14 between the plurality of first contacts 112 and the plurality of second contacts 13. That is, the second surface 182 of the metal plate 18 is selectively etched until the plurality of pads u are exposed, and the connection line 113 and the first contact 112 are also exposed. As shown in FIG. 1E, a plurality of solder balls 17 are respectively fixed on the surface of the plurality of pads 1U, so that the substrateless chip package 10 has external I/O contacts and can be soldered to other circuit boards. The bottom of the solder ball 17 can be lower than the lower surface of the encapsulant 19, which is advantageous for soldering to a flat circuit board. Figure 2 is a bottom plan view of the substrateless wafer package in which a plurality of solder balls 17 have not been fixed in Figure 1D. As shown in the figure, the encapsulant 19 surrounds the patterned circuit layer 11, and it is clearly seen that the patterned circuit layer includes a plurality of interfaces 1^, a plurality of first contacts 112, and a plurality of connections at least one The pad η is connected to at least the connecting line 113 of the first contact 112. The adhesive layer 15 G of the two regions is also exposed by the removal of the metal plate 18, and of course the adhesive layer 15 is also cured by heating. The intermediate strip-shaped encapsulant 19 covers and protects the plurality of metal wires 16 and the second contacts 13. The cross-sectional views in Figs. 1A to 1E correspond to the A-A hatching in Fig. 2. Figure 3 is a cross-sectional view showing a substrateless chip package in accordance with an embodiment of the present invention. The substrateless package 10 includes a patterned wiring layer 1]L, a plurality of connecting pillars 14, a plurality of second contacts 13, a wafer 12, an adhesive layer μ, a plurality of metal wires 16 and an encapsulant 19. The patterned circuit layer u includes a plurality of pads 111, a plurality of first contacts 112, and a plurality of connections to 137400 (2008|〇〇〇l). D〇c -9- 201036113
• I 少一該接墊111與至少一該第一接點112之連接線113。該複 數個連接柱14設置於該圖案化線路層11之至少一該第一接 點上112。該複數個第二接點13設置於至少一該連接柱14 上。該晶片12包含一主動面121及複數個設置於主動面121 上之銲墊122 «該黏膠層15黏著結合於該晶片12之主動面 121及該圖案化線路層11之間。該複數個金屬導線16電性連 接該晶片12之銲墊122及該複數個第二接點13。該封裝膠體 ❹ 19至少覆蓋該晶片12、該圖案化線路層11、該複數個連接 柱14、該複數個第二接點13及該複數個金屬導線16之一部 份。該封裝膠體19底部設置有複數個凹穴（未標號），且該 複數個接墊111係分別位於該封裝膠體丨9之複數個凹穴内。 圖4A〜4E係本發明另一實施例之無基板晶片封裝製 造方法之示意圖。如圖4 A所示，提供一金屬板48,其包含 一第一表面481及一第二表面482。又該第二表面482中央上 具有一凹部4821，該凹部4821中具有一與該第一表面481 ❹ 相連通之通孔441。該凹部4821及通孔441可藉由蝕刻製程 形成於原本為平板狀之金屬板48上。該金屬板48可以是銅 、鐵或鋁之金屬材料。 參見圖4 A，於此實施例中，繼續形成複數個接墊411 於該金屬板48之第一表面481，及形成複數個第一接點412 於該金屬板48之第一表面481上鄰接通孔441處，例如：以 鍍金之電鍍(或喷印、印刷等製程）製程形成接墊411及第一 接點412於銅材之金屬板48上，或者電鑛（或喷印、印刷等 製程）把、銀、錄金合金或錫錯合金等焊接性較佳之金屬材 137400(200810001)^ -10- 201036113 • « 料。然於前述其他實施例中，該複數個接墊41丨可以直接形 成於一完整平面之第一表面481上，因此該複數個接墊411 係凸設於該第一表面481。接著，於該複數個接墊411及該 複數個第一接點412間形成複數個連接線413，如此使得該 至少一接塾411與至少第一接點412彼此相連接。該連接線 413也可採用電鍍方式形成。相似地，形成複數個第二接點 43於該凹部4821上，亦即於凹部4821之四周底面電鍍複數 0 個第二接點43，例如：電鍍金、鈀、銀、鎳金合金或錫錯 合金。該複數個接墊411、複數個第一接點412及複數個連 接線413構成圖案化線路層41。 如圖4B所示，提供一晶片42’其具有一主動面421及複 數個設置於主動面421上之銲墊422。並藉由一黏膠層45黏 置該晶片42於該金屬板48之第一表面481上，且該金屬板48 之通孔441使該晶片42之主動面421之銲墊422露出。經過通 孔441可以完成銲墊422和該複數個第二接點43間電性連接 ❹ ，亦即藉由複數個金屬導線46穿過金屬板48之通孔441，從 而電性連接該主動面421之銲墊422及該複數個第二接點43 。該黏膠層45可以藉由塗佈或印刷等方式覆蓋於金屬板48 之第一表面481上對應於晶片42之主動面421處，亦即覆蓋 於第一表面481上有主動面421疊置之區域。 為保護晶片42及金屬導線46不受外力破壞，可以封裝： 膠體49覆蓋該晶片42、該金屬板48之第一表面481及該複數 個金屬導線46，參見圖4C。該封裝膠體49可採轉j：主模（ transfer molding)或壓縮模（Compression molding)方式填充 137400(200810001).DOC -11· 201036113 s « 於通孔441及凹部4821内，及覆蓋該晶片42之背面及該金屬 板48之第一表面481上。 由於金屬板48之第二表面482除凹部4821為凹入部分 ，其他部分均為一平坦之板面。於模封（m〇lding)時，可 使用習用之平底下模具抵靠於第二表面482之平坦部分，並 使封裝膠體49充填於凹部4821中，無需另外製作專用模具 ，就能大幅節省成本。 ❹ 如圖4D所示，藉由蝕刻製程將大部份金屬板48移除， 僅留下位於複數個第一接點412及複數個第二接點43間之 複數個連接柱44。亦即，選擇性蝕刻該金屬板48之第二表 面482直至該複數個接墊41露出，且連接線413及第一接點 412也會露出。 如圖4E所示，於該複數個接墊411表面分別固定複數個 錫球47，如此無基板晶片封裝4〇就具有外部1/〇接點，並可 供焊接於其他電路板上。 〇 本發明之技術内容及技術特點已揭示如上，然而熟悉 本項技術之人士仍可能基於本發明之教示及揭示而作種種 不背離本發明精神之替換及修飾。因此，本發明之保護範 圍應不限於實施例所揭示者，而應包括各種不背離本發明 之替換及修飾，並為以下之申請專利範圍所涵蓋。 【圖式簡要說明】 圖1A〜1E係本發明一實施例之無基板晶片封裝製造 方法之不意圖； 圖2係圖1D中尚未固定複數個錫球之無基板晶片封裝 137400(2008]000i).DOC -12- 201036113 之仰視圖； 圖3係本發明一實施例之無基板晶片封裝件之剖面示 意圖；以及 圖4A〜4E係本發明另一實施例之無基板晶片封裴製 造方法之示意圖。 【主要元件符號說明】 10 無基板晶片封|• I has one less connection line 113 between the pad 111 and at least one of the first contacts 112. The plurality of connection posts 14 are disposed on at least one of the first contacts 112 of the patterned circuit layer 11. The plurality of second contacts 13 are disposed on at least one of the connecting posts 14. The wafer 12 includes an active surface 121 and a plurality of pads 122 disposed on the active surface 121. The adhesive layer 15 is adhesively bonded between the active surface 121 of the wafer 12 and the patterned wiring layer 11. The plurality of metal wires 16 are electrically connected to the pads 122 of the wafer 12 and the plurality of second contacts 13. The encapsulant ❹ 19 covers at least the wafer 12, the patterned wiring layer 11, the plurality of connecting posts 14, the plurality of second contacts 13, and a portion of the plurality of metal wires 16. A plurality of recesses (not labeled) are disposed at the bottom of the encapsulant 19, and the plurality of pads 111 are respectively located in a plurality of recesses of the encapsulant colloid 9. 4A to 4E are schematic views showing a method of manufacturing a substrateless wafer package according to another embodiment of the present invention. As shown in FIG. 4A, a metal plate 48 is provided that includes a first surface 481 and a second surface 482. Further, the second surface 482 has a concave portion 4821 in the center thereof, and the concave portion 4821 has a through hole 441 communicating with the first surface 481 。. The concave portion 4821 and the through hole 441 can be formed on the metal plate 48 which is originally in the form of a flat plate by an etching process. The metal plate 48 may be a metal material of copper, iron or aluminum. Referring to FIG. 4A, in this embodiment, a plurality of pads 411 are formed on the first surface 481 of the metal plate 48, and a plurality of first contacts 412 are formed adjacent to the first surface 481 of the metal plate 48. At the through hole 441, for example, a gold plating (or printing, printing, etc.) process is used to form the pad 411 and the first contact 412 on the metal plate 48 of the copper material, or electric ore (or printing, printing, etc.) Process) Metals with better solderability such as silver, gold alloy or tin alloy. 137400(200810001)^ -10- 201036113 • «Material. In the foregoing other embodiments, the plurality of pads 41 can be directly formed on the first surface 481 of a complete plane. Therefore, the plurality of pads 411 are protruded from the first surface 481. Then, a plurality of connecting lines 413 are formed between the plurality of pads 411 and the plurality of first contacts 412 such that the at least one interface 411 and the at least first contacts 412 are connected to each other. The connection line 413 can also be formed by electroplating. Similarly, a plurality of second contacts 43 are formed on the recesses 4821, that is, a plurality of second contacts 43 are plated on the bottom surfaces of the recesses 4821. For example, electroplating gold, palladium, silver, nickel gold alloy or tin bump alloy. The plurality of pads 411, the plurality of first contacts 412, and the plurality of wires 413 constitute a patterned wiring layer 41. As shown in FIG. 4B, a wafer 42' is provided having an active surface 421 and a plurality of pads 422 disposed on the active surface 421. The wafer 42 is adhered to the first surface 481 of the metal plate 48 by an adhesive layer 45, and the through hole 441 of the metal plate 48 exposes the pad 422 of the active surface 421 of the wafer 42. The electrical connection between the bonding pad 422 and the plurality of second contacts 43 is completed through the through holes 441, that is, the plurality of metal wires 46 pass through the through holes 441 of the metal plate 48 to electrically connect the active surface. 421 pads 422 and the plurality of second contacts 43. The adhesive layer 45 can be coated on the first surface 481 of the metal plate 48 by coating or printing, etc., corresponding to the active surface 421 of the wafer 42, that is, the active surface 421 is covered on the first surface 481. The area. To protect the wafer 42 and the metal wires 46 from external forces, a package 49 can be used to cover the wafer 42, the first surface 481 of the metal plate 48, and the plurality of metal wires 46, see FIG. 4C. The encapsulant 49 can be filled with a transfer molding or a compression molding method to fill 13740 (200810001). DOC -11· 201036113 s « in the through hole 441 and the recess 4821, and cover the wafer 42 The back side and the first surface 481 of the metal plate 48. Since the second surface 482 of the metal plate 48 is a concave portion except the concave portion 4281, the other portions are a flat plate surface. In the case of molding, a flat bottom mold can be used to abut against the flat portion of the second surface 482, and the encapsulant 49 can be filled in the recess 4821, thereby saving a substantial cost without separately manufacturing a special mold. . As shown in FIG. 4D, most of the metal plates 48 are removed by an etching process, leaving only a plurality of connecting posts 44 between the plurality of first contacts 412 and the plurality of second contacts 43. That is, the second surface 482 of the metal plate 48 is selectively etched until the plurality of pads 41 are exposed, and the connection line 413 and the first contact 412 are also exposed. As shown in FIG. 4E, a plurality of solder balls 47 are respectively fixed on the surface of the plurality of pads 411, so that the substrateless chip package 4 has external 1/〇 contacts and can be soldered to other circuit boards. The technical content and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention is not limited by the scope of the invention, and the invention is intended to cover various alternatives and modifications. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1E are schematic diagrams showing a method of manufacturing a substrateless wafer package according to an embodiment of the present invention; FIG. 2 is a substrateless chip package 137400 (2008]000i in FIG. 1D in which a plurality of solder balls have not been fixed. FIG. 3 is a schematic cross-sectional view of a substrateless chip package according to an embodiment of the present invention; and FIGS. 4A to 4E are schematic views showing a method of manufacturing a substrateless wafer package according to another embodiment of the present invention; . [Main component symbol description] 10 substrateless wafer seal |
11 圖案化線路層 111 接墊 112 第一接點 113 連接線 12 晶片 121 主動面 122 銲墊 13 第二接點 14 連接柱 141 通孔 15 黏膠層 16 金屬導線 17 錫球 18 金屬板 181第一表面 1811第一凸部 1812第二表面 1813第二凹部 137400(2008!0001).DOC -13- 20103611311 patterned circuit layer 111 pad 112 first contact 113 connection line 12 wafer 121 active surface 122 solder pad 13 second contact 14 connection post 141 through hole 15 adhesive layer 16 metal wire 17 solder ball 18 metal plate 181 a surface 1811 first protrusion 1812 second surface 1813 second recess 137400 (2008! 0001). DOC -13- 201036113
182 第二表面 1821 第三凹部 19 封裝膠體 40 無基板晶片封裝 41 圖案化線路層 411 接墊 412 第一接點 413 連接線 42 晶片 421 主動面 422 輝墊 43 第二接點 44 連接柱 441 通孔 45 黏膠層 46 金屬導線 47 錫球 48 金屬板 481 第一表面 4812 第二表面 482 第二表面 4821 凹部 49 封裝膠體 I37400(20081000!).DOC -14182 second surface 1821 third recess 19 encapsulant 40 substrateless chip package 41 patterned circuit layer 411 pad 412 first contact 413 connection line 42 wafer 421 active surface 422 glow pad 43 second contact 44 connection column 441 pass Hole 45 Adhesive layer 46 Metal wire 47 Tin ball 48 Metal plate 481 First surface 4812 Second surface 482 Second surface 4821 Recess 49 Encapsulant colloid I37400 (20081000!).DOC -14