JP2551349B2 - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JP2551349B2 JP2551349B2 JP5230783A JP23078393A JP2551349B2 JP 2551349 B2 JP2551349 B2 JP 2551349B2 JP 5230783 A JP5230783 A JP 5230783A JP 23078393 A JP23078393 A JP 23078393A JP 2551349 B2 JP2551349 B2 JP 2551349B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- resin
- semiconductor element
- high thermal
- thermal conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Description
【０００１】[0001]
【産業上の利用分野】本発明は樹脂封止型半導体装置に
関し、特にパッケージの薄型化と低熱抵抗化を図った半
導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device, and more particularly to a semiconductor device having a thin package and low thermal resistance.
【０００２】[0002]
【従来の技術】従来の樹脂封止型半導体装置では、半導
体素子で発生した熱を効率良く外部に放熱してその低熱
抵抗化を図るために、例えば、図４に示す構成が提案さ
れている。この半導体装置は、ヒートスプレッダとして
の高熱伝導板１２の表面中心部に半導体素子１１を搭載
するとともに、その高熱伝導板１２の表面周辺部に外部
リード１４を絶縁材１３を介して取着し、半導体素子１
１の電極パッドと外部リード１４の内側端部とをボンデ
ィングワイヤ１５で電気接続した上で、樹脂１６等によ
り封止したものである。この半導体装置では、半導体素
子１１で発生した熱を高熱伝導板１２に伝達させ、ここ
から樹脂１６を介して放熱することで低熱抵抗化を図っ
ている。例えば、特開昭６１−７７３５０号公報。2. Description of the Related Art In a conventional resin-encapsulated semiconductor device, for example, a structure shown in FIG. 4 has been proposed in order to efficiently dissipate heat generated in a semiconductor element to the outside and reduce its thermal resistance. . In this semiconductor device, a semiconductor element 11 is mounted on the center of the surface of a high thermal conductive plate 12 as a heat spreader, and external leads 14 are attached to the peripheral portion of the surface of the high thermal conductive plate 12 via an insulating material 13, Element 1
The first electrode pad and the inner end of the external lead 14 are electrically connected by a bonding wire 15 and then sealed with a resin 16 or the like. In this semiconductor device, the heat generated in the semiconductor element 11 is transferred to the high thermal conductive plate 12, and is radiated from there through the resin 16 to reduce the thermal resistance. For example, JP-A-61-77350.
【０００３】また、他の構成として、図５に示すよう
に、リードフレーム２４と一体の素子搭載部２２に搭載
した半導体素子２１をワイヤ２５でリードフレーム２４
に接続するとともに、半導体素子２１の表面に放熱ブロ
ック２３を接着し、半導体素子２１で発生した熱をこの
放熱ブロック２３に伝達させ、ここから樹脂２６を通し
て放熱して低熱抵抗化を図ったものもある。例えば、特
開昭６０−１３７０４１号公報。更に、図６に示すよう
に、フィルムキャリア３２を用いて半導体素子３１を搭
載し、このフィルムキャリア３２の表面の金属箔３３を
介して外部導出リード３４に電気接続し、樹脂３６で封
止する。また、フィルムキャリア３２の裏面に金属箔３
５を形成し、この金属箔３５を放熱手段とした構成もあ
る。例えば、特開平２−９２７４４号公報。As another structure, as shown in FIG. 5, the semiconductor element 21 mounted on the element mounting portion 22 integrated with the lead frame 24 is connected to the lead frame 24 by a wire 25.
In addition, the heat dissipation block 23 is bonded to the surface of the semiconductor element 21 and the heat generated in the semiconductor element 21 is transmitted to the heat dissipation block 23, and the resin 26 is radiated from there to reduce the thermal resistance. is there. For example, JP-A-60-137041. Further, as shown in FIG. 6, the semiconductor element 31 is mounted using the film carrier 32, electrically connected to the external lead 34 through the metal foil 33 on the surface of the film carrier 32, and sealed with the resin 36. . In addition, the metal foil 3 is provided on the back surface of the film carrier 32.
5 is formed, and the metal foil 35 is used as a heat radiating means. For example, Japanese Patent Laid-Open No. 2-92744.
【０００４】[0004]
【発明が解決しようとする課題】これら従来の樹脂封止
型半導体装置では、半導体素子に直接的に放熱手段を接
触させることで、半導体素子の熱を放熱手段に伝導さ
せ、ここから放熱を行うために放熱効果を高めることが
できる。しかしながら、図４及び図５の半導体装置で
は、半導体素子の両面側或いは裏面側に重ねて放熱手段
を設けるとともに、半導体素子とリードフレームとをワ
イヤ接続しているため、このワイヤのループ高さと放熱
手段の高さが半導体素子の厚さ寸法に加えられることに
なるため、半導体装置の高さ寸法が大きくなり、半導体
装置の薄型化を図ることが難しいという問題がある。In these conventional resin-encapsulated semiconductor devices, the heat of the semiconductor element is conducted to the heat radiating means by directly contacting the heat radiating means with the semiconductor element, and the heat is radiated from there. Therefore, the heat dissipation effect can be enhanced. However, in the semiconductor device of FIGS. 4 and 5, since the heat dissipation means is provided on both sides or the back side of the semiconductor element in a stacked manner and the semiconductor element and the lead frame are connected by wire, the loop height of this wire and the heat dissipation are increased. Since the height of the means is added to the thickness dimension of the semiconductor element, the height dimension of the semiconductor device becomes large and it is difficult to reduce the thickness of the semiconductor device.
【０００５】この点、図６の構成では、フィルムキャリ
ア方式を用いているため、ワイヤが不要となり、かつ放
熱手段も薄くできるため、半導体装置の薄型化には有効
であるが、放熱手段が金属箔であるために図４及び図５
に示したものよりも低熱抵抗効果が劣ることは避けられ
ず、またフィルムキャリア方式によるボンディングは、
現状ではワイヤボンディング方式に比べて歩留が低く、
しかもテープ等の資材費が高いことによる製造コスト高
になり易いという問題がある。本発明の目的は、低熱抵
抗化を高めると共に、薄型化を図った半導体装置を提供
することにある。In this respect, in the structure of FIG. 6, since the film carrier system is used, the wire is not necessary and the heat radiating means can be made thin, which is effective for thinning the semiconductor device, but the heat radiating means is made of metal. 4 and 5 because it is a foil
It is unavoidable that the low thermal resistance effect is inferior to that shown in, and bonding by the film carrier method is
At present, the yield is lower than that of the wire bonding method,
Moreover, there is a problem that the manufacturing cost tends to increase due to the high cost of materials such as tape. It is an object of the present invention to provide a semiconductor device which has a reduced thermal resistance and a reduced thickness.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体装置は、
半導体素子の表面の電極パッドを除く領域に高熱伝導板
の一部を接着し、かつこの高熱伝導板の他の一部には前
記半導体素子が接着された側と同じ面に外部導出リード
を接着し、前記電極パッドと外部導出リードの接着面側
の一部とをワイヤで電気接続した構成とする。高熱伝導
板と半導体素子及び外部導出リードとは、両面にエポキ
シ系接着剤を有するポリイミドにより接着してもよい。
また、高熱伝導板は、半導体素子の電極パッドの配列領
域よりも小さい外形寸法の中心部と、外部導出リードの
内側端部を結ぶ線よりも大きい内形寸法の枠状の周辺部
と、これらを連結する吊り部とで構成されており、中心
部の外側に露呈された電極パッドと、周辺部の内側に露
呈される外部導出リードの内側端部とをワイヤで接続す
る構成とする。更に、半導体素子の裏面を封止樹脂から
露呈させてもよい。According to the present invention, there is provided a semiconductor device comprising:
High thermal conductive plate in the area of the semiconductor element surface excluding the electrode pads
Part of the high thermal conductive plate
External lead-out lead on the same surface as the side where the semiconductor element is bonded
Is bonded, and the electrode pad and part of the bonding surface side of the external lead are electrically connected by a wire. The high thermal conductive plate, the semiconductor element, and the external leads may be bonded to each other with polyimide having an epoxy adhesive.
Further, the high thermal conductive plate includes a central portion having an outer dimension smaller than the array area of the electrode pads of the semiconductor element, and a frame-shaped peripheral portion having an inner dimension larger than a line connecting the inner end portions of the external lead-outs. The electrode pad exposed to the outside of the central portion and the inner end of the external lead lead exposed to the inside of the peripheral portion are connected by a wire. Furthermore, the back surface of the semiconductor element may be exposed from the sealing resin.
【０００７】[0007]
【実施例】次に、本発明について図面を参照して説明す
る。図１（ａ），（ｂ）はそれぞれ本発明の実施例１の
一部破断平面図及びそのＡ−Ａ線断面図である。半導体
素子１は電極パッド１ａを有する表面を上方に向けてお
り、この電極パッド１を除く表面にポリイミド３ａを介
して０．１〜０．２ｍｍ厚程度のＣｕアロイ板等からな
る高熱伝導板（ヒートスプレッダ）２の中心部２ａを接
着してある。また、この高熱伝導板２の周辺部２ａには
ポリイミド３ｂを介して０．１〜０．２ｍｍ厚程度の金
属板からなる外部導出リード４を接着してある。前記高
熱伝導板２は、前記中心部２ａの形状寸法は半導体素子
１の周辺部に配置した電極パッド１ａの配列領域よりも
小さい寸法とされ、その四隅において吊り部２ｃにより
方形枠状の周辺部２ｂと一体的に連結されており、ま
た、その周辺部２ｂは外部導出リード４の内側端部４ａ
を結ぶ領域よりも大きな内形寸法としている。なお、前
記ポリイミド３ａ，３ｂの厚さは５０〜１００μｍ厚程
度とされる。そして、前記半導体素子１の電極パッド１
ａと、外部導出リード４の内側端部４ａの接着面側とを
ボンディングワイヤ５にて電気接続を行い、かつこれら
をエポキシ樹脂６により樹脂封止した構成とされてい
る。Next, the present invention will be described with reference to the drawings. 1A and 1B are a partially cutaway plan view and a cross-sectional view taken along the line AA of Embodiment 1 of the present invention, respectively. The semiconductor element 1 has a surface having the electrode pad 1a directed upward, and a high thermal conductive plate (Cu alloy plate or the like) having a thickness of about 0.1 to 0.2 mm is formed on the surface excluding the electrode pad 1 via the polyimide 3a ( The central portion 2a of the heat spreader 2 is adhered. Further, an external lead 4 made of a metal plate having a thickness of about 0.1 to 0.2 mm is bonded to the peripheral portion 2a of the high thermal conductive plate 2 via a polyimide 3b. In the high thermal conductive plate 2, the shape and size of the central portion 2a is smaller than the arrangement area of the electrode pads 1a arranged in the peripheral portion of the semiconductor element 1, and the rectangular frame-shaped peripheral portion is formed by the hanging portions 2c at the four corners. 2b, and its peripheral portion 2b is an inner end 4a of the external lead-out lead 4.
The internal dimension is larger than the area connecting the two. The thickness of the polyimides 3a and 3b is about 50 to 100 μm. Then, the electrode pad 1 of the semiconductor element 1
a and the bonding surface side of the inner end portion 4a of the external lead 4 are electrically connected by a bonding wire 5, and these are resin-sealed with an epoxy resin 6.
【０００８】図２は図１の半導体装置の製造方法を工程
順に示す図である。先ず、図２（ａ）のように、リード
フレームの外部導出リード４の一部に両面にエポキシ系
の接着剤を塗布したポリイミド３ｂを介して高熱伝導板
２の周辺部２ｂを接続する。このとき、外部導出リード
４の内側先端部４ａはポリイミド３ｂ及び高熱伝導板２
の周辺部２ｂの内側に露呈される。次いで、図（ｂ）の
ように、表面にポリイミドコーティングが施された半導
体装素子１の表面に、両面にエポキシ系接着剤を塗布し
たポリイミド３ａを介して前記高熱伝導板２の中心部２
ａを接着する。このとき、半導体素子１の表面の周辺部
に配置されている電極パッド１ａはポリイミド３ａ及び
高熱伝導板２の中心部２ａの周囲に露呈される。2A to 2D are views showing a method of manufacturing the semiconductor device of FIG. First, as shown in FIG. 2A, the peripheral portion 2b of the high thermal conductive plate 2 is connected to a part of the lead-out lead 4 of the lead frame via the polyimide 3b whose both surfaces are coated with an epoxy adhesive. At this time, the inner tip portion 4a of the external lead 4 has the polyimide 3b and the high thermal conductive plate 2.
Is exposed inside the peripheral portion 2b. Next, as shown in FIG. 2B, the central portion 2 of the high thermal conductive plate 2 is formed on the surface of the semiconductor device 1 having a polyimide coating on the surface thereof via the polyimide 3a having epoxy adhesives on both surfaces.
Adhere a. At this time, the electrode pads 1a arranged on the peripheral portion of the surface of the semiconductor element 1 are exposed around the polyimide 3a and the central portion 2a of the high thermal conductive plate 2.
【０００９】しかる後、図２（ｃ）のように、露呈され
ている電極パッド１ａと前記外部導出リード４の内側先
端部４ａとをボンディングワイヤ５にて相互に電気接続
する。このとき、ボンディングワイヤ５には上向きのル
ープが生じる。その後、図２（ｄ）のように、トランス
ファーモールド法等によりエポキシ樹脂６により樹脂封
止をする。その上で、図示は省略するが外部導出リード
４の外側端部の切断及び成形を行って所要のリード形状
の半導体装置を得る。After that, as shown in FIG. 2C, the exposed electrode pad 1a and the inner tip 4a of the external lead 4 are electrically connected to each other by a bonding wire 5. At this time, an upward loop is generated in the bonding wire 5. After that, as shown in FIG. 2D, resin molding is performed with an epoxy resin 6 by a transfer molding method or the like. Then, although not shown in the drawing, the outer end portion of the external lead 4 is cut and molded to obtain a semiconductor device having a desired lead shape.
【００１０】このように構成した半導体装置では、半導
体素子１の動作時に発生する熱は、ポリイミド３ａを介
して高熱伝導板２へ伝達され、ここから樹脂６を介して
放散される。また、他の一部は半導体素子１の裏面から
樹脂６へと効率的に放散される。これにより、低熱抵抗
化を改善することが可能となる。また、ボンディングワ
イヤ５に生じるループの高さ寸法相当分の大部分を、高
熱伝導板２とポリイミド３ａの厚さと相殺することがで
きる。また半導体素子１の厚さも外部導出リード４の厚
さとその一部が相殺できる。これにより、半導体素子１
とボンディングワイヤ５にそれぞれ必要とされる高さ寸
法を従来よりも低減でき、半導体装置の薄型化が可能と
なる。In the semiconductor device configured as described above, the heat generated during the operation of the semiconductor element 1 is transferred to the high thermal conductive plate 2 via the polyimide 3a, and is radiated from there through the resin 6. The other part is efficiently diffused from the back surface of the semiconductor element 1 to the resin 6. This makes it possible to improve the low thermal resistance. Further, most of the loop corresponding to the height dimension of the bonding wire 5 can be offset by the thicknesses of the high thermal conductive plate 2 and the polyimide 3a. Further, the thickness of the semiconductor element 1 can be offset by the thickness of the external lead 4 and a part thereof. Thereby, the semiconductor element 1
Also, the height required for the bonding wire 5 and the height required for the bonding wire 5 can be reduced as compared with the conventional case, and the semiconductor device can be thinned.
【００１１】図３（ａ），（ｂ）はそれぞれ本発明の実
施例２の一部破断平面図及びそのＢ−Ｂ線断面図であ
る。この実施例では半導体素子１をポリイミド３ａによ
り高熱伝導板２に接着し、かつポリイミド３ｂにより外
部導出リード４を接着し、ワイヤボンディングを行って
樹脂６で封止している点は実施例１と同じである。そし
て、この実施例２では、半導体素子１の裏面を樹脂６の
裏面から外部に直接露出させた構成がとられている。こ
れにより、少なくとも半導体素子１の裏面側の封止樹脂
６の厚さだけ半導体装置全体を更に薄くすることが可能
となる。例えば、半導体素子１の厚さを２００μｍ程度
にすれば、半導体装置全体の厚さを０．５ｍｍ以下にす
ることが可能となる。また、半導体素子１の裏面が露出
していることにより、この面からの熱放散もより効率的
になり、低熱抵抗化が可能となる。因に、空冷等による
強制冷却時には３〜５Ｗの消費電力を有する半導体素子
にも対応可能となる。FIGS. 3 (a) and 3 (b) are a partially cutaway plan view and a sectional view taken along line BB of Example 2 of the present invention, respectively. In this embodiment, the semiconductor element 1 is adhered to the high thermal conductive plate 2 with the polyimide 3a, the external lead 4 is adhered with the polyimide 3b, and wire bonding is performed to seal the resin 6 with the embodiment 1. Is the same. In the second embodiment, the back surface of the semiconductor element 1 is directly exposed from the back surface of the resin 6 to the outside. As a result, the entire semiconductor device can be further thinned by at least the thickness of the sealing resin 6 on the back surface side of the semiconductor element 1. For example, if the thickness of the semiconductor element 1 is about 200 μm, the thickness of the entire semiconductor device can be 0.5 mm or less. In addition, since the back surface of the semiconductor element 1 is exposed, heat can be more efficiently dissipated from this surface, and low thermal resistance can be achieved. Incidentally, it becomes possible to cope with a semiconductor element having a power consumption of 3 to 5 W during forced cooling by air cooling or the like.
【００１２】ここで、高熱伝導板の材料や、高熱伝導板
に半導体素子や外部導出リードを接着するための絶縁材
料、更に封止樹脂材料等は前記実施例のものに限られ
ず、種々の材料が適用できることは言うまでもない。ま
た、ワイヤのループ高さが高熱伝導板の上面から突出さ
れない場合には、高熱伝導板の上面を樹脂から露出させ
ることもでき、放熱効率を更に高めることが可能とな
る。Here, the material of the high thermal conductive plate, the insulating material for adhering the semiconductor element or the external lead to the high thermal conductive plate, the sealing resin material, etc. are not limited to those in the above-mentioned embodiment, and various materials can be used. Needless to say, can be applied. Also, when the loop height of the wire does not protrude from the upper surface of the high thermal conductive plate, the upper surface of the high thermal conductive plate can be exposed from the resin, and the heat dissipation efficiency can be further enhanced.
【００１３】[0013]
【発明の効果】以上説明したように本発明は、高熱伝導
板の一方の面に半導体素子と外部導出リードとをそれぞ
れ接着し、かつ電極パッドと外部導出リードの接着面側
の一部とをワイヤで電気接続しているので、高熱伝導板
によって半導体素子で発生された熱を高い効率で放熱で
き、低熱抵抗化を図ることができるとともに、ワイヤの
ループ高さを高熱伝導板の厚さ分だけ相殺でき、半導体
装置の薄型化を図ることができる。。また、半導体素子
の裏面を封止樹脂から露呈させることで、裏面側の樹脂
の厚さ分薄型化を促進でき、かつ半導体素子の裏面から
の直接放熱を可能にして低熱抵抗化も促進できる。As described above, according to the present invention, the semiconductor element and the external lead are bonded to one surface of the high thermal conductive plate, and the electrode pad and a part of the bonded surface of the external lead are bonded to each other. Since they are electrically connected by wires, the heat generated by the semiconductor element can be dissipated with high efficiency by the high thermal conductive plate, and low thermal resistance can be achieved, and the loop height of the wire can be made equal to the thickness of the high thermal conductive plate. Therefore, the semiconductor device can be thinned. . Further, by exposing the back surface of the semiconductor element from the sealing resin, it is possible to promote the reduction in thickness by the thickness of the resin on the back surface side, and it is also possible to directly radiate heat from the back surface of the semiconductor element to promote low thermal resistance.
【図１】本発明の実施例１を示し、（ａ）は一部破断平
面図、（ｂ）はそのＡ−Ａ線断面図である。1A and 1B show a first embodiment of the present invention, in which FIG. 1A is a partially cutaway plan view and FIG. 1B is a sectional view taken along line AA.
【図２】実施例１の製造方法を工程順に示す要部の断面
図である。FIG. 2 is a cross-sectional view of a main part showing the manufacturing method of Example 1 in process order.
【図３】本発明の実施例２を示し、（ａ）は一部破断平
面図、（ｂ）はそのＢ−Ｂ線断面図である。3A and 3B show a second embodiment of the present invention, in which FIG. 3A is a partially cutaway plan view, and FIG.
【図４】従来の半導体装置の一例を示す断面図である。FIG. 4 is a sectional view showing an example of a conventional semiconductor device.
【図５】従来の半導体装置の他の例を示す断面図であ
る。FIG. 5 is a cross-sectional view showing another example of a conventional semiconductor device.
【図６】従来の半導体装置の更に他の例を示す断面図で
ある。FIG. 6 is a sectional view showing still another example of a conventional semiconductor device.
１ 半導体素子 ２ 高熱伝導板 ３ ポリイミド ４ 外部導出リード ５ ボンディングワイヤ ６ 樹脂 1 Semiconductor Element 2 High Thermal Conductive Plate 3 Polyimide 4 External Lead 5 Bonding Wire 6 Resin
Claims (4)
子の前記表面の電極パッドを除く領域に高熱伝導板の一
部を接着し、かつこの高熱伝導板の他の一部には前記半
導体素子が接着された側と同じ面に外部導出リードを接
着し、前記電極パッドと外部導出リードの接着面側の一
部とをワイヤで電気接続したことを特徴とする樹脂封止
型半導体装置。1. A semiconductor device having an electrode pad formed on the surface thereof.
In the area of the surface of the child excluding the electrode pads, one of the high thermal conductive plates is
Part of the high thermal conductive plate
Connect the external lead to the same surface as the side to which the conductor element is bonded.
The resin-encapsulated semiconductor device , wherein the electrode pad and a part of the external lead-out lead on the bonding surface side are electrically connected by a wire.
ードとは、両面にエポキシ系接着剤を有するポリイミド
により接着されてなる請求項１の樹脂封止型半導体装
置。2. The resin-encapsulated semiconductor device according to claim 1, wherein the high thermal conductive plate, the semiconductor element and the external lead-out are bonded to each other with polyimide having an epoxy adhesive.
の配列領域よりも小さい外形寸法の中心部と、外部導出
リードの内側端部を結ぶ線よりも大きい内形寸法の枠状
の周辺部と、これらを連結する吊り部とで構成され、前
記中心部の外側に露呈された電極パッドと、前記周辺部
の内側に露呈される外部導出リードの内側端部とをワイ
ヤで接続してなる請求項１又は２の樹脂封止型半導体装
置。3. The high thermal conductive plate is a frame-shaped peripheral portion having an inner size larger than a line connecting a center portion of an outer dimension smaller than an array region of electrode pads of a semiconductor element and an inner end portion of an external lead-out lead. And a suspending part connecting them, and connecting the electrode pad exposed outside the central part and the inner end part of the external lead lead exposed inside the peripheral part with a wire. The resin-encapsulated semiconductor device according to claim 1.
せてなる請求項１乃至３のいずれかの樹脂封止型半導体
装置。4. The resin-encapsulated semiconductor device according to claim 1, wherein the back surface of the semiconductor element is exposed from the encapsulating resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5230783A JP2551349B2 (en) | 1993-08-25 | 1993-08-25 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5230783A JP2551349B2 (en) | 1993-08-25 | 1993-08-25 | Resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0766323A JPH0766323A (en) | 1995-03-10 |
| JP2551349B2 true JP2551349B2 (en) | 1996-11-06 |
Family
ID=16913203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5230783A Expired - Fee Related JP2551349B2 (en) | 1993-08-25 | 1993-08-25 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2551349B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4246598B2 (en) * | 2003-10-22 | 2009-04-02 | 三菱電機株式会社 | Power semiconductor device |
| US8304871B2 (en) * | 2011-04-05 | 2012-11-06 | Texas Instruments Incorporated | Exposed die package for direct surface mounting |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60130649U (en) * | 1984-02-10 | 1985-09-02 | 関西日本電気株式会社 | Resin-encapsulated semiconductor device |
| JP2905609B2 (en) * | 1991-02-05 | 1999-06-14 | 三菱電機株式会社 | Resin-sealed semiconductor device |
-
1993
- 1993-08-25 JP JP5230783A patent/JP2551349B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0766323A (en) | 1995-03-10 |
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