JPS6193654A - Resin sealed type semiconductor device - Google Patents

Resin sealed type semiconductor device

Info

Publication number
JPS6193654A
JPS6193654A JP59214191A JP21419184A JPS6193654A JP S6193654 A JPS6193654 A JP S6193654A JP 59214191 A JP59214191 A JP 59214191A JP 21419184 A JP21419184 A JP 21419184A JP S6193654 A JPS6193654 A JP S6193654A
Authority
JP
Japan
Prior art keywords
solder
semiconductor element
section
mounting
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59214191A
Other languages
Japanese (ja)
Inventor
Yoshimasa Kudo
工藤　好正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59214191A priority Critical patent/JPS6193654A/en
Publication of JPS6193654A publication Critical patent/JPS6193654A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To stop the flow of solder on mounting at a predetermined position, and to improve the defective bonding of ground bonding by forming a plating non-attaching section between a mounting section for a metallic substrate and a ground bonding section. CONSTITUTION:Gold or silver is plated 5a so that a semiconductor element 4 can be joined with a mounting section for the semiconductor element 4 on a metallic substrate 2 consisting of a copper material positively and stably through solder 6, and gold or silver is plated 5b so that ground bonding is conducted excellently. An isolation zone 10 is formed so that a section between both plating sections is made discontinuous at that time. The flowing of solder extending due to scrubbing, etc. on mounting is stopped by a plating non- attaching section, thus eliminating defective ground bonding resulting from the flowing of solder.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は樹脂封止型半導体装置、特に放熱部を備えた小
型、薄型パワーＩＣに関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a resin-sealed semiconductor device, and particularly to a small, thin power IC equipped with a heat dissipation section.

〔発明の技術的背景〕[Technical background of the invention]

従来、パワーＩＣには放熱部が設けられており、例えば
第７図（斜視図）、第８図（側面図）及び第９図Ｃ部分
拡大図）に示すように樹脂製外囲器（１）と、この外囲
器（１）内を貫通し側方乃至下方に折れ曲って突出した
金属基板（２）とリード（３）とを有するパワーＩＣ例
である。この金属元板（２）は熱伝導度の良い銅系材料
からなり、その中央部に形成された半田のぬれをよくす
る表面めっき部（５）上に半田（６）付けされた半導体
素子（４）の発熱を外部に放熱するためのものである。Conventionally, a power IC has been provided with a heat dissipation section, and for example, as shown in FIG. 7 (perspective view), FIG. 8 (side view), and FIG. ), a metal substrate (2) and leads (3) that penetrate through the envelope (1) and protrude sideways or downwardly by bending. This metal base plate (2) is made of a copper-based material with good thermal conductivity, and the semiconductor element (6) is soldered on a surface plating part (5) formed in the center of the plate to improve solder wetting. This is to radiate the heat generated in step 4) to the outside.

また、半導体素子（４）の回路を動作させるためにその
回路から複数の内部リードにワイヤボンディングすると
共にパワーＩＣがもつ高出力特性安定のために金属基板
（２）にグランドボンディング（７）が施される。また
、素子材料と金属基板（２）の銅系材料とは熱膨張率が
７倍近く違うため、マウント材としては、共晶合金（）
ｌａｒｄ　５ｏｌｄｅｒ）や樹脂接着剤では、素子のク
ラックの原因となること及び熱伝導性の上から半田（Ｓ
ｏｆｔ　５ｏｌｄｅｒ）材（６）が使用される。In addition, in order to operate the circuit of the semiconductor element (4), wire bonding is performed from the circuit to a plurality of internal leads, and ground bonding (7) is performed to the metal substrate (2) to stabilize the high output characteristics of the power IC. be done. In addition, since the thermal expansion coefficients of the element material and the copper-based material of the metal substrate (2) are approximately 7 times different, the eutectic alloy (2) is used as the mounting material.
lard 5 older) or resin adhesives may cause cracks in the element, and solder (S
of 5older) material (6) is used.

〔背景技術の問題点〕[Problems with background technology]

従来、金属基板（２）にグランドボンディング（７）を
行う場合、第８図、第９図に示すようにマウント材の半
田（６）がマウン時のスクラブにより素子（４）の周辺
にはみ出し、ボンディング位置（７Ａ）まで流れ、ボン
ディング不良をひきおこす問題があった。その改善の為
にマウント部とボンディング位置との間に刻印（数条の
溝を設ける）を施し、半田の流れを止める方法が取られ
た。また刻印のかわりに貫通穴（長穴や丸穴）を施す場
合もあった。Conventionally, when performing ground bonding (7) on a metal substrate (2), the solder (6) of the mounting material protrudes around the element (4) due to scrubbing during mounting, as shown in FIGS. 8 and 9. There was a problem that the liquid flowed to the bonding position (7A) and caused bonding defects. In order to improve this problem, a method was adopted in which a stamp (several grooves were provided) between the mount part and the bonding position was used to stop the flow of solder. There were also cases where a through hole (elongated hole or round hole) was made instead of a stamp.

しかし最近、ＩＣを組込まれる機器の小型化に伴ない、
パワーＩＣの分野でもパッケージの超小型化、薄型化が
要求されている。そのため、リード、金属基板を含め板
厚を薄くすることが必要条件となってきた。それ故、前
記の刻印の方法では板厚が薄いため刻印を深くできず、
半田の流れを止める効果が少ない欠点があった。また無
理に深くした場合は薄板のために金属基板に変形が生じ
る問題があった。貫通穴の場合は薄板化になっても加工
上問題はないが小型化と放熱効果を考えると穴を明ける
スペースが得難く半田流れを完全に止めることは不可能
であった。However, recently, with the miniaturization of devices into which ICs are incorporated,
In the field of power ICs, there is also a demand for ultra-small and thin packages. Therefore, it has become necessary to reduce the thickness of the boards, including the leads and metal substrates. Therefore, with the above marking method, it is not possible to make deep markings because the board is thin.
The drawback was that it was less effective in stopping the flow of solder. In addition, if the depth is forced, there is a problem that the metal substrate may be deformed because it is a thin plate. In the case of through-holes, there is no problem in processing even if the plate is made thinner, but considering miniaturization and heat dissipation effects, it is difficult to find space for holes and it is impossible to completely stop solder flow.

金属基板構造パッケージの放熱性を理論計算で説明する
と次の通りとなる。熱抵抗をＲｔｈ、λを熱が通過する
物体の熱伝導率、Ａを熱が通過する物体の断面積、Ｑを
熱が通過する距離とすると熱抵抗Ｒｔｈは、Ｒｔｈ＝　
”で表わされる。そしてλＡ 熱抵抗（Ｒｔｈ）が大きくなれば放熱性は悪くなる。The heat dissipation performance of the metal substrate structure package is explained as follows using theoretical calculations. Thermal resistance Rth is Rth=
”.The larger the λA thermal resistance (Rth), the worse the heat dissipation.

板厚を薄くすることは断面積を小にすることになり放熱
効果が悪くなる。貫通穴を明けることはもちろん、刻印
を入れることも部分的に断面が小になり、パワーＩＣの
小型化につれて熱抵抗が大きくなり放熱効果は悪くなり
好ましくない。Reducing the plate thickness reduces the cross-sectional area, which deteriorates the heat dissipation effect. Not only through-holes but also markings are not desirable because the cross-section becomes smaller in some parts, and as the power IC becomes smaller, the thermal resistance increases and the heat dissipation effect deteriorates.

〔発明の目的〕[Purpose of the invention]

本発明は小型パワーＩ　Ｃ（Ｓｍａｉｌ　Ｏｕｔ−１ｉ
ｎｅＰａｃｋａｇｅ、　Ｐｏｗｅｒ　Ｆｌａｔ　Ｐａｃ
ｋａｇｅ）の放熱効果を下げることなく、マウント時の
半田流れを所定の場所で止めグランドボンディングのボ
ンディング不良を改善することを目時とする。The present invention is a compact power IC (Smail Out-1i).
nePackage, Power Flat Pack
The aim is to stop the flow of solder at a predetermined location during mounting and improve bonding defects in ground bonding without reducing the heat dissipation effect of the cage.

〔発明の概要〕[Summary of the invention]

本発明は金属基板のマウント部とグランドボンディング
部との間にめっき不着部を形成し、半田に対する銅素子
面とめっき上面の半田のぬれ性の違いを利用しマウント
時の半田の流れをめっき不着部で止めるようにして前記
改善の目的を達成したものである。The present invention forms a non-plated part between the mounting part of the metal substrate and the ground bonding part, and utilizes the difference in the wettability of the solder between the copper element surface and the top surface of the plating to control the flow of solder during mounting. The purpose of the improvement described above was achieved by stopping at the end.

〔発明の実施例〕[Embodiments of the invention]

第１図は本発明の一実施例の要部を示す平面図、第２図
はその側面図、第３図は第２図の一部の拡大図で、第４
図は全貌を示す斜視図である。また第５図は本発明の他
の実施例の全貌を示す斜視図。FIG. 1 is a plan view showing essential parts of an embodiment of the present invention, FIG. 2 is a side view thereof, FIG. 3 is an enlarged view of a part of FIG. 2, and FIG.
The figure is a perspective view showing the whole picture. Moreover, FIG. 5 is a perspective view showing the whole picture of another embodiment of the present invention.

第６図は第５図の内部構造を示す平面図である。FIG. 6 is a plan view showing the internal structure of FIG. 5.

これらの図においては第７図乃至第９図と同一部分には
同一番号を付は類似部分には添字を付加して示しである
。In these figures, the same parts as in FIGS. 7 to 9 are given the same numbers, and similar parts are given suffixes.

第１図乃至第４図、第５図、第６図に示す実施例におけ
る特徴は、鋼材からなる金属基板（２）上の半導体素子
（４）のマウント部に、半田（６）を介して半導体素子
（４）が確実且つ安定した接合が可能になるように金又
は銀めっき（５ａ）を、またグランドボンディングが良
好に行なえるように金又は銀のめっき（５ｂ）を行うが
、その際、両めっき部間が不連続になるように分離帯（
めっき不着部）（１０）が形成される。こけ分離帯はめ
っき用マスクを加工して、リードフレームめっき作業中
にリードフレーム加工の一貫作業として作ることができ
、リードフレームを低コストで量産的に供給できる。そ
の他、工程数は増えるが金属基板上面全体にめっきをし
てから分離帯を化学的に除去して形成する方法もある。The features of the embodiments shown in FIGS. 1 to 4, 5, and 6 are that the mounting portion of the semiconductor element (4) on the metal substrate (2) made of steel is bonded to the mounting portion of the semiconductor element (4) through solder (6). Gold or silver plating (5a) is performed to enable reliable and stable bonding of the semiconductor element (4), and gold or silver plating (5b) is performed to ensure good ground bonding. , a separation band (
A non-plated portion (10) is formed. The moss separation zone can be made by processing a plating mask as part of the lead frame processing process during the lead frame plating process, and lead frames can be mass-produced at low cost. Another method, which increases the number of steps, is to plate the entire top surface of the metal substrate and then chemically remove the separation band.

〔発明の効果〕〔Effect of the invention〕

本発明は以上のようになるものであって、ｉ）マウン部
とグランドホンディング部との間に設けためっき不着部
により、マウント時のスクラブ等で広がった半田の流れ
がめつき不着部で止まるので、それに原因するグランド
ボンディング不良をなくすことができる。ｉｉ）パワー
ＩＣの必要条件である放熱性に対し、前記従来技術で述
べた問題点の軽減により小型化、薄型化パワーＩＣの供
給が可能となる。ｉｕ）金属基板構造のパワーＩＣは従
来から樹脂と金属基板の接触部から水が浸入し易く、耐
湿性の劣化を招くという問題があったが。The present invention is as described above, and has the following features: i) The non-plated portion provided between the mounting portion and the ground bonding portion prevents the flow of solder that spreads due to scrubbing during mounting to stop at the non-plated portion. Therefore, ground bonding defects caused by this can be eliminated. ii) With regard to heat dissipation, which is a necessary condition for power ICs, by alleviating the problems described in the prior art, it becomes possible to supply smaller and thinner power ICs. iu) Power ICs having a metal substrate structure have conventionally had the problem that water easily enters through the contact portion between the resin and the metal substrate, resulting in deterioration of moisture resistance.

前記のめっき不着部（銅の素材面）がマウントボンディ
ング工程等の加熱で酸化され酸化銅となり。The unplated area (copper material surface) is oxidized by heating during the mount bonding process and becomes copper oxide.

この酸化鋼と樹脂材との密着性が良好なため耐湿性の向
上も得られる。等の効果がある。Since the adhesion between the oxidized steel and the resin material is good, moisture resistance can also be improved. There are other effects.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例を示す平面図、第２図は第１
図の側面図、第３図は第２図の一部の拡大図、第４図は
装置の全貌を示す斜視図、第５図は本発明の他の実施例
の全貌を示す斜視図、第６図は第５図の内部構造を示す
平面図、第７図乃至第９図は従来例を示し、第７図は斜
視図、第８図は側面図、第９図は部分拡大図である。 １：樹脂製外囲器、２：金属基板、３：外部リード、４
：半導体素子、５．５ａ、　５ｂ、　５ｃ：めっき部。 ６：半田、７，７ａ：ワイヤーボンディング、９：内部
リード、１０：めっき不着部。Fig. 1 is a plan view showing one embodiment of the present invention, and Fig. 2 is a plan view showing an embodiment of the present invention.
3 is an enlarged view of a part of FIG. 2, FIG. 4 is a perspective view showing the overall appearance of the device, and FIG. 5 is a perspective view showing the overall appearance of another embodiment of the present invention. Fig. 6 is a plan view showing the internal structure of Fig. 5, Figs. 7 to 9 show conventional examples, Fig. 7 is a perspective view, Fig. 8 is a side view, and Fig. 9 is a partially enlarged view. . 1: Resin envelope, 2: Metal substrate, 3: External lead, 4
: Semiconductor element, 5.5a, 5b, 5c: Plating part. 6: solder, 7, 7a: wire bonding, 9: internal lead, 10: non-plated area.

Claims (1)

【特許請求の範囲】[Claims] 　半導体素子を固着するマウント部と放熱部および両者
を連結する伝熱部とを有する金属基板と、この金属基板
の前記マウント部およびそのマウント部と所定の間隔離
間した前記伝熱部に設けられためっき層と、前記マウン
ト部に前記めっき層を介して半田で固着された半導体素
子と、この半導体素子の電極に接続された複数のリード
と、前記半導体素子の電極と前記伝熱部のめっき層に接
続された導電性細線と、前記金属基板のマウント部、伝
熱部、半導体素子、導電性細線および複数のリードの前
記電極に接続された端部を封止する樹脂製外囲器とを具
備することを特徴とする樹脂封止型半導体装置。a metal substrate having a mount portion for fixing a semiconductor element, a heat radiation portion, and a heat transfer portion for connecting the two; a plating layer, a semiconductor element fixed to the mount part with solder via the plating layer, a plurality of leads connected to electrodes of the semiconductor element, and a plating layer of the electrode of the semiconductor element and the heat transfer part. a resin envelope that seals the conductive thin wire connected to the metal substrate, the heat transfer portion, the semiconductor element, the conductive thin wire, and the ends of the plurality of leads connected to the electrode. A resin-sealed semiconductor device comprising:
JP59214191A 1984-10-15 1984-10-15 Resin sealed type semiconductor device Pending JPS6193654A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59214191A JPS6193654A (en) 1984-10-15 1984-10-15 Resin sealed type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59214191A JPS6193654A (en) 1984-10-15 1984-10-15 Resin sealed type semiconductor device

Publications (1)

Publication Number Publication Date
JPS6193654A true JPS6193654A (en) 1986-05-12

Family

ID=16651746

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59214191A Pending JPS6193654A (en) 1984-10-15 1984-10-15 Resin sealed type semiconductor device

Country Status (1)

Country Link
JP (1) JPS6193654A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006005281A (en) * 2004-06-21 2006-01-05 Nippon Inter Electronics Corp Lead frame, manufacturing method thereof, and resin-sealed semiconductor device
JP2011014713A (en) * 2009-07-02 2011-01-20 Mitsubishi Electric Corp Semiconductor device
US8398512B2 (en) 2007-04-30 2013-03-19 Miba Sinter Austria Gmbh Toothed belt pulley

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS553641A (en) * 1978-06-23 1980-01-11 Hitachi Ltd Lead frame

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS553641A (en) * 1978-06-23 1980-01-11 Hitachi Ltd Lead frame

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006005281A (en) * 2004-06-21 2006-01-05 Nippon Inter Electronics Corp Lead frame, manufacturing method thereof, and resin-sealed semiconductor device
JP4537774B2 (en) * 2004-06-21 2010-09-08 日本インター株式会社 Lead frame manufacturing method
US8398512B2 (en) 2007-04-30 2013-03-19 Miba Sinter Austria Gmbh Toothed belt pulley
JP2011014713A (en) * 2009-07-02 2011-01-20 Mitsubishi Electric Corp Semiconductor device

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