JP2506429B2 - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JP2506429B2 JP2506429B2 JP1026218A JP2621889A JP2506429B2 JP 2506429 B2 JP2506429 B2 JP 2506429B2 JP 1026218 A JP1026218 A JP 1026218A JP 2621889 A JP2621889 A JP 2621889A JP 2506429 B2 JP2506429 B2 JP 2506429B2
- Authority
- JP
- Japan
- Prior art keywords
- stage
- resin
- lead frame
- semiconductor device
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔概要〕 樹脂封止型半導体装置に関し、 プリント基板等外部回路への装着時におけるパッケー
ジモールドのクラック発生を防止することを目的とし、 リードフレームのステージ上に半導体チップを搭載
し、該半導体チップ上の複数の電極と該各電極に対応し
て上記ステージの周囲に配置された該リードフレームの
配線電極との間をワイヤボンディングし、上記半導体チ
ップとワイヤボンディング部分を上記ステージと共に樹
脂封止した樹脂封止型半導体装置であって、半導体チッ
プ搭載前の前記リードフレームが、ステージの半導体チ
ップ搭載面の裏面側に、散在配置した複数の突起と該ス
テージ周囲に沿い該突起と等しい高さの閉ループ状の壁
とを備えて形成され、該ステージとその周囲に位置する
前記配線電極の少なくとも上記裏面側を除く面に金属め
っきして構成する。DETAILED DESCRIPTION OF THE INVENTION [Outline] Regarding a resin-sealed semiconductor device, a semiconductor chip is mounted on a stage of a lead frame for the purpose of preventing generation of cracks in a package mold when mounted on an external circuit such as a printed circuit board. The semiconductor chip and the wire bonding portion are mounted by wire bonding between a plurality of electrodes on the semiconductor chip and wiring electrodes of the lead frame arranged around the stage corresponding to the respective electrodes. A resin-encapsulated semiconductor device, which is resin-encapsulated with a stage, wherein the lead frame before mounting a semiconductor chip has a plurality of protrusions arranged in a scattered manner on the back surface side of the semiconductor chip mounting surface of the stage and along the periphery of the stage. A closed loop wall having a height equal to that of the projection, and the wiring electrode located around the stage and the periphery of the stage. At least the surface other than the back surface side is metal-plated.
本発明は半導体装置に係り、特にプリント基板等外部
回路への装着時におけるパッケージモールドのクラック
発生を防止して特性の向上と生産性の向上を図った樹脂
封止型半導体装置に関する。The present invention relates to a semiconductor device, and more particularly to a resin-encapsulated semiconductor device in which cracks are prevented from being generated in a package mold when mounted on an external circuit such as a printed circuit board to improve characteristics and productivity.
第２図は従来の樹脂封止型半導体装置の一例を示す図
であり、（Ａ）は全体の構成断面図をまた（Ｂ）はステ
ージ単体の形成工程を裏面側から見た状態で示す図，
（Ｃ）はステージのメッキ工程を示す図である。FIG. 2 is a diagram showing an example of a conventional resin-encapsulated semiconductor device, (A) is a sectional view of the entire configuration, and (B) is a diagram showing a step of forming a single stage as viewed from the back side. ，
(C) is a figure which shows the plating process of a stage.
図（Ａ）で半導体チップ２は、例えば厚さ0.1mmでそ
の表面の少なくともステージ4aを含む所定領域に銀メッ
キ層３′が施された42アロイ合金等よりなるリードフレ
ーム４の該ステージ4a上に、銀ペースト等で接着固定さ
れている。In FIG. 1A, the semiconductor chip 2 is, for example, on a stage 4a of a lead frame 4 made of a 42 alloy alloy or the like having a thickness of 0.1 mm and a silver plating layer 3'provided on a predetermined region including at least the stage 4a on the surface thereof. It is adhesively fixed with silver paste or the like.
そこで、上記半導体チップ２上の複数の電極とステー
ジ4aの周囲に上記各電極に対応して配置したリードフレ
ーム４の配線電極とをワイヤ５でボンディング接続した
後、少なくとも上記半導体チップ２を含むステージ4aと
上記ワイヤ５が完全に覆われるようにエポキシ系樹脂６
等で封止して樹脂封止型半導体装置１を構成している。Therefore, after connecting a plurality of electrodes on the semiconductor chip 2 and the wiring electrodes of the lead frame 4 arranged around the stage 4a so as to correspond to the electrodes with wires 5, a stage including at least the semiconductor chip 2 is provided. Epoxy resin 6 so that 4a and the wire 5 are completely covered
The resin-encapsulated semiconductor device 1 is configured by encapsulation with the like.
かかる樹脂封止型半導体装置１をプリント基板等の外
部回路に搭載するには、該樹脂封止型半導体装置１の外
部に露出している上記リードフレーム４の配線電極部分
を上記の外部回路に半田等の手段で接続固定するが、こ
の接続時には通常約200℃程度まで加熱される。To mount the resin-sealed semiconductor device 1 on an external circuit such as a printed circuit board, the wiring electrode portion of the lead frame 4 exposed outside the resin-sealed semiconductor device 1 is mounted on the external circuit. It is connected and fixed by means of solder or the like, but this connection is usually heated to about 200 ° C.
この際、リードフレーム４の材料と封止樹脂材６の間
特にステージ4a部分では熱膨張係数の差によって発生す
る界面部分での内部応力が該界面部分を剥離させたり封
止樹脂材６にクラックを生するが、上記リードフレーム
４のステージ4aの封止樹脂材６と接する面が平坦な場合
には特にこの傾向が強くなることが知られている。At this time, internal stress at the interface between the material of the lead frame 4 and the encapsulation resin 6, especially at the stage 4a portion due to the difference in thermal expansion coefficient causes the interface to peel off or crack the encapsulation resin 6. However, it is known that this tendency becomes particularly strong when the surface of the lead frame 4 in contact with the sealing resin material 6 of the stage 4a is flat.
そこでこれを防止するため、一般には上記ステージ4a
の封止樹脂材６と接する面に図示の如き微小な突起4bが
生ずるように該リードフレーム４を加工して凹凸を付与
するようにしている。Therefore, in order to prevent this, in general, the stage 4a described above is used.
The lead frame 4 is processed so as to have irregularities so that minute protrusions 4b as shown in the figure are formed on the surface contacting with the sealing resin material 6.
この微小な凹凸を付与する方法を説明する図（Ｂ）
は、理解し易くするために図（Ａ）におけるリードフレ
ーム４を裏面側から見た状態で表わしており、（１）は
成形したままのリードフレーム４のステージ4a近傍を示
しまた（２）は凹凸を付けた状態を示している。The figure explaining the method of giving this minute unevenness | corrugation (B).
For ease of understanding, the lead frame 4 in FIG. 4A is viewed from the back side, (1) shows the vicinity of the stage 4a of the as-molded lead frame 4, and (2) shows The figure shows a state with unevenness.
図（１）で成形したままのリードフレーム４は、ほぼ
中央部に５〜10mm角のステージ4aと該ステージ4aを保持
する例えば２個の保持部4cおよび該ステージ4aを取り囲
んでその周囲に放射状に形成した複数の配線電極4dとで
構成されている。The lead frame 4 as-molded in FIG. 1A has a stage 4a of 5 to 10 mm square in the substantially central portion, for example, two holding portions 4c for holding the stage 4a and the stage 4a surrounding and radially surrounding the stage 4a. It is composed of a plurality of wiring electrodes 4d formed in.
ここで該リードフレーム４の片面に、ステージ4aより
多少大きい例えば図の一点鎖線で示す領域Ｓの部分を通
常のエッチング手段を用いて該リードフレーム４の厚さ
の50〜60％程度例えば0.05〜0.06mm位の範囲にエッチン
グ除去するが、この際複数（図では９個）の円形状の突
起4bが残るように該エッチング処理を施して図（２）に
示す状態としている。Here, on one surface of the lead frame 4, a portion slightly larger than the stage 4a, for example, a region S indicated by a dashed line in the figure, is used by an ordinary etching means to be about 50 to 60% of the thickness of the lead frame 4, for example, 0.05 to Although it is removed by etching to a range of about 0.06 mm, the etching process is performed so that a plurality of (9 in the figure) circular protrusions 4b remain at this time, and the state shown in FIG. 2 is obtained.
次いて、該ステージ4aの平坦面部分すなわち図（Ｂ）
の裏面側に図（Ａ）で説明した半導体チップ２を導通を
保って接着固定するため、少なくとも該ステージ4aの平
坦面部分を含むリードフレーム４の所定領域に銀（Ag）
メッキ処理を施す。Next, the flat surface portion of the stage 4a, that is, FIG.
In order to fix the semiconductor chip 2 explained in FIG. 1 (A) to the back surface side of the same by adhering and fixing the same, silver (Ag) is provided in a predetermined area of the lead frame 4 including at least the flat surface portion of the stage 4a.
Apply plating treatment.
図（Ｃ）はメッキ処理工程を説明する図であり、図
（Ｂ）をｃ〜ｃ′で切断した断面を上下反転させて正規
の方向になるように示している。FIG. 6C is a diagram for explaining the plating process, and the cross section taken along line c-c ′ in FIG.
図で、は図（Ｂ）の（１）に対応しまたは図
（Ｂ）の（２）に対応するものである。In the figure, corresponds to (1) in FIG. (B) or corresponds to (2) in FIG.
ここでに示す如く該ステージ4aの突起4b側の全面に
平坦なマスク７を添着被覆した後、通常の方法で銀メッ
キ処理を施すが、図（Ｂ）で説明した如く複数の突起4b
は散在するように配置されているためメッキ処理液が各
突起間に流入し、結果的に図に示す如く銀メッキ層
３′はマスク７が密着している突起4bの先端面を除く全
面に形成されることになる。As shown here, after a flat mask 7 is attached and coated on the entire surface of the stage 4a on the side of the protrusion 4b, a silver plating process is performed by a usual method. However, as shown in FIG.
The plating solution flows in between the protrusions because they are arranged in a scattered manner, and as a result, as shown in the figure, the silver plating layer 3'is formed on the entire surface of the protrusion 4b except the tip surface of the protrusion 4b to which the mask 7 is adhered. Will be formed.
一方、この銀メッキ層は封止樹脂材料との密着性が芳
しくなく、半導体装置として前述した外部回路に装着す
るときの熱で封止樹脂が銀メッキ層から剥離したり該封
止樹脂にクラックが発生することがある。On the other hand, this silver-plated layer does not have good adhesion to the encapsulating resin material, and thus the encapsulating resin may peel off from the silver-plating layer or crack in the encapsulating resin due to heat when the semiconductor device is mounted on the external circuit described above. May occur.
従ってかかる構成になる樹脂封止型半導体装置では、
プリント基板等の外部回路に装着する際の熱によって封
止樹脂材料との間の剥離やクラックの発生を完全に防止
することができず、特性および生産性の向上を阻害する
要因となっている。Therefore, in the resin-sealed semiconductor device having such a configuration,
It is not possible to completely prevent peeling and cracks from the encapsulating resin material due to heat when mounting it on an external circuit such as a printed circuit board, which is a factor that hinders improvement in characteristics and productivity. .
なお封止樹脂材料と接する面に銀メッキ層３′が形成
されないようにするには上記マスク７を該ステージ4aの
凹凸に合わせて加工しなければならず、価格的に得策で
ない。In order to prevent the silver plating layer 3'from being formed on the surface in contact with the encapsulating resin material, the mask 7 must be processed according to the irregularities of the stage 4a, which is not a good cost measure.
従来の樹脂封止型半導体装置では、プリント基板等の
外部回路に装着する際の熱による封止樹脂材料の剥離や
クラックの発生を完全に防止することができないと言う
問題があった。The conventional resin-encapsulated semiconductor device has a problem that it is impossible to completely prevent peeling or cracking of the encapsulating resin material due to heat when it is mounted on an external circuit such as a printed circuit board.
上記問題点は、リードフレームのステージ上に半導体
チップを搭載し、該半導体チップ上の複数の電極と該各
電極に対応して上記ステージの周囲に配置された該リー
ドフレームの配線電極との間をワイヤボンディングし、
上記半導体チップとワイヤボンディング部分を上記ステ
ージと共に樹脂封止した樹脂封止型半導体装置であっ
て、 半導体チップ搭載前の前記リードフレームが、ステー
ジの半導体チップ搭載面の裏面側に、散在配置した複数
の突起と該ステージ周囲に沿い該突起と等しい高さの閉
ループ状の壁とを備えて形成され、該ステージとその周
囲に位置する前記配線電極の少なくとも上記裏面側を除
く面が金属めっきされてなる樹脂封止型半導体装置によ
って解決される。The above-mentioned problem is that a semiconductor chip is mounted on the stage of the lead frame, and between the plurality of electrodes on the semiconductor chip and the wiring electrodes of the lead frame arranged around the stage corresponding to the respective electrodes. Wire bonding,
A resin-encapsulated semiconductor device in which the semiconductor chip and a wire bonding portion are resin-encapsulated together with the stage, wherein the lead frame before mounting the semiconductor chip is arranged in a scattered manner on the back surface side of the semiconductor chip mounting surface of the stage. And a wall of a closed loop shape having a height equal to that of the projection along the periphery of the stage, and at least the surface of the wiring electrode located around the stage except the back surface side is metal-plated. This is solved by the resin-sealed semiconductor device.
封止樹脂材料の剥離やクラックの発生を防止するに
は、クラック発生防止用の微小突起形成面側のステージ
全面が銀メッキされないことが必要である。In order to prevent peeling of the encapsulating resin material and the occurrence of cracks, it is necessary that the entire stage on the microprojection formation surface side for preventing the occurrence of cracks is not silver-plated.
本発明では、凹凸形成面側のステージ周囲を突起の高
さと等しい閉ループをなす壁で完全に囲むように該ステ
ージを形成している。In the present invention, the stage is formed so as to completely surround the periphery of the stage on the side of the concavo-convex formation with a wall forming a closed loop equal to the height of the protrusion.
従って、該凹凸形成面を平坦なマスクでカバーしても
メッキ処理液がマスクとステージの間に流入せず該凹凸
形成面がメッキされないことから、外部回路に装着する
際にも剥離やクラックの発生のない樹脂封止型半導体装
置を得ることができる。Therefore, even if the concavo-convex forming surface is covered with a flat mask, the plating solution does not flow between the mask and the stage, and the concavo-convex forming surface is not plated. It is possible to obtain a resin-sealed semiconductor device that does not generate.
第１図は本発明になる樹脂封止型半導体装置の一例を
示す図であり、（ａ）は全体の構成断面図をまた（ｂ）
はステージ単体の形成工程を示す図，（ｃ）はステージ
のメッキ工程を示す図である。FIG. 1 is a view showing an example of a resin-encapsulated semiconductor device according to the present invention, in which (a) is a sectional view of the entire structure and (b) is a sectional view.
FIG. 4A is a diagram showing a step of forming a single stage, and FIG. 7C is a diagram showing a stage plating process.
図（ａ）で半導体チップ２は、第２図同様の方法でリ
ードフレーム11のステージ11a上に銀ペースト等で接着
固定してある。2A, the semiconductor chip 2 is adhered and fixed onto the stage 11a of the lead frame 11 with silver paste or the like in the same manner as in FIG.
また該半導体チップ２上の複数の電極と該各電極に対
応する上記リードフレーム11の配線電極とがワイヤ５で
ボンディング接続された後、エポキシ系樹脂６等で封止
して樹脂封止型半導体装置10が構成されていることは第
２図と同様である。Further, a plurality of electrodes on the semiconductor chip 2 and the wiring electrodes of the lead frame 11 corresponding to the respective electrodes are bonded and connected by wires 5, and then sealed with an epoxy resin 6 or the like to form a resin-sealed semiconductor. The construction of the device 10 is similar to that of FIG.
該ステージ11a部分に凹凸を付加する方法を説明する
図（ｂ）は、第２図同様に図（ａ）のリードフレーム11
を裏面側から見た状態で表わしており、（Ｉ）は成形し
たままのリードフレーム11をまた（II）は凹凸を付けた
状態をそれぞれ示している。2B is a view for explaining a method of adding unevenness to the stage 11a portion, the same as FIG. 2, and the lead frame 11 of FIG.
Is viewed from the back side, (I) shows the as-molded lead frame 11, and (II) shows the state in which unevenness is provided.
図（Ｉ）で、成形したままのリードフレーム11は、ほ
ぼ中央部に５〜10mm角のステージ11aと該ステージ11aを
保持する例えば２個の保持部11cおよび該ステージ11aを
取り囲むようにその周囲放射状に形成した複数の配線電
極11dとで構成されていることは第２図の場合と同様で
ある。In FIG. 1 (I), the lead frame 11 as it is molded has a stage 11a of 5 to 10 mm square in the substantially central portion, for example, two holding portions 11c for holding the stage 11a and the periphery thereof so as to surround the stage 11a. It is similar to the case of FIG. 2 in that it is composed of a plurality of wiring electrodes 11d formed radially.
ここで、該リードフレーム11の片面のステージ11aよ
り僅かに小さい例えば図の一点鎖線で示す領域S1の部分
のみを、第２図同様に複数（図では９個）の円形状の突
起が残るように通常の手段によってエッチング除去す
る。Here, a plurality of (9 in the drawing) circular protrusions are left in the same manner as in FIG. 2 only in a part of the area S 1 shown by the alternate long and short dash line in FIG. 2 which is slightly smaller than the stage 11a on one surface of the lead frame 11. As described above, it is removed by etching by the usual means.
この場合には図（II）に示す如く、該ステージ11aの
片面に複数の突起11bと共にその周囲に該突起11bと同じ
高さの壁11eが残る。In this case, as shown in FIG. (II), a plurality of projections 11b are left on one surface of the stage 11a, and a wall 11e having the same height as the projections 11b remains around the projections 11b.
メッキ処理を施す工程を説明する図（ｃ）は、図
（ｂ）をｃ〜ｃ′で切断した断面を上下反転させて表わ
している。FIG. 7C for explaining the step of performing the plating process is shown by vertically inverting the cross section taken along line c-c ′ in FIG.
図で、（イ）は図（ｂ）の（Ｉ）に対応しまた（ロ）
は図（ｂ）の（II）に対応するものである。In the figure, (a) corresponds to (I) in figure (b) and (b).
Corresponds to (II) in FIG.
ここで（ハ）に示す如く該ステージ11aの突起11b側の
全面に第２図同様のマスク７を添着して該面を被覆した
後、通常の方法で銀メッキ処理を施すが、複数の突起11
bが散在して配置されていても図（ｂ）で説明した如く
その周囲が該突起11bと同じ高さの壁11eで囲まれている
ため銀メッキ液の流入がなく、結果的に図（ニ）に示す
如く銀メッキ層３は凹凸形成面内には形成されない。Here, as shown in (c), a mask 7 similar to that shown in FIG. 2 is attached to the entire surface of the stage 11a on the side of the projection 11b to cover the surface, and then silver plating is performed by a normal method. 11
Even if the b's are scattered, the surroundings are surrounded by the wall 11e having the same height as the protrusion 11b as described with reference to FIG. As shown in (d), the silver-plated layer 3 is not formed on the surface where the concavities and convexities are formed.
従ってかかる構成になる樹脂封止型半導体装置では、
封止樹脂材料がステージ11aの凹凸形成面側の壁11cの内
部で銀メッキ層を介することなく直接ステージ11aの凹
凸形成面と接することから、接触面積の拡大とあいまっ
て該封止樹脂材料のステージ11aに対する密着性が向上
し、プリント基板等の外部回路に装着する際の熱による
封止樹脂材料の剥離やクラックの発生を完全に防止する
ことができる。Therefore, in the resin-sealed semiconductor device having such a configuration,
Since the encapsulating resin material directly contacts the uneven surface of the stage 11a without interposing the silver plating layer inside the wall 11c on the uneven surface forming surface of the stage 11a, the encapsulating resin material is combined with the expansion of the contact area. Adhesion to the stage 11a is improved, and peeling or cracking of the sealing resin material due to heat when mounted on an external circuit such as a printed circuit board can be completely prevented.
上述の如く本発明により、プリント基板等の外部回路
に装着しても剥離やクラック等が発生することのない特
性および生産性に優れた樹脂封止型半導体装置を提供す
ることができる。As described above, according to the present invention, it is possible to provide a resin-encapsulated semiconductor device which is excellent in characteristics and productivity without peeling or cracking even when mounted on an external circuit such as a printed circuit board.
なお本発明の説明に当たっては、リードフレームのス
テージ片面に形成する突起を円柱状に形成した場合につ
いて行っているが、その断面を三角，四角等何れの形状
にしても同様の効果を得ることができる。In the description of the present invention, the case where the projection formed on one surface of the stage of the lead frame is formed in a cylindrical shape is performed, but the same effect can be obtained even if the cross section is triangular or square. it can.
第１図は本発明になる樹脂封止型半導体装置の一例を示
す図、 第２図は従来の樹脂封止型半導体装置の一例を示す図、 である。図において、 ２は半導体チップ、3,3′は銀メッキ層、５はワイヤ、
６は封止樹脂材、７はマスク、10は樹脂封止型半導体装
置、11はリードフレーム、11aはステージ、11bは突起、
11cは保持部、11dは配線電極、11eは壁、 をそれぞれ表わす。FIG. 1 is a diagram showing an example of a resin-sealed semiconductor device according to the present invention, and FIG. 2 is a diagram showing an example of a conventional resin-sealed semiconductor device. In the figure, 2 is a semiconductor chip, 3, 3'is a silver plating layer, 5 is a wire,
6 is a sealing resin material, 7 is a mask, 10 is a resin-sealed semiconductor device, 11 is a lead frame, 11a is a stage, 11b is a protrusion,
Reference numeral 11c represents a holding portion, 11d represents a wiring electrode, and 11e represents a wall.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 蛯原 一美 鹿児島県薩摩郡入来町副田5950番地 株 式会社九州富士通エレクトロニクス内 (56)参考文献 特開 昭56−94760（ＪＰ，Ａ) 特開 昭63−31147（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazumi Ebihara 5950 Soeda, Iriki-cho, Satsuma-gun, Kagoshima Prefecture Within Kyushu Fujitsu Electronics Co., Ltd. (56) Reference JP-A-56-94760 (JP, A) Sho 63-31147 (JP, A)
Claims (1)
プを搭載し、該半導体チップ上の複数の電極と該各電極
に対応して上記ステージの周囲に配置された該リードフ
レームの配線電極との間をワイヤボンディングし、上記
半導体チップとワイヤボンディング部分を上記ステージ
と共に樹脂封止した樹脂封止型半導体装置であって、 半導体チップ搭載前の前記リードフレームが、 ステージの半導体チップ搭載面の裏面側に、散在配置し
た複数の突起と該ステージ周囲に沿い該突起と等しい高
さの閉ループ状の壁とを備えて形成され、 少なくとも上記裏面側を除く該ステージが金属めっきさ
れてなることを特徴とする樹脂封止型半導体装置。1. A semiconductor chip is mounted on a stage of a lead frame, and between a plurality of electrodes on the semiconductor chip and wiring electrodes of the lead frame arranged around the stage corresponding to the respective electrodes. Is a resin-sealed semiconductor device in which the semiconductor chip and the wire-bonded portion are resin-sealed together with the stage, and the lead frame before mounting the semiconductor chip is on the back surface side of the semiconductor chip mounting surface of the stage. Characterized in that it is formed of a plurality of protrusions arranged in a scattered manner and a closed loop wall having a height equal to the protrusions along the periphery of the stage, and at least the stage except the back surface side is metal-plated. Resin-sealed semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1026218A JP2506429B2 (en) | 1989-02-03 | 1989-02-03 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1026218A JP2506429B2 (en) | 1989-02-03 | 1989-02-03 | Resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02205351A JPH02205351A (en) | 1990-08-15 |
| JP2506429B2 true JP2506429B2 (en) | 1996-06-12 |
Family
ID=12187263
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1026218A Expired - Lifetime JP2506429B2 (en) | 1989-02-03 | 1989-02-03 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2506429B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06209054A (en) * | 1993-01-08 | 1994-07-26 | Mitsubishi Electric Corp | Semiconductor device |
| KR100386061B1 (en) | 1995-10-24 | 2003-08-21 | 오끼 덴끼 고오교 가부시끼가이샤 | Semiconductor device and lead frame with improved construction to prevent cracking |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5694760A (en) * | 1979-12-28 | 1981-07-31 | Nec Corp | Semiconductor device |
| JPS6331147A (en) * | 1986-07-24 | 1988-02-09 | Nec Corp | Lead frame of semiconductor device |
-
1989
- 1989-02-03 JP JP1026218A patent/JP2506429B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02205351A (en) | 1990-08-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3012816B2 (en) | Resin-sealed semiconductor device and method of manufacturing the same | |
| JP2000188353A (en) | Ball grid array type semiconductor device and its manufacture | |
| JPH1012773A (en) | Resin-sealed semiconductor device and its manufacture | |
| JPH0778900A (en) | Plastic package structure for power device and its assembly | |
| JP2000269166A (en) | Manufacture of integrated circuit chip and semiconductor device | |
| JPS6050343B2 (en) | Lead frame for semiconductor device manufacturing | |
| JP2506429B2 (en) | Resin-sealed semiconductor device | |
| WO1998042022A1 (en) | Semiconductor device and method of manufacturing same | |
| JPS59161850A (en) | Resin sealed type semiconductor device and lead frame used therefor | |
| JPH03149865A (en) | Lead frame | |
| JP2694871B2 (en) | Semiconductor device | |
| JP2954297B2 (en) | Resin-sealed semiconductor device | |
| JPS6224650A (en) | Semiconductor device | |
| JP2002164497A (en) | Semiconductor device and method for manufacturing the same | |
| JPS62263665A (en) | Lead frame and semiconductor device using thesame | |
| JPH0526761Y2 (en) | ||
| JPH05166871A (en) | Semiconductor device | |
| JP2023172854A (en) | Lead frame and method for manufacturing the same | |
| JPH09275176A (en) | Plastic molded type semiconductor device | |
| JPH10189834A (en) | Semiconductor device | |
| JPH09275177A (en) | Semiconductor device | |
| JP2771475B2 (en) | Semiconductor device | |
| JPH0536863A (en) | Semiconductor device | |
| JPS6178150A (en) | Lead frame for resin seal type semiconductor device | |
| JPH10163231A (en) | Manufacture of semiconductor package |