JPS6178150A - Lead frame for resin seal type semiconductor device - Google Patents

Lead frame for resin seal type semiconductor device

Info

Publication number
JPS6178150A
JPS6178150A JP59200256A JP20025684A JPS6178150A JP S6178150 A JPS6178150 A JP S6178150A JP 59200256 A JP59200256 A JP 59200256A JP 20025684 A JP20025684 A JP 20025684A JP S6178150 A JPS6178150 A JP S6178150A
Authority
JP
Japan
Prior art keywords
lead frame
film
resin
coating
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59200256A
Other languages
Japanese (ja)
Inventor
Seisaku Yamanaka
山中　正策
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP59200256A priority Critical patent/JPS6178150A/en
Publication of JPS6178150A publication Critical patent/JPS6178150A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48639—Silver (Ag) as principal constituent
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439—Silver (Ag) as principal constituent
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    • H01L2924/01047—Silver [Ag]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To omit plating treatment after a resin seal and pretreatment and the like, and to reduce cost by coating at least an outer lead section of a lead frame proper with Au. CONSTITUTION:A thin Au film 9 is formed onto the whole surface of a lead frame 1, and Ag films 4 are shaped onto a chip bonding section 2 and wire bonding sections 3. A chip 5 is fitted onto the Ag film 4, and the Ag film 4 on an inner lead section and electrodes on the chip are connected by Au wires 6, and sealed with a resin 7. The thickness of the Au film on the lead frame 1 extends over 100-1,000Angstrom . Accordingly, plating processing after the resin sealing is unnecessitated, and cost can be reduced.

Description

【発明の詳細な説明】 １１ユ旦豆里糧 本発明は樹脂封止型半導体装置用リードフレームに関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a lead frame for a resin-sealed semiconductor device.

従来の技術 所定の機能付与がなされた半導体装置は、一般に気密封
止法、樹脂封止法などに従ってパッケージに封入される
。このパッケージングは該装置（またはチップ）を外部
雰囲気から遮断することにより所期の特性値を十分に保
持し、熱的、電気的導出、電極間の絶縁距離の確保、そ
の他運搬、取扱い性の便宜のために行なわれるものであ
り、半導体装置の微細化、高性能化等を追求してい（際
に、特に半導体装置と外的条件との整合を図るために極
めて１要であり、この意味でパッケージング技術、その
８品の改良も、半導体素子自体の改良と平行して行わね
ばならない重要な課題であり、無視できない問題である
。2. Description of the Related Art Semiconductor devices that have been provided with predetermined functions are generally sealed in a package using a hermetic sealing method, a resin sealing method, or the like. This packaging sufficiently maintains the desired characteristic values by isolating the device (or chip) from the external atmosphere, ensuring thermal and electrical conduction, insulation distance between electrodes, and other aspects such as transportation and handling. This is done for convenience, and in pursuit of miniaturization and higher performance of semiconductor devices (in particular, it is extremely important to match semiconductor devices with external conditions, and this meaning is important). Improving packaging technology and its eight products is an important issue that must be carried out in parallel with the improvement of semiconductor devices themselves, and is a problem that cannot be ignored.

ところで、パッケージとしては金属、セラミックス等と
比較して量産性が良く、低価格であることから樹脂封止
型パッケージが広く利用され、また各種改良が加えられ
て、信頼性も向上しており、実用性の高いものとされて
いる。By the way, resin-sealed packages are widely used as packages because they are easier to mass produce and are cheaper than metals, ceramics, etc., and various improvements have been made to improve reliability. It is considered highly practical.

該パッケージにおいて、機能付与された半導体チップは
リードフレームにダイボンディングにより固定され、ま
たワイヤボンディング等により電気的に接続される。In the package, a semiconductor chip with functions is fixed to a lead frame by die bonding and electrically connected by wire bonding or the like.

現在樹脂封圧型パッケージにおいて使用されているリー
ドフレームは、材質の点からＦｅ−Ｎｉ系、Ｃｕ系、Ｆ
ｅ系などに大別されるが、使用目的、特にＩＣ自体の高
信頼性が必要とされる場合には、Ｆｅ−Ｎ＋系の材料を
使用することが主流となっている。Lead frames currently used in resin-sealed packages are Fe-Ni based, Cu based, F
Fe-N+ materials are mainly used for purposes of use, especially when high reliability of the IC itself is required.

半導体チップとリードフレームとの間の熱膨張率の差が
問題となることから、特に大型チップ、高集積チップに
ついてはＦｅ−Ｎｉ系のリードフレームが広く利用され
ている。Since the difference in thermal expansion coefficient between a semiconductor chip and a lead frame poses a problem, Fe--Ni lead frames are widely used, especially for large chips and highly integrated chips.

このＰｅ−Ｎｉ系リードフレームには通常金属被膜が施
されるが、チップボンド、ワイヤーボンドなどの組立実
装の観点からＡｕ、　Ａｇなどが使用されている。これ
らは、ＩＣに要求される信頼性の度合、Ｓｉチップの搭
載形式、金属被膜のコストなどを考慮して適宜使い分け
られていた。This Pe-Ni lead frame is usually coated with a metal film, but Au, Ag, etc. are used from the viewpoint of assembly and mounting such as chip bonding and wire bonding. These were used appropriately depending on the degree of reliability required for the IC, the mounting format of the Si chip, the cost of the metal coating, and so on.

従来、第２図に示したように、リードフレーム１のグイ
パッド部２およびインナーリードｉｌ’ｌＳ３にこれら
金属被ｖ４がスポット状に形成されていた。Conventionally, as shown in FIG. 2, these metal coverings v4 have been formed in the shape of spots on the lead frame 1 and the inner lead il'lS3.

また、第２図に示したような金属被膜を有するリードフ
レートを使用してＩＣパッケージを組立てる場合、その
グイパッド邪２上にスポット状金属膜４を介してＳｉチ
ップ５等の半導体素子を搭載し、チップ５とリードフレ
ームインナーリード邪３とをＡｕワイヤー６などで電気
的に接続し、樹脂封止７を施して完成品としての半導体
装置としていたが、この場合アウターリード部の表面に
Ｓｎめっきまたは半■１めっきを施す必要があった。こ
のアウターリード部へめっきを施す理由は、半導体装置
をプリント基板等に半田付けする場合に、Ｆｅ−Ｎｉ合
金等のリードフレーム素材のままでは半田等に対する濡
れ性が著しく悪（、その都度強力な前処理、例えばフラ
／クスを使用した前処理などが必要となるからである。Furthermore, when assembling an IC package using a lead plate having a metal coating as shown in FIG. , the chip 5 and the lead frame inner leads 3 were electrically connected with Au wires 6, etc., and resin sealing 7 was applied to produce a semiconductor device as a completed product.In this case, the surface of the outer lead part was Sn plated. Alternatively, it was necessary to apply semi-1 plating. The reason why this outer lead is plated is that when a semiconductor device is soldered to a printed circuit board, etc., lead frame materials such as Fe-Ni alloy have extremely poor wettability to solder, etc. This is because pretreatment, such as pretreatment using flux, is required.

従って、めっき加工の工程数が増大し、仕掛り日数も増
大し、結果としてコスト高となるなど各（重の問題点を
含んでいる。Therefore, the number of plating processes increases, the number of work days increases, and as a result, costs increase.

発明が解決すべき問題点 以上詳しく述べたように、半導体素子の進歩は著しいが
、それに応じてパッケージング技術の向上を図ることも
重要な課題である。ところが、従来、特に樹脂封止型パ
ッケージにおけるリードフレームではスポット状の金属
被膜を特定部分に形成して、半導体チップの搭載並びに
これら相互の電気的接続を行い、更に樹脂封止を行った
後、別途プリント基板等への取付けの際の予備加工とし
てアウターリード部のめっき工程が必要とされていたが
、このような方法は工程数が多く、コスト高であり、ま
た特にＦｅ−Ｎｉ合金等のリードフレーム素材自体が半
田に対する低い濡れ性を有することから、特別な前処理
を必要とするなど、各種改善すべき問題点を内包してい
た。Problems to be Solved by the Invention As described in detail above, semiconductor devices have made remarkable progress, but it is also an important issue to improve packaging technology accordingly. However, in the past, especially in lead frames for resin-sealed packages, spot-shaped metal coatings were formed on specific parts to mount semiconductor chips and electrically connect them, and after sealing with resin, A plating process was required for the outer lead part as a preliminary process when attaching it to a separate printed circuit board, etc., but such a method requires a large number of steps and is expensive, and is especially suitable for Fe-Ni alloys etc. Since the lead frame material itself has low wettability with solder, it requires special pretreatment, and has various problems that need to be improved.

そこで、本発明は従来の如く、樹脂封止後のアウターリ
ードのめっき処理、そのための前処理等を省くことがで
き、またコストの節減を図ることのできる新しいリード
フレームを提供することにあり、その製造方法を提供す
ることも本発明の目的の１つである。Therefore, an object of the present invention is to provide a new lead frame that can omit the conventional plating treatment of outer leads after resin sealing, pretreatment, etc., and can reduce costs. It is also an object of the present invention to provide a manufacturing method thereof.

問題点を解決するための手段 本発明者は上記のようなリードフレームに関する現状に
鑑みて、新たなリードフレームを開発すべく種々検討し
たところ、予めリードフレーム自体のアウターリード部
を＾Ｕ薄膜でコーティングしておくことが上記目的達成
のために極めて有効であることを見出した。本発明はこ
のような新規知見に基き完成されたものである。Means for Solving the Problems In view of the current state of lead frames as described above, the present inventor conducted various studies in order to develop a new lead frame. It has been found that coating is extremely effective for achieving the above objective. The present invention was completed based on such new findings.

本発明の樹脂封止型半導体装置用リードフレームはリー
ドフレーム本体と、チγプボンディング邪及びインナー
リード部にスポット状に設けられたグイボンディング用
並びにワイヤボンディング用金属被膜と、リードフレー
ム本体の少なくともてウターリード部に設けられたＡｕ
被膜とで構成されたことを特徴とする。The lead frame for a resin-sealed semiconductor device of the present invention includes a lead frame body, a metal coating for chip bonding and wire bonding provided in spots on the tip bonding portion and the inner lead portion, and at least one of the lead frame body. Au provided on the outer lead part
It is characterized by being composed of a film.

本発明のリードフレームにおいて、リードフレーム本体
は一般的に知られている各種方法のいずれかによって作
製することができ、例えば典型的な方法を挙げると、打
抜き法、エツチング法、例えばレジスト材などのマスク
パターンを利用して化学的に行ういわゆるウェットエツ
チングなどを例示できる。尚、これらによって何隻制限
されるものではな（、例えばエツチングとしてドライエ
ツチング、即ちスパッタエツチング、ガスプラズマエツ
チング等を使用し得ることはいうまでもない。In the lead frame of the present invention, the lead frame main body can be produced by any of various generally known methods. Typical methods include punching, etching, and using a resist material, etc. An example of this is so-called wet etching, which is chemically performed using a mask pattern. Note that the number of etching devices is not limited by these (for example, it goes without saying that dry etching, sputter etching, gas plasma etching, etc. can be used as etching).

リードフレーム本体の材質としては、既に挙げたように
Ｆｅ−Ｎｉ系、Ｃｕ系、Ｆｅ系の従来公知の任意の材料
を選ぶことができるが、特に大型チップ、高集積チップ
等に有利に使用できるＦｅ　　Ｎ＋系材料が適している
。As the material of the lead frame body, any conventionally known material such as Fe-Ni, Cu, or Fe can be selected as mentioned above, but it can be used particularly advantageously for large chips, highly integrated chips, etc. Fe N+ based materials are suitable.

また、少なくともアウターリード部に適用される静被膜
は各種被覆法、例えば塗布、浸漬、電解めっき、スプレ
ー法、一般的な蒸着法等により形成することができ、特
に制限はない。同様に、チップボンディング品及びワイ
ヤーボンディング部の金属被膜の形成も、従来公知の電
解めっき法、蒸着法等各種の方法に従って実施すること
ができる。Further, the static coating applied to at least the outer lead portion can be formed by various coating methods, such as coating, dipping, electrolytic plating, spraying, general vapor deposition, etc., and is not particularly limited. Similarly, the formation of metal coatings on chip bonded products and wire bonded parts can be carried out according to various conventionally known methods such as electrolytic plating and vapor deposition.

以下、添付図を参照しつつ本発明のリードフレームを更
に詳しく説明する。第１図は本発明のリードフレームを
用いた樹脂封止型ＩＣの模式的な断面図を示すものであ
り、リードフレーム１の全面に薄いＡｕ被膜９を設けた
態様を示すものである（第２図と同一の部分に対しては
同一の参照番号を用いた）。チップボンディング部２お
よびワイヤーボンディング部３上にＡｇ被膜４が設けら
れている。Hereinafter, the lead frame of the present invention will be explained in more detail with reference to the accompanying drawings. FIG. 1 shows a schematic cross-sectional view of a resin-sealed IC using the lead frame of the present invention, and shows an embodiment in which a thin Au film 9 is provided on the entire surface of the lead frame 1 (see Fig. 1). The same reference numbers have been used for the same parts as in Figure 2). An Ag coating 4 is provided on the chip bonding part 2 and the wire bonding part 3.

本発明のリードフレームを使用してＩＣパッケージを組
立てるには、まず所定の機能付与がなされたＩＣチップ
５をグイボンディング用静被覆４上に、例えばＡｇペー
ストなどの導電性接着剤等により接着し、次いでインナ
ーリード部のワイヤーボンディング用Ａｇ被膜４とチッ
プ上の電極とをへ〇ワイヤー６などで接続し、これらの
間の電気的接続を確保し、最後に、これらを樹脂７によ
り封止する。樹脂としては、例えばエポキシ樹脂、シリ
コーン樹脂等各種公知のものを、搭載するＩＣチップの
特性に応じて適宜選択して使用することができ、封止は
モールド、キャスティング、ディッピング、ポツティン
グ等により行うことができる。To assemble an IC package using the lead frame of the present invention, first, the IC chip 5 that has been given a predetermined function is bonded onto the static coating 4 for bonding using a conductive adhesive such as Ag paste. Next, the wire bonding Ag film 4 on the inner lead part and the electrode on the chip are connected with a wire 6, etc. to ensure electrical connection between them, and finally, they are sealed with resin 7. . As the resin, various known resins such as epoxy resin and silicone resin can be selected and used as appropriate depending on the characteristics of the IC chip to be mounted, and sealing can be performed by molding, casting, dipping, potting, etc. I can do it.

従って、本発明のリードフレームは、従来樹脂封止型で
パッケージされているすべての半導体装置に対して適用
することができる。Therefore, the lead frame of the present invention can be applied to all semiconductor devices conventionally packaged with resin sealing.

作用 本発明のリードフレームは、リードフレーム本体の少な
くともアウターリード部にＡｕ被覆を施したことに特徴
があり、この特徴に基き、従来製品においてみられた上
記のような諸欠点が効果的に改善され、取扱い上におい
ても極めて有利な製品を提供することができる。Function The lead frame of the present invention is characterized in that at least the outer lead portion of the lead frame body is coated with Au, and based on this feature, the above-mentioned defects found in conventional products can be effectively improved. This makes it possible to provide products that are extremely advantageous in terms of handling.

本発明のリードフレームは、特に樹脂封止型ＩＣパッケ
ージのリードフレームとして有用なものである。その理
由は、ガラスセラミック封止型ＩＣなどの気密封止では
、ＩＣ組立工程で５００　ｔを越える熱履歴を受ける。The lead frame of the present invention is particularly useful as a lead frame for resin-sealed IC packages. The reason for this is that hermetically sealed glass-ceramic ICs undergo a thermal history of over 500 tons during the IC assembly process.

しかしながら、Ａｕ被覆がこれに耐え得る４）のである
ためには２０．００（ｌ　Ａ以上の膜厚を必要とするこ
とが知られており、その結果、全体としての製造コスト
は著しく高いものとなってしまい、目的とするトータル
コストの節減を達成することができない。However, it is known that in order for the Au coating to withstand this, a film thickness of 20.00 lA or more is required, and as a result, the overall manufacturing cost is significantly high. As a result, the desired total cost reduction cannot be achieved.

従って、本発明のリードフレームにおいて、Ａｕ被膜の
厚さは１００〜１．０００人とすることが好ましい。即
ち、１００八に満たない場合には、リードフレーム素材
表面の微細な凹凸を考慮すると、均一な被膜を得ること
ができず、また、１，　０００人を越える場合には経済
的な観点から不利であり、いずれも望ましいものとはい
えない。Therefore, in the lead frame of the present invention, the thickness of the Au coating is preferably 100 to 1,000. In other words, if the number of workers is less than 1,008, it will not be possible to obtain a uniform coating considering the minute irregularities on the surface of the lead frame material, and if there are more than 1,000 workers, it will be disadvantageous from an economic point of view. None of these can be said to be desirable.

このＡｕ被膜形成操作は打抜き加工もしくはエツチング
によりリードフレーム本体を成形した後に、少なくとも
アウターリード全面に対して実施されるが、これはＡｕ
被膜の形成をアウターリードの全面に対して行わないと
、本発明の目的とする均一な半田付は性が保証できない
からである。This Au film forming operation is performed on at least the entire surface of the outer lead after forming the lead frame body by punching or etching.
This is because unless the coating is formed on the entire surface of the outer lead, uniform soldering, which is the object of the present invention, cannot be guaranteed.

尚、グイパッド部およびインナーリード部に施すスポッ
ト状の金属被膜が八８である場合、Ｆｅ−Ｎｉ系合金と
の密着性を保証するためには、一般にＡｕ。In addition, when the spot-shaped metal coating applied to the Gui pad part and the inner lead part is 88, Au is generally used to ensure adhesion with the Fe-Ni alloy.

Ｃｕなどの下地被膜を設ける必要があるが、本発明の＾
Ｕ被覆形成操作を、スポット状醜被覆形成に先立って、
リードフレーム全面に対して行うことにより、へｇＭＬ
ｍ用の下地処理とアウターリード部のへｕ被覆処理とを
同時に行い、所要工程数を減すことが可能となる。Although it is necessary to provide a base film such as Cu, the method of the present invention
The U coating formation operation is performed prior to the formation of a spot-like ugly coating,
HegML can be applied to the entire surface of the lead frame.
It is possible to perform the base treatment for m and the U coating treatment for the outer lead portion at the same time, thereby reducing the number of required steps.

上記の如く、少なくともアウターリード部に１００〜１
．０００へのへｕ被覆を施すことにより、樹脂封止型１
ｃ組立て工程における熟思層を経ても、Ａｕ被膜のもつ
良好な耐酸化性により、従来の半田またはＳｎめっきし
た場合と同等の、プリント基板等に対する良好な半田付
は性を確保することが可能となる。As mentioned above, at least the outer lead part has 100 to 1
．． By applying U coating to 000, resin-sealed mold 1
c Even after the careful consideration during the assembly process, the good oxidation resistance of the Au film ensures good solderability to printed circuit boards, etc., equivalent to that of conventional solder or Sn plating. Become.

また、上記の如く、Ａｕ被膜をリードフレーム本体全表
面に施し、次いでＡｇスポット被膜を形成することによ
り、該被膜はインナーリード部およびグイパッド部にス
ポット状に形成されるＡｇ被覆の密着性改善用の下地と
しての機能をも果たすことになる。In addition, as described above, by applying an Au coating to the entire surface of the lead frame body and then forming an Ag spot coating, the coating is used to improve the adhesion of the Ag coating formed in spots on the inner lead part and the Gui pad part. It will also function as a base.

実施例 以下、実施例により本発明のリードフレームを更に具体
的に記載する。しかし、本発明の範囲はこれら実施例に
より同等制限されない。EXAMPLES Hereinafter, the lead frame of the present invention will be described in more detail using examples. However, the scope of the invention is not equally limited by these Examples.

実施例１ 打抜き加工により碍だ、４２重量％Ｎ＋　　Ｆｅ合金製
リードフレームを使用し、これをＫＡｕ（ＣＮ）２０．
５ｇ／　ＩＫ２８　Ｐ　Ｏ−５０ｇ／β及びＫ　ＣＮ　
ｌｏｇ／　ｊ！金含有るめっき浴中、電流密度５Ａ／ｄ
ｍ’で電解めっき処理して、膜厚３００人の薄い八Ｕめ
っきを該リードフレーム全面に施した。次いで、該リー
ドフレームのインナーリード部およびグイパッド部に開
口を有する弾性体シートを用いて、Ａｇ　ＣＮ　６０ｇ
／　１及びＫ　ＣＮ９０ｇ／β含有するめっき浴にて電
流密度５０Ａ／ｄｍ″の下で処理して３μｍのＡｇ層を
設けた。Example 1 A lead frame made of a 42% by weight N+Fe alloy, which is strong through punching, is used, and this is made of KAu(CN) 20% by weight.
5g/IK28 PO-50g/β and K CN
log/j! Current density 5A/d in gold-containing plating bath
A thin 8U plating with a film thickness of 300 mm was applied to the entire surface of the lead frame by electrolytic plating with m'. Next, using an elastic sheet having openings in the inner lead part and the Gui pad part of the lead frame, 60g of Ag CN was added.
/1 and K CN 90 g/β-containing plating bath under a current density of 50 A/dm'' to form a 3 μm Ag layer.

このようにして作製したリードフレームを用い、グイパ
ッド部に３１チツプをＡｇペーストにより接着し、次い
でＡｕワイヤーによる結線を行い、樹脂封止を実施して
ｔＣパッケージを作成した。こうして僻だＩＣパッケー
ジのアウターリード部はフラックスを用いた前処理を行
わなくとも良好な半田濡れ性を示した。Using the lead frame thus produced, 31 chips were bonded to the Gui pad portion using Ag paste, and then connections were made using Au wires and resin sealing was carried out to produce a tC package. In this way, the outer lead portion of the IC package, which is located in a remote area, showed good solder wettability even without pretreatment using flux.

発明の効果 以上詳しく述べたように、樹脂封止型ＩＧに有効な、本
発明のリードフレームにおいては、少なくともアウター
リード部に薄いＡｕ被膜を形成したことに基き、樹脂封
止後のめっき加工が不要となり、従って所要工数を減じ
ることが可能となり、ひいては低コストのＩＣ生産が可
能となる。Effects of the Invention As described in detail above, in the lead frame of the present invention, which is effective for resin-sealed IGs, since a thin Au film is formed on at least the outer lead portion, plating processing after resin-sealing is possible. This eliminates the need for this process, thus making it possible to reduce the number of man-hours required, which in turn makes it possible to produce ICs at low cost.

また、リードフレーム本体全面にＡｕ被膜をほどこした
場合には、該Ａｕ被膜はＡｇのスポット状被膜形成の際
の密着性改害のための下地としても機能することになる
。この観点からも、本発明のリードフレームによれば工
程数並びにコストの節減を計ることが可能であることは
明らかである。Furthermore, when an Au coating is applied to the entire surface of the lead frame body, the Au coating also functions as a base for improving adhesion when forming an Ag spot-like coating. From this point of view as well, it is clear that the lead frame of the present invention makes it possible to reduce the number of steps and costs.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明のリードフレームを用いた樹脂封止型の
ＩＣパッケージを模式的に断面図で示したものであり、 第２図は従来のリードフレームを用いた同様なＩＣパッ
ケージを模式的断面図で示したものである。 （主な参照番号） １　リードフレーム、 ２　チップボンディング部、 ３　ワイヤボンディング部、 ４　へｇ被膜、　　５　チップ、 ６　へＵワイヤー、７　樹月旨、 ８　半日または８口被膜、 ９　　Ａｕ被膜Figure 1 is a schematic cross-sectional view of a resin-sealed IC package using the lead frame of the present invention, and Figure 2 is a schematic cross-sectional view of a similar IC package using a conventional lead frame. It is shown in a cross-sectional view. (Main reference numbers) 1 Lead frame, 2 Chip bonding part, 3 Wire bonding part, 4 Heg coating, 5 Chip, 6 To U wire, 7 Jugetsuji, 8 Half day or eight mouth coating, 9 Au coating

Claims (3)

【特許請求の範囲】[Claims] （１）リードフレーム本体と、該リードフレーム本体の
少なくともアウターリード部に設けられたＡｕ被膜と、
チップボンディング部並びにワイヤーボンディング部に
設けられた金属被膜とを具備することを特徴とする樹脂
封止型半導体装置用リードフレーム。(1) a lead frame main body; an Au coating provided on at least the outer lead portion of the lead frame main body;
A lead frame for a resin-sealed semiconductor device, comprising a metal coating provided on a chip bonding portion and a wire bonding portion. （２）前記Ａｕ被膜の膜厚が１００〜１，０００Åの範
囲内にあることを特徴とする特許請求の範囲第１項記載
のリードフレーム。(2) The lead frame according to claim 1, wherein the thickness of the Au film is within a range of 100 to 1,000 Å. （３）前記リードフレーム本体全面に亘りＡｕ被膜を設
け、その上にチップボンディング用並びにワイヤーボン
ディング用金属被膜を設けたことを特徴とする特許請求
の範囲第１項または第２項記載のリードフレーム。(3) The lead frame according to claim 1 or 2, characterized in that an Au film is provided over the entire surface of the lead frame body, and a metal film for chip bonding and wire bonding is provided thereon. .
JP59200256A 1984-09-25 1984-09-25 Lead frame for resin seal type semiconductor device Pending JPS6178150A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59200256A JPS6178150A (en) 1984-09-25 1984-09-25 Lead frame for resin seal type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59200256A JPS6178150A (en) 1984-09-25 1984-09-25 Lead frame for resin seal type semiconductor device

Publications (1)

Publication Number Publication Date
JPS6178150A true JPS6178150A (en) 1986-04-21

Family

ID=16421344

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59200256A Pending JPS6178150A (en) 1984-09-25 1984-09-25 Lead frame for resin seal type semiconductor device

Country Status (1)

Country Link
JP (1) JPS6178150A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4777520A (en) * 1986-03-27 1988-10-11 Oki Electric Industry Co. Ltd. Heat-resistant plastic semiconductor device
WO2004064154A1 (en) * 2003-01-16 2004-07-29 Matsushita Electric Industrial Co., Ltd. Lead frame for a semiconductor device
US11264546B2 (en) 2018-09-27 2022-03-01 Nichia Corporation Metallic structure for optical semiconductor device, method for producing the same, and optical semiconductor device using the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4777520A (en) * 1986-03-27 1988-10-11 Oki Electric Industry Co. Ltd. Heat-resistant plastic semiconductor device
WO2004064154A1 (en) * 2003-01-16 2004-07-29 Matsushita Electric Industrial Co., Ltd. Lead frame for a semiconductor device
US7692277B2 (en) 2003-01-16 2010-04-06 Panasonic Corporation Multilayered lead frame for a semiconductor light-emitting device
US7994616B2 (en) 2003-01-16 2011-08-09 Panasonic Corporation Multilayered lead frame for a semiconductor light-emitting device
US8541871B2 (en) 2003-01-16 2013-09-24 Panasonic Corporation Multilayered lead frame for a semiconductor light-emitting device
DE112004000155B4 (en) * 2003-01-16 2019-06-19 Panasonic Intellectual Property Management Co., Ltd. Leadframe for a semiconductor device
US11264546B2 (en) 2018-09-27 2022-03-01 Nichia Corporation Metallic structure for optical semiconductor device, method for producing the same, and optical semiconductor device using the same

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