JPH0249456A - Resin sealed type semiconductor device - Google Patents

Resin sealed type semiconductor device

Info

Publication number
JPH0249456A
JPH0249456A JP63200742A JP20074288A JPH0249456A JP H0249456 A JPH0249456 A JP H0249456A JP 63200742 A JP63200742 A JP 63200742A JP 20074288 A JP20074288 A JP 20074288A JP H0249456 A JPH0249456 A JP H0249456A
Authority
JP
Japan
Prior art keywords
resin
semiconductor chip
sealed
thin film
die stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63200742A
Other languages
Japanese (ja)
Inventor
Fumihiro Sei
文博 清
Hideaki Kotsuru
英昭 小水流
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyushu Fujitsu Electronics Ltd
Fujitsu Ltd
Original Assignee
Kyushu Fujitsu Electronics Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyushu Fujitsu Electronics Ltd, Fujitsu Ltd filed Critical Kyushu Fujitsu Electronics Ltd
Priority to JP63200742A priority Critical patent/JPH0249456A/en
Publication of JPH0249456A publication Critical patent/JPH0249456A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To prevent a package from cracks and improve the package in resistance to humidity by a method wherein a thin film is provided on all the exposed surfaces of a semiconductor chip, a die stage, bonding wires, and on the lead surfaces to be sealed by resin, and then a resin seal is provided. CONSTITUTION:A thin film 6 of titanium nitride, silicon carbide, or diamond is provided on all the exposed surfaces of a semiconductor chip 1, a die stage 2, bonding wires 4, and on the surfaces of the parts of leads 3 planned to be sealed in a resin. The parts covered by the thin film 6 are sealed in a resin 5. This design enhances the bond with the resin 5, and moisture or impurities are prevented from penetrating along the interfaces. Packages are protected from cracks and improved in moisture-resistant feature.

Description

【発明の詳細な説明】 〔概　要〕 樹脂封止型半導体装置に係り、特に樹脂パッケージ内部
の熱ストレスの軽減と耐湿性を向上させる構造を持たせ
た樹脂封止型半導体装置に関し、パフケージクランクの
発生防止と、耐湿性の向上と、樹脂中のフィラーによる
損傷の軽減を図ることができる樹脂封止型半導体装置の
提供を目的とし、 半導体チップと、該半導体チップが固着されたダイステ
ージと、該半導体チップとボンディングワイヤにより接
続された外部導出用のリードとを有し、該半導体チップ
、ダイステージ、ボンディングワイヤの全表出面及び該
リードの封止領域全表面に少なくとも窒化チタン、炭化
シリコン、ダイヤモンドのいずれかのｆ！膜が被覆され
、該薄膜が被覆された部分が樹脂で封止されてなるよう
に構成する。[Detailed Description of the Invention] [Summary] The puff cage relates to a resin-sealed semiconductor device, and particularly to a resin-sealed semiconductor device having a structure that reduces thermal stress and improves moisture resistance inside the resin package. We aim to provide a resin-sealed semiconductor device that can prevent the occurrence of cranks, improve moisture resistance, and reduce damage caused by fillers in the resin. and a lead for leading to the outside connected to the semiconductor chip by a bonding wire, and at least titanium nitride or carbide is applied to the entire exposed surface of the semiconductor chip, the die stage, the bonding wire, and the entire surface of the sealing area of the lead. Either silicon or diamond f! The structure is such that the thin film is coated and the portion covered with the thin film is sealed with a resin.

〔産業上の利用分野〕[Industrial application field]

本発明は樹脂封止型半導体装置に係り、特に樹脂パッケ
ージ内部の熱ストレスの軽減と耐湿性を向上させる構造
を持たせた樹脂封止型半導体装置に関する。The present invention relates to a resin-sealed semiconductor device, and more particularly to a resin-sealed semiconductor device having a structure that reduces thermal stress inside a resin package and improves moisture resistance.

〔従来の技術〕[Conventional technology]

第４図は従来の樹脂封止型半導体装置の断面図を示す。 FIG. 4 shows a cross-sectional view of a conventional resin-sealed semiconductor device.

図において、１は半導体チ・ノブ、震よ半導体チップ１
がグイ付けされたダイステージ、３はリード（ダイステ
ージ２およびリード３は一体的に形成された図示しない
リードフレームの部分である）、４は半導体チ・ツブ１
の電極とり一ド３とを接続するボンディングワイヤー、
５番よ半導体チップ１を封止するための樹脂、＜ツケー
ジを示す。In the figure, 1 is a semiconductor chip, 1 is a semiconductor chip, and 1 is a semiconductor chip.
3 is a lead (the die stage 2 and lead 3 are integrally formed parts of a lead frame (not shown)), and 4 is a semiconductor chip 1.
a bonding wire connecting the electrode and the electrode 3;
No. 5 shows a resin for sealing the semiconductor chip 1.

かかる樹脂封止型半導体装置はモールド装置を用いる成
形方法によって一度に数十何件られる。Several dozen such resin-sealed semiconductor devices are manufactured at a time by a molding method using a molding device.

このような構造の樹脂封止型半導体装置の各＠ｂ分はそ
れぞれ異なる材料で作られている。例えＧｆ半導体チチ
タ１はシリコン、ダイステージ２４ま４２７０イ　（重
量比にてニッケル４２％、鉄５８％の合金）また封止の
ための樹脂パフケージ５は、エポキシ樹脂等とフィラー
（酸化珪素等）との混合物力く用いられるので、それぞ
れ膨張係数が異なる。Each part of the resin-sealed semiconductor device having such a structure is made of a different material. For example, the Gf semiconductor chip 1 is made of silicon, the die stage 24 or 4270 (an alloy of 42% nickel and 58% iron by weight), and the resin puff cage 5 for sealing is made of epoxy resin etc. and filler (silicon oxide etc.). Since they are often used in mixtures with each other, their expansion coefficients are different.

また、封止のために用いられる樹脂は、樹月旨封止形成
用の金型より離型し易くする離型剤力（含まれるため、
ダイステージ２やリード３のような金属と樹脂パッケー
ジ５との密着力は、半導体チップｌと樹脂パッケージ５
との密着力の１７２０〜１７３０程度と小さい。In addition, the resin used for sealing also contains a release agent that makes it easier to release from the mold for forming the seal.
The adhesion between metals such as the die stage 2 and leads 3 and the resin package 5 is determined by the adhesion between the semiconductor chip l and the resin package 5.
The adhesion strength is as low as 1720 to 1730.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

樹脂パフケージ５は、その使用時において温度変化によ
る熱応力を受け、温度サイクルが繰り返されると、樹脂
パッケージ５と密着力の低いダイステージ２の接合面に
おいては金属と樹脂間の膨張係数の差によりスリップ現
象が発生し、ダイステージ２が樹脂パッケージ５から剥
がれてくる。During use, the resin puff cage 5 is subjected to thermal stress due to temperature changes, and when temperature cycles are repeated, the bonding surface between the resin package 5 and the die stage 2, which has low adhesion, is exposed to thermal stress due to the difference in expansion coefficient between the metal and the resin. A slip phenomenon occurs, and the die stage 2 peels off from the resin package 5.

この隙間に水分が侵入すると実装時の熱ストレスで水分
が爆発し、樹脂パッケージ５のその縁部分にクランク（
ひび割れ）が発生する欠点があった。If moisture enters this gap, it will explode due to the heat stress during mounting, causing a crank (
It had the disadvantage of causing cracks.

また、半導体チップ１の電極（アルミニウム）を剥き出
しにしてボンディングワイヤー４をボンディングした接
続部分における剥き出しのアルミニウムと樹脂パッケー
ジ５とは殆ど密着しない性質がある。この接続部分に樹
脂パフケージ５に含まれた水分や不純物が、リードフレ
ーム、ボンディングワイヤー等を伝わって侵入し、アル
ミニウムを腐食させる欠点がある。Furthermore, there is a property that the exposed aluminum and the resin package 5 hardly come into close contact with each other at the connection portion where the electrode (aluminum) of the semiconductor chip 1 is exposed and the bonding wire 4 is bonded. There is a drawback that moisture and impurities contained in the resin puff cage 5 enter this connection portion through the lead frame, bonding wire, etc., and corrode the aluminum.

また、樹脂封止中に樹脂パッケージ５に含まれるフィラ
ーが比較的硬質の材料であるため半導体チタン１の表面
に損傷を与える欠点がある。Furthermore, since the filler contained in the resin package 5 is a relatively hard material during resin sealing, there is a drawback that the surface of the semiconductor titanium 1 is damaged.

本発明は上記従来の欠点に鑑みてなされたもので、パッ
ケージクランクの発生防止と、耐湿性の向上と、樹脂中
のフィラーによる損傷の軽減を図ることができる樹脂封
止型半導体装置の提供を目的とする。The present invention has been made in view of the above-mentioned conventional drawbacks, and aims to provide a resin-sealed semiconductor device that can prevent the occurrence of package cranks, improve moisture resistance, and reduce damage caused by fillers in the resin. purpose.

〔課題を解決するための手段〕[Means to solve the problem]

第１図は本発明の構成を示す断面図である。半導体チタ
ン１と、該半導体チップ１が固着されたダイステージ２
と、該半導体チップ１とボンディングワイヤ４により接
続された外部導出用のり一ド３とを有し、該半導体チッ
プ１．ダイステージ２、ボンディングワイヤ４の全表出
面及び該り−ド３の封止領域全表面に少なくとも窒化チ
タン炭化シリコン、ダイヤモンドのいずれかの薄膜６が
被覆され、該薄膜６が被覆された部分が、樹脂５で封止
されてなるように構成する。FIG. 1 is a sectional view showing the structure of the present invention. A semiconductor titanium 1 and a die stage 2 to which the semiconductor chip 1 is fixed.
and an external lead-out glue 3 connected to the semiconductor chip 1 by a bonding wire 4, the semiconductor chip 1. The entire exposed surface of the die stage 2, the bonding wire 4, and the entire surface of the sealing area of the die stage 3 are coated with at least a thin film 6 of either titanium nitride silicon carbide or diamond, and the portion covered with the thin film 6 is , and are sealed with resin 5.

〔作　用〕[For production]

ダイステージ２に半導体チップ１をグイボンディングし
、半導体チタン１とリード３とをワイヤーボンディング
したものの封止領域の表出面に、全面的に窒化チタン膜
、炭化シリコン膜、あるいはダイヤモンド膜のいずれか
を被膜し、それを樹脂封止することにより封止樹脂との
密着力を向上させると共に、界面への水分あるいは不純
物の侵゛入を防止し、耐湿性を向上させる。また、窒化
チタン膜、炭化シリコン膜、ダイヤモンド膜は比較的硬
質であるためフィラーによる損傷を防止できる効果があ
る。After the semiconductor chip 1 is firmly bonded to the die stage 2 and the semiconductor titanium 1 and the leads 3 are wire-bonded, either a titanium nitride film, a silicon carbide film, or a diamond film is entirely applied to the exposed surface of the sealing area. By forming a film and sealing it with resin, the adhesion with the sealing resin is improved, and the moisture resistance is improved by preventing moisture or impurities from entering the interface. Furthermore, since the titanium nitride film, silicon carbide film, and diamond film are relatively hard, they are effective in preventing damage caused by fillers.

〔実施例〕 以下本発明の実施例を図面によって詳述する。〔Example〕 Embodiments of the present invention will be described in detail below with reference to the drawings.

なお、構成、動作の説明を理解し易くするために全図を
通じて同一部分には同一符号を付してその重複説明を省
略する。Note that, in order to make the explanation of the configuration and operation easier to understand, the same parts are given the same reference numerals throughout all the figures, and repeated explanation thereof will be omitted.

第１図は本発明の構成を示す断面図、第２図は本発明の
製造方法を示す工程図、第３図はスパッタリング法によ
る窒化チタン膜形成工程の断面図を示す。以下各図を参
照しながら本発明の説明を行う。FIG. 1 is a sectional view showing the structure of the present invention, FIG. 2 is a process diagram showing the manufacturing method of the invention, and FIG. 3 is a sectional view showing the step of forming a titanium nitride film by sputtering. The present invention will be explained below with reference to each figure.

第１図において、６は薄膜であって窒化チタンＴｉＮ膜
、炭化シリコンＳｉＣ膜、またはダイヤモンドＣ膜のい
ずれか一つにて構成され、その被膜部分をリードフレー
ムの全面にハツチングを施して示す。その製造工程は第
２図に示すように工程■にてリードフレームを用意し、
工程■にて半導体チップ１をダイステージ２にグイボン
ディングする。工程■にて半導体チップ１とリード３と
の間をワイヤーボンディングする。In FIG. 1, a thin film 6 is made of one of a titanium nitride TiN film, a silicon carbide SiC film, or a diamond C film, and the film portion is shown hatched over the entire surface of the lead frame. As shown in Figure 2, the manufacturing process involves preparing a lead frame in step ①,
In step (2), the semiconductor chip 1 is bonded to the die stage 2. In step (2), wire bonding is performed between the semiconductor chip 1 and the leads 3.

工程■にて工程■まで形成されたリードフレームの全面
に窒化チタンＴｉＮ膜をスパッタリング法にて被覆する
か、または炭化シリコンＳｉＣ膜をプラズマ化学気相成
長法にて被覆するか、またはダイヤモンドＣ膜をプラズ
マ化学気相成長法にて被覆する。A titanium nitride TiN film is coated by a sputtering method, a silicon carbide SiC film is coated by a plasma chemical vapor deposition method, or a diamond C film is coated on the entire surface of the lead frame formed in step ② up to step ②. is coated using plasma chemical vapor deposition.

第３図は窒化チタン膜にて被覆する場合の工程の断面図
であって、図示するようにリードフレームに形成された
半導体チップ１．ダイステージ２゜リード３およびボン
ディングワイヤー４を治具７の上に２個所支持する。そ
の支持個所は被覆を必要としないリード３の露出部分に
対応している。FIG. 3 is a cross-sectional view of the process of coating with a titanium nitride film, and shows a semiconductor chip 1 formed on a lead frame as shown. Die stage 2° leads 3 and bonding wires 4 are supported at two locations on a jig 7. Its support points correspond to exposed parts of the leads 3 that do not require coating.

８と９はそれぞれ電極ＡとＢ１１０はチタンのターゲッ
トでこの電極間に所要の電圧が印加され、減圧０．１　
Ｔｏｒｒ　（アルゴンガス＋窒素ガス）、加熱温度２０
０〜２５０℃の環境にて厚さ１５００人程度０スパッタ
リング成膜が行われる。8 and 9, electrodes A and B110 are titanium targets, respectively, and the required voltage is applied between these electrodes, and the reduced pressure is 0.1.
Torr (argon gas + nitrogen gas), heating temperature 20
A sputtering film is formed to a thickness of about 1500 in an environment of 0 to 250°C.

炭化シリコン膜にて被覆する場合は、例えばＨ２゜Ｓｉ
Ｈ４，ＣＪｌｌ＋　ＨＣ１、Ａｒ等のガスを用い、４０
０〜５００℃、　１３．５６ＭＨ２または４ＭＨｚのプ
ラズマ化学気相成長法により厚さ５００〜２０００人程
度形成する以下た、ダイヤモンド膜により被覆する場合
は、例えばＣ）Ｉｔ＋Ｈ２，Ａｒ等のガスを用い、４０
０℃程度、数十Ｔｏｒｒ、　１３．５６ＭＨ２または４
ＭＨｚのプラズマ化学的気相成長法により厚さ５００〜
２０００人程度形成する以下のようにしてリードフレー
ムの全面に所要の被覆が出来上がると工程■にて、例え
ばトランスファモールド金型を用いて樹脂モールドを行
う。When covering with a silicon carbide film, for example, H2゜Si
Using gas such as H4, CJll+ HC1, Ar, etc., 40
When coating with a diamond film, which is formed to a thickness of about 500 to 2,000 layers by plasma chemical vapor deposition at 0 to 500°C and 13.56 MH2 or 4 MHz, for example, C) using a gas such as It+H2, Ar, etc. 40
Around 0℃, several tens of Torr, 13.56MH2 or 4
Thickness: 500~ by MHz plasma chemical vapor deposition method
When the required coating is completed on the entire surface of the lead frame in the following manner, resin molding is carried out using, for example, a transfer mold die in step (2).

このときリード３の露出部分には不要の膜が被覆される
から工程■にてホーニング法によりこれを取り除く。次
に工程■にてリード３の露出部分に半田メツキを施すこ
とにより完了する。At this time, the exposed portions of the leads 3 are covered with an unnecessary film, which is removed by honing in step (2). Next, in step (2), the exposed portions of the leads 3 are soldered to complete the process.

上記の工程を経由してできた樹脂封止型半導体装置の８
チツプのサンプルを無作為にて揃え、検査を行った結果
、塩酸浸漬によるマイクロクラックの初期不良数は零、
２気圧の水中に１００８時間浸漬後加熱試験によるパッ
ケージクランクの発生件数は零の成績が得られ、耐湿性
の良好なことが立証された。8. Resin-sealed semiconductor device made through the above process
As a result of randomly arranging chip samples and inspecting them, the number of initial defects due to microcracks caused by immersion in hydrochloric acid was zero.
A heating test after immersion in water at 2 atm for 1008 hours showed that the number of package cranks was zero, proving that the product had good moisture resistance.

とができる効果がある。There is an effect that can be done.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の構成を示す断面図、 第２図は本発明の製造方法を示す工程図、第３図はスパ
ッタリング法による窒化チタン膜形成工程の断面図、 第４図は従来の樹脂封止型半導体装置の断面図を示す。 第１図において、１は半導体チップ、２はダイステージ
、３はリード、４はボンディングワイヤ、５は樹脂パッ
ケージ、６は薄膜（窒化チタン膜、炭化シリコン膜、ま
たはダイヤモンド膜）をそれぞれ示す。 〔発明の効果〕 以上の説明から明らかなように本発明によれば、パッケ
ージクランクの発生防止と、耐湿性の向上と、樹脂中の
フィラーによる損傷の軽減を図るこ第 図 第 図Fig. 1 is a cross-sectional view showing the structure of the present invention, Fig. 2 is a process diagram showing the manufacturing method of the present invention, Fig. 3 is a cross-sectional view of the titanium nitride film forming process by sputtering method, and Fig. 4 is a conventional resin A cross-sectional view of a sealed semiconductor device is shown. In FIG. 1, 1 is a semiconductor chip, 2 is a die stage, 3 is a lead, 4 is a bonding wire, 5 is a resin package, and 6 is a thin film (titanium nitride film, silicon carbide film, or diamond film). [Effects of the Invention] As is clear from the above description, according to the present invention, it is possible to prevent the occurrence of package cranks, improve moisture resistance, and reduce damage caused by filler in the resin.

Claims (1)

【特許請求の範囲】 半導体チップ（１）と、該半導体チップ（１）が固着さ
れたダイステージ（２）と、該半導体チップ（１）とボ
ンディングワイヤ（４）により接続された外部導出用の
リード（３）とを有し、 該半導体チップ（１）、ダイステージ（２）、ボンディ
ングワイヤ（４）の全表出面及び該リード（３）の封止
領域全表面に少なくとも窒化チタン、炭化シリコン、ダ
イヤモンドのいずれかの薄膜（６）が被覆され、該薄膜
（６）が被覆された部分が、樹脂（５）で封止されてな
ることを特徴とする樹脂封止型半導体装置。[Claims] A semiconductor chip (1), a die stage (2) to which the semiconductor chip (1) is fixed, and a die stage (2) for external extraction connected to the semiconductor chip (1) by bonding wires (4). leads (3), and at least titanium nitride and silicon carbide are applied to the entire exposed surfaces of the semiconductor chip (1), the die stage (2), the bonding wires (4), and the entire surface of the sealing area of the leads (3). , a thin film (6) of diamond, and a portion covered with the thin film (6) is sealed with a resin (5).
JP63200742A 1988-08-11 1988-08-11 Resin sealed type semiconductor device Pending JPH0249456A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63200742A JPH0249456A (en) 1988-08-11 1988-08-11 Resin sealed type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63200742A JPH0249456A (en) 1988-08-11 1988-08-11 Resin sealed type semiconductor device

Publications (1)

Publication Number Publication Date
JPH0249456A true JPH0249456A (en) 1990-02-19

Family

ID=16429416

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63200742A Pending JPH0249456A (en) 1988-08-11 1988-08-11 Resin sealed type semiconductor device

Country Status (1)

Country Link
JP (1) JPH0249456A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448106A (en) * 1991-08-20 1995-09-05 Kabushiki Kaisha Toshiba Thin semiconductor integrated circuit device assembly

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448106A (en) * 1991-08-20 1995-09-05 Kabushiki Kaisha Toshiba Thin semiconductor integrated circuit device assembly
US5672908A (en) * 1991-08-20 1997-09-30 Kabushiki Kaisha Toshiba Thin semiconductor integrated circuit device assembly
US5767572A (en) * 1991-08-20 1998-06-16 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device assembly

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