JPS6151950A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPS6151950A JPS6151950A JP17607584A JP17607584A JPS6151950A JP S6151950 A JPS6151950 A JP S6151950A JP 17607584 A JP17607584 A JP 17607584A JP 17607584 A JP17607584 A JP 17607584A JP S6151950 A JPS6151950 A JP S6151950A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- filler
- semiconductor device
- passivation film
- filament
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
- H01L23/295—Organic, e.g. plastic containing a filler
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の技術分野］
この発明は樹脂封止型半導体装置に関し、特に、熱硬化
性樹脂と充填材とからなる熱硬化性樹脂組成物によって
半導体素子を封止した樹脂封止型半導体装置に関するも
のである。Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a resin-encapsulated semiconductor device, and in particular to a resin encapsulating a semiconductor element with a thermosetting resin composition comprising a thermosetting resin and a filler. The present invention relates to a sealed semiconductor device.
［従来技術］ 従来、この秒の装置として第１図に示すものがあった。[Prior art] Conventionally, there has been a device for this purpose as shown in FIG.
第１図は、従来の樹脂封止型半導体装置の一例で、大規
模集積回路のパッケージとして多用されているデュアル
・イン・ライン型パッケージ（以下、ＤＩＰと略記する
〉の断面図である。FIG. 1 is a cross-sectional view of a dual-in-line package (hereinafter abbreviated as DIP), which is an example of a conventional resin-sealed semiconductor device and is often used as a package for large-scale integrated circuits.
まず、第１図に示す従来の樹脂封止型半導体装置の構成
について説明する。図において、半導体素子２はロウ材
３によりダイパッド４に同性されている。半導体素子２
上にはアルミニウム配Ｊ３７が所定の間隔で形成されて
おり、アルミニウム配線７のボンディング・パッド部分
はボンディング・ワイヤ５によってリード・フレー１の
一端に接続されている。なあ、この接続工程をワイヤリ
ングという。半導体素子２の表面上には、半導体素子２
の表面を不活性化して保護するためのパッシベーション
膜８が形成されている。エポキシ樹脂６および充填材９
かうなる樹脂組成物によって、上述のリード・フレーム
１の端部と、半導体素子２と、ロウ材３と、ダイパッド
４と、アルミニウム配線７と、パッシベーション膜８と
、ボンディング・ワイヤ５とが一体に形成されている。First, the structure of the conventional resin-sealed semiconductor device shown in FIG. 1 will be explained. In the figure, a semiconductor element 2 is bonded to a die pad 4 by a brazing material 3. Semiconductor element 2
Aluminum interconnects J37 are formed on the top at predetermined intervals, and a bonding pad portion of the aluminum interconnect 7 is connected to one end of the lead fly 1 by a bonding wire 5. Hey, this connection process is called wiring. On the surface of the semiconductor element 2, the semiconductor element 2
A passivation film 8 is formed to inactivate and protect the surface. Epoxy resin 6 and filler 9
With this resin composition, the end of the lead frame 1, the semiconductor element 2, the brazing material 3, the die pad 4, the aluminum wiring 7, the passivation film 8, and the bonding wire 5 are integrated. It is formed.
次に、充填材９について説明する。充填材９としては石
英ガラス粉、ジルコン粉、アルミナ粉、マグネシア粉、
シリカ粉などを使用することができるが、特に大規模集
積回路においてはシリカ粉が従来から一般的に用いられ
ている。充填材を使用する目的については、特公昭５７
−１６７４３および特公昭５８−３３８２において詳細
に開示されており、以下に簡単に説明する。Next, the filler 9 will be explained. As the filler 9, quartz glass powder, zircon powder, alumina powder, magnesia powder,
Although silica powder or the like can be used, silica powder has been commonly used, particularly in large-scale integrated circuits. Regarding the purpose of using fillers,
-16743 and Japanese Patent Publication No. 58-3382, and will be briefly explained below.
上記充填材の線膨張係数は１．５Ｘ１０−５／℃以下で
あり、これらの充填材をエポキシ樹脂６に配合すること
により半導体素子２およびボンディング・ワイｌノ５の
線膨張係数に近い（直の線９張係数を有する（１１脂組
成物を得ることができる。したがって、エポキシ樹脂６
に充填材９として上述のシリカ粉などを配合したものを
成形材料として用いて半導体素子２を封止することによ
り、半導体装置の熱は載持性を改善することができる。The coefficient of linear expansion of the above-mentioned filler is 1.5×10-5/°C or less, and by blending these fillers with the epoxy resin 6, the coefficient of linear expansion of the semiconductor element 2 and bonding wire 5 is close to (directly) An epoxy resin composition having a linear tensile modulus of (11) can be obtained. Therefore, an epoxy resin 6
By sealing the semiconductor element 2 using a mixture of the above-mentioned silica powder and the like as the filler 9 as a molding material, it is possible to improve the heat retention of the semiconductor device.
充填材つとして通常用いられるシリカ粉は溶融シリカで
あるが、高い熱伝導性を必要とする場合には、結晶シリ
カが用いられ、特に大規模集積回路ではほとんどの場合
結晶シリカが用いられている。この結晶シリカはへき同
性を有するため、微粒粉にした場合鋭角の多面体となる
。The silica powder commonly used as a filler is fused silica, but when high thermal conductivity is required, crystalline silica is used, especially in large-scale integrated circuits, where crystalline silica is almost always used. . Since this crystalline silica has cleavage properties, when it is made into fine powder, it becomes a polyhedron with acute angles.
第２図は、第１図に示した樹脂封止型半導体装置におい
て微泣粉した結晶シリカを充填材として用いた場合のそ
の拡大断面図である。図において、参照番号２，３．４
．６，７．８．９は第１図と同一部分を示し、１ｏは大
規模集積回路の種類によって異なるが、通常は燐・ガラ
ス膜で形成されるスムースコートＩＩＩでおる。この図
においては、簡単のためスムースニート膜１０の下の梠
造を省略している。FIG. 2 is an enlarged sectional view of the resin-sealed semiconductor device shown in FIG. 1 in which finely powdered crystalline silica is used as a filler. In the figure, reference number 2, 3.4
．． 6, 7, 8, and 9 show the same parts as in FIG. 1, and 1o is usually a smooth coat III formed of a phosphorus/glass film, although it varies depending on the type of large-scale integrated circuit. In this figure, the structure under the smooth neat film 10 is omitted for simplicity.
ところで、特公昭５７−１６７４３、特公昭５８−３３
８２の各公報に開示されるように、エポキシ樹脂６に充
填材９を充填すると、次のような問題点を生じるおそれ
がある。すなわち、結晶シリカなどの充填材９は鋭角尉
造を有しているため、これが樹脂注入時の圧力（第２図
中の矢印方向）を受けてパッシベーションｖ８に突き刺
さり、その下のアルミニウム配線７やスムースコート膜
１０に達する可能性がある。その場合、外部から侵入し
た湿気が、パッシベーション膜８と充填材９との境界面
に伝わって、アルミニウム配線７やスムースコート膜１
０に達する。このため、アルミニウム配線７の腐蝕など
を招き、半導体装置のイ２頼性の上で問題が生じるおそ
れがある。但し、充Ｉｉ材９の外径寸法よりもパッシベ
ーション膜８の膜厚の方が厚い場合には、第２図かられ
かるように、充填材９がパッシベーション膜８中に埋も
れてしまい、樹脂注入時の圧力が緩和されて、充填材９
がアルミニウム配線７やスムースコート膜１０に達せず
にパッシベーション膜８中に留まってしまう。By the way, the special public service 57-16743, the special public service 58-33
As disclosed in each publication of No. 82, when the epoxy resin 6 is filled with the filler 9, the following problems may occur. In other words, since the filler material 9, such as crystalline silica, has an acute angle, it pierces the passivation v8 under pressure (in the direction of the arrow in FIG. 2) when the resin is injected, and the aluminum wiring 7 and the underlying aluminum wires 7. There is a possibility that it will reach the smooth coat film 10. In that case, moisture entering from the outside is transmitted to the interface between the passivation film 8 and the filler 9, and the aluminum wiring 7 and the smooth coat film 1
reaches 0. This may lead to corrosion of the aluminum wiring 7 and cause problems in terms of reliability of the semiconductor device. However, if the thickness of the passivation film 8 is thicker than the outer diameter of the filler material 9, the filler material 9 will be buried in the passivation film 8, as shown in FIG. When the pressure is relieved, the filling material 9
The particles remain in the passivation film 8 without reaching the aluminum wiring 7 or the smooth coat film 10.
従来の樹脂封止型半導体装置は以上のように（Ｒ成され
ているが、パッシベーション膜８の膜厚が１〜２ミクロ
ンであるのに対して、充填材９の外径寸法は最大数１０
ミクロンにわたって分布しているため、パッシベーショ
ン膜８に突き刺さった充填材９が下層のアルミニウム配
ｍ７やスムースコートＰＡ １０ ｋ： ’＞９してし
まうことがある。このため、半導体装置に外部からの水
分の浸入を誘発する可能性があり、その耐湿性や信傾性
が低下するおそれがあるという欠点があった。Conventional resin-sealed semiconductor devices are constructed as described above (R), but while the passivation film 8 has a thickness of 1 to 2 microns, the outer diameter of the filler 9 has a maximum thickness of several tens of microns.
Since the filler material 9 is distributed over microns, the filler material 9 that penetrates the passivation film 8 may damage the underlying aluminum layer m7 or the smooth coat PA 10 k: '>9. For this reason, there is a possibility that moisture may enter the semiconductor device from the outside, and there is a drawback that the moisture resistance and reliability of the semiconductor device may be deteriorated.
［発明の概鼓］
この発明は上記のような従来のものの欠点を除去するた
めになされたもので、それゆえに、この発明の主たる目
的は、樹脂封止の充＋１１ｔ材としてフィラメント状の
微細物を用いることにより、バッシベーション膜にノロ
傷を与えずかつ熱的・は械的特性の優れた樹脂封止型半
導体装置を提供することである。[Overview of the invention] This invention was made in order to eliminate the drawbacks of the conventional products as described above.Therefore, the main purpose of this invention is to use filament-like fine particles as a filler material for resin sealing. It is an object of the present invention to provide a resin-sealed semiconductor device which does not cause slag damage to a passivation film and has excellent thermal and mechanical properties.
［発明の実施例］
以下、この発明の一実施例を図によって説明する。第３
図は、この発明の一実施例ｒある樹脂封止型半導体装は
の断面図である。図において、参照番号２，３．４，６
．７．８．１０は第１図および第２図と同一部分を示す
。第３図に示した実施例の構成は、以下の点を除いて第
１図および第２図に示した従来の樹脂封止型半導体装置
の構成と同じである。すなわち、樹脂封止の充填材とし
て、従来のシリカ粉の代わりにプラズマＣＶＤ法（ｐｌ
ａｓｍａ Ｃｈｅｍｉｃａｌ ■ａｐｏｒ Ｑｅｐｏｓ
ｉＮｏｎ ）で作製したフィラメント状の微細シリコン
窒化物からなる充填材１８を使用していることである。[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Third
The figure is a sectional view of a resin-sealed semiconductor device according to an embodiment of the present invention. In the figures, reference numbers 2, 3, 4, 6
．． 7.8.10 shows the same parts as FIGS. 1 and 2. The structure of the embodiment shown in FIG. 3 is the same as the structure of the conventional resin-sealed semiconductor device shown in FIGS. 1 and 2 except for the following points. In other words, as a filling material for resin sealing, plasma CVD method (PL) is used instead of conventional silica powder.
asma Chemical ■apor Qepos
The filling material 18 is made of a filament-shaped fine silicon nitride made of iNon).
次に、この充填材の作用について説明する。充填材１８
は、その大きざが微細でしなやかなフィラメント溝道を
しているため、従来の鋭角構造の充填材のように、樹脂
注入時の圧力により充填材１８がパッシベーション膜８
に突き刺さることがないｌζめパッシベーション膜８へ
の損傷は全くなく、極めて熟的・驕械的特性の浸れた樹
脂封止型半導体装置を（ηることか−Ｃきる。Next, the action of this filler will be explained. Filler 18
Because the size of the filler 18 is fine and it has a flexible filament groove, the pressure during resin injection causes the filler 18 to form a passivation film 8, unlike a conventional filler with an acute angle structure.
There is no damage to the passivation film 8, and the resin-sealed semiconductor device, which has extremely sophisticated and mechanical characteristics, can be cut by (η) or -C.
次に、この充填月１８の作製方法について説明する。第
４図は、プラズマＣＶＤ法によりフィラメント状の微細
シリコン窒化物を作成するプラズマＣＶＤ装置の断面側
面図である。図において、石英反応チ１ｒンバ′１２の
上流側端にはガス導入孔＋ １が、その下流側端には真
空排気管１６が設けられでおり、真空排気管１６は真空
排気ポンプ１７に結合されている。石英反応チャンバ１
２の上流側には、その外周壁に沿って加熱用ヒータ′１
３が、その内周壁に沿って電極板１４が設りられている
。石英反応チャンバ１２の下ＦＡＣ側に警よ、その外周
壁に沿って冷却水バイブ１５が設けられている。コ８は
、プラズマ合成されたフィラメント状の微細シリコン窒
化物である。Next, a method for manufacturing the filled moon 18 will be explained. FIG. 4 is a cross-sectional side view of a plasma CVD apparatus for producing filament-like fine silicon nitride by plasma CVD. In the figure, a gas introduction hole +1 is provided at the upstream end of the quartz reaction chamber 1r'12, and a vacuum exhaust pipe 16 is provided at its downstream end, and the vacuum exhaust pipe 16 is connected to a vacuum pump 17. has been done. Quartz reaction chamber 1
On the upstream side of 2, a heating heater '1 is installed along its outer peripheral wall.
3, an electrode plate 14 is provided along its inner peripheral wall. A cooling water vibrator 15 is provided on the lower FAC side of the quartz reaction chamber 12 along its outer peripheral wall. 8 is a plasma-synthesized filament-like fine silicon nitride.
以上のように組成され１ζプラズマＣＶＤ装置において
、石英反応チャンバ１２の内部を真空排気管１６を通じ
て真空排気ポンプ１７で排気しつつガス導入孔１１から
反応ガス（たとえば、シランガスＳ＋Ｈ＜ とアンモニ
アガスＮＨ，）を流し、石英反応チャンバ１２の内部を
反応ガスで充満さｍｌ せてその圧力を０．５〜
数Ｔｏｒｒにする。この状態で、石英チャンバ１２の内
部の上流側のガスを加熱用ヒータ１３によって３００〜
５００℃に加熱し、その加熱雰囲気中で電極板１４に高
周波電圧を加えると、その部分の低圧ガスはｉｓされて
プラズマ状態となる。このプラズマ化されたガスが冷却
水バイブ１５で冷却された部分に流れて冷却されると、
低圧雰囲気中で反応ガスの結合反応が起こり平均径が１
ミクロン以下のフィラメント状の微細シリコン窒化物が
石英反応チャンバ１２の内周壁に堆積する。このフィラ
メント状の微細なシリコン窒化物は窒化シリコンに水素
が含有されたような組成で、ＬＳＩチップの表面のパッ
シベーション膜８に利用しているものと組成的には同じ
であるため、熱膨張率的には従来よく使用されてきた石
英粉末と同等の特性を示し、またエポキシ樹脂とのなじ
みも非常に良好である。In the 1ζ plasma CVD apparatus composed as described above, the inside of the quartz reaction chamber 12 is evacuated through the vacuum exhaust pipe 16 by the vacuum exhaust pump 17, and the reaction gas (for example, silane gas S+H<, ammonia gas NH, ) to fill the inside of the quartz reaction chamber 12 with the reaction gas and increase the pressure to 0.5 - ml.
Set it to several Torr. In this state, the gas on the upstream side inside the quartz chamber 12 is heated by the heater 13 to
When the electrode plate 14 is heated to 500° C. and a high frequency voltage is applied to the electrode plate 14 in the heated atmosphere, the low pressure gas in that area is turned into a plasma state. When this plasma gas flows to the part cooled by the cooling water vibrator 15 and is cooled,
In a low-pressure atmosphere, a bonding reaction of reaction gases occurs and the average diameter is 1.
Fine silicon nitride in the form of submicron filaments is deposited on the inner peripheral wall of the quartz reaction chamber 12 . This filament-shaped fine silicon nitride has a composition similar to silicon nitride containing hydrogen, and has the same composition as that used for the passivation film 8 on the surface of the LSI chip, so the coefficient of thermal expansion is In terms of characteristics, it exhibits properties equivalent to those of quartz powder that has been commonly used in the past, and is also very compatible with epoxy resin.
なお、上記実施例では、シランガスとアンモニアガスを
用いてプラズマＣＶＤ法によりフィラメント状の微細な
シリコン窒化物を作成し、これを充填材として利用する
場合についてｊホべたが、この充填材の線膨張係数を微
′７Ａ！するために、ガス中に一定ｍの酸素を混ぜて作
成した窒化物と醇化物の化合体（プラズマオキシナイト
ライド）を充填材として用いてもよいことは会うまでも
ない。In the above example, a filament-like fine silicon nitride was created by plasma CVD using silane gas and ammonia gas, and this was used as a filler. However, the linear expansion of this filler The coefficient is fine '7A! It goes without saying that a compound of nitride and moltenide (plasma oxynitride) prepared by mixing a certain amount of oxygen into a gas may be used as the filler.
［発明の効果］
以上のように、この発明によれば、樹脂封止の充填材と
してフィラメント状の微細物を用いるようにしたので、
パッシベーション膜に損１ｎを与えずかつ熱的・畷械的
特性の優れた樹脂封止型半導体装置を得ることができる
。[Effects of the Invention] As described above, according to the present invention, since filament-like fine particles are used as the filler for resin sealing,
It is possible to obtain a resin-sealed semiconductor device that does not cause loss to the passivation film and has excellent thermal and mechanical properties.
４、図面のｌ！ｌ？１ｔｒｉな説明
第１図は、従来の樹脂封止型半導体装置の一例の断面図
である。4.L of the drawing! l? Brief Description FIG. 1 is a sectional view of an example of a conventional resin-sealed semiconductor device.
第２図は、第１図に示した従来の樹脂封止型半導体装置
の拡大断面図である。FIG. 2 is an enlarged sectional view of the conventional resin-sealed semiconductor device shown in FIG.
第３図は、この発明の一実絶例である樹脂封止型半導体
装置の断面図である。FIG. 3 is a cross-sectional view of a resin-sealed semiconductor device which is an example of the present invention.
第４図は、プラズマＣＶＤ法によりフィラメント状の微
細シリコン窒化物を作成するプラズマＣＶＤ装置の断面
側面図である。FIG. 4 is a cross-sectional side view of a plasma CVD apparatus for producing filament-like fine silicon nitride by plasma CVD.
図において、１はリード・フレーム、２は半導体素子、
３はロウ材、４はダイパッド、５はボンディング・ワイ
ヤ、６はエポキシ樹脂、７はアルミニウム配線、８はパ
ッシベーション膜、９は充填材、１０はスムースコート
膜、１１はガス導入孔、１２は石英反応チャンバ、１３
は加熱用ヒータ、１４は電極板、１５は冷却水バイブ、
１６は真空排気管、１７は真空排気ポンプ、１８はフィ
ラメント状の微細シリコン窒化物の充填材である。In the figure, 1 is a lead frame, 2 is a semiconductor element,
3 is a brazing material, 4 is a die pad, 5 is a bonding wire, 6 is an epoxy resin, 7 is an aluminum wiring, 8 is a passivation film, 9 is a filler material, 10 is a smooth coat film, 11 is a gas introduction hole, 12 is quartz reaction chamber, 13
14 is a heating heater, 14 is an electrode plate, 15 is a cooling water vibrator,
16 is a vacuum exhaust pipe, 17 is a vacuum pump, and 18 is a filament-shaped fine silicon nitride filling material.
なお各図中同一符号は同一または相当部分を示すものと
する。Note that the same reference numerals in each figure indicate the same or corresponding parts.
代 理 人 大 岩 増 雄部１図
＄ ２ 図
２、発明の名称
樹脂封止型半導体装置
６． ３．補正をする者
代表者片山仁入部
三菱電機株式会社内
５、補正の対象
明細書の発明の詳細な説明の欄
６、補正の内容
（１） 明細再閉３頁第３行の「リード・フレー１の一
端に」を「リード・フレーム１の一端に」に補正する。Agent Masu Oiwa Figure 1 $ 2 Figure 2 Name of invention Resin-sealed semiconductor device 6. 3. Representative of the person making the amendment Hitoshi Katayama, Mitsubishi Electric Corporation 5, Detailed explanation of the invention in the specification subject to amendment 6, Contents of the amendment (1) Reclose the specification, page 3, line 3, ``Lead Frame''"at one end of lead frame 1" is corrected to "at one end of lead frame 1."
（２） 明細Ｇ第３頁第１２行の「一体に形成」を「一
体に成形」に補正する。(2) "Formed in one piece" on page 3, line 12 of Specification G is amended to "molded in one piece."
（３） 明細占第４頁第１７行の「微粒粉した」を「微
粒粉にした」に補正する。(3) In page 4, line 17 of the specification, "made into fine powder" is corrected to "made into fine powder."
以上 ’）ＡＩthat's all ’) AI
Claims (5)
らなり、前記半導体素子と、前記パッシベーション膜と
を封止する熱硬化性樹脂組成物とを含む樹脂封止型半導
体装置。(1) Consisting of a semiconductor element, a passivation film formed on the semiconductor element, a thermosetting resin, and a filler of filament-like fine particles, the semiconductor element and the passivation film are sealed. A resin-encapsulated semiconductor device comprising a thermosetting resin composition.
窒化物である特許請求の範囲第１項記載の樹脂封止型半
導体装置。(2) The resin-sealed semiconductor device according to claim 1, wherein the filament-like fine filler is silicon nitride.
酸化物の化合体である特許請求の範囲第１項記載の樹脂
封止型半導体装置。(3) The resin-sealed semiconductor device according to claim 1, wherein the filament-like fine filler is a combination of nitride and oxide.
マＣＶＤ法で作製する特許請求の範囲第１項または第２
項または第３項記載の樹脂封止型半導体装置。(4) The filament-like fine filler is produced by a plasma CVD method as claimed in claim 1 or 2.
The resin-sealed semiconductor device according to item 1 or 3.
の範囲第１項記載の樹脂封止型半導体装置。(5) The resin-sealed semiconductor device according to claim 1, wherein the thermosetting resin is an epoxy resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59176075A JP2579142B2 (en) | 1984-08-22 | 1984-08-22 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59176075A JP2579142B2 (en) | 1984-08-22 | 1984-08-22 | Resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6151950A true JPS6151950A (en) | 1986-03-14 |
| JP2579142B2 JP2579142B2 (en) | 1997-02-05 |
Family
ID=16007280
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59176075A Expired - Lifetime JP2579142B2 (en) | 1984-08-22 | 1984-08-22 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2579142B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63104455A (en) * | 1986-10-22 | 1988-05-09 | Oki Electric Ind Co Ltd | Filler for filling sealing resin and its manufacture |
| JPH0327892A (en) * | 1989-06-26 | 1991-02-06 | Kawasaki Steel Corp | Manufacture of fused flux |
| US5369299A (en) * | 1993-07-22 | 1994-11-29 | National Semiconductor Corporation | Tamper resistant integrated circuit structure |
| US5468990A (en) * | 1993-07-22 | 1995-11-21 | National Semiconductor Corp. | Structures for preventing reverse engineering of integrated circuits |
| US5475251A (en) * | 1994-05-31 | 1995-12-12 | National Semiconductor Corporation | Secure non-volatile memory cell |
| US6720656B2 (en) | 1998-12-21 | 2004-04-13 | Sharp Kabushiki Kaisha | Semiconductor device with analysis prevention feature |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5799759A (en) * | 1980-12-11 | 1982-06-21 | Matsushita Electric Ind Co Ltd | Manufacture of resin sealing type electronic part |
| JPS58140142A (en) * | 1982-02-16 | 1983-08-19 | Shin Etsu Chem Co Ltd | Composition of covering material for electronic parts |
| JPS5933319A (en) * | 1982-08-20 | 1984-02-23 | Shin Etsu Chem Co Ltd | Flame-retarding epoxy resin composition |
| JPS59108332A (en) * | 1982-12-14 | 1984-06-22 | Dainippon Ink & Chem Inc | Sealing method of electronic parts |
-
1984
- 1984-08-22 JP JP59176075A patent/JP2579142B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5799759A (en) * | 1980-12-11 | 1982-06-21 | Matsushita Electric Ind Co Ltd | Manufacture of resin sealing type electronic part |
| JPS58140142A (en) * | 1982-02-16 | 1983-08-19 | Shin Etsu Chem Co Ltd | Composition of covering material for electronic parts |
| JPS5933319A (en) * | 1982-08-20 | 1984-02-23 | Shin Etsu Chem Co Ltd | Flame-retarding epoxy resin composition |
| JPS59108332A (en) * | 1982-12-14 | 1984-06-22 | Dainippon Ink & Chem Inc | Sealing method of electronic parts |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63104455A (en) * | 1986-10-22 | 1988-05-09 | Oki Electric Ind Co Ltd | Filler for filling sealing resin and its manufacture |
| JPH0327892A (en) * | 1989-06-26 | 1991-02-06 | Kawasaki Steel Corp | Manufacture of fused flux |
| US5369299A (en) * | 1993-07-22 | 1994-11-29 | National Semiconductor Corporation | Tamper resistant integrated circuit structure |
| US5468990A (en) * | 1993-07-22 | 1995-11-21 | National Semiconductor Corp. | Structures for preventing reverse engineering of integrated circuits |
| US5821582A (en) * | 1993-07-22 | 1998-10-13 | National Semiconductor Corp. | Structures for preventing reverse engineering of integrated circuits |
| US5475251A (en) * | 1994-05-31 | 1995-12-12 | National Semiconductor Corporation | Secure non-volatile memory cell |
| US6720656B2 (en) | 1998-12-21 | 2004-04-13 | Sharp Kabushiki Kaisha | Semiconductor device with analysis prevention feature |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2579142B2 (en) | 1997-02-05 |
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