JPS59231840A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS59231840A
JPS59231840A JP58106452A JP10645283A JPS59231840A JP S59231840 A JPS59231840 A JP S59231840A JP 58106452 A JP58106452 A JP 58106452A JP 10645283 A JP10645283 A JP 10645283A JP S59231840 A JPS59231840 A JP S59231840A
Authority
JP
Japan
Prior art keywords
semiconductor device
pads
silicon nitride
nitride film
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58106452A
Other languages
Japanese (ja)
Other versions
JPH0142629B2 (en
Inventor
Shunpei Yamazaki
舜平 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP58106452A priority Critical patent/JPS59231840A/en
Publication of JPS59231840A publication Critical patent/JPS59231840A/en
Publication of JPH0142629B2 publication Critical patent/JPH0142629B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
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    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain a semiconductor device having high humidity resistance by a method wherein the surfaces of a semiconductor chip, pads and wires are covered with Si3N4 films, and moreover sealed with a plastic material. CONSTITUTION:Si3N4 films are deposited on the respective surfaces of a chip 26 adhered closely on a die 28, the Al pads 38 thereof, and Au wirings 27 between the pads 38 and stems 35, and especially deposited carefully on the surfaces of the Au wires in the neighborhood of the pads. The Si3N4 film is formed according to the plasma vapor phase method by introducing silicide gas and NH3 gas in a reaction oven at 150-250 deg.C, and after deposited at about 1,000Angstrom film thickness, sealed with epoxy resin. A large quentity of Cl2 survive in the sealing material, converted into Cl ions according to invasions 33, 34, 31 of water from the bulk, from the surfaces of the wirings 27 or from cracks, and react with Al to generate corrosion and disconnection, but because the Al pads 38 especially are protected completely by the Si3N4 film having a large masking effect to water and Cl, the semiconductor device formed according to this construction presents high humidity resistance, and corrosion of the Al and disconnection are not generated.

Description

【発明の詳細な説明】 この発明は半導体装置の封止に関する。[Detailed description of the invention] The present invention relates to the sealing of semiconductor devices.

この発明は、プラスチック・モーールド封止に関し、窒
化珪素膜を半導体チップ（トランジスタまたはそれが複
数個集積化された半導体装置を以下チップという）の表
面のみならず、ワイヤボンド用パッドにボンディングさ
れた金相ＩＪｎ　（２５＃φ）の少なくともバンド近傍
にコーティングすることにより、アルミニューム・パッ
ドまたはチップ内の５〜１０μ中のり一ト等でのコロ−
ジョン（ｇ食）を防くことを目的としている。The present invention relates to plastic mold encapsulation, in which silicon nitride film is applied not only to the surface of a semiconductor chip (a semiconductor device in which a plurality of transistors or transistors are integrated is hereinafter referred to as a chip), but also to a metal bonded to a wire bond pad. By coating at least the vicinity of the band of phase IJn (25 #φ), it is possible to coat the aluminum pad or the 5 to 10μ glue in the chip.
The purpose is to prevent G-eating.

この発明は、プラスチック・モールド・パッケージにお
いて、信頼性の低下をする水等の湿度が単にプラスチッ
ク・パッケージのバルクのみならず、ワイヤを伝わり侵
入する水、リードフレームの表面を伝わって侵入する水
に対しても、ブロッキング効果を有した、高信頼性の半
導体装置を設けたごとを特徴としている。In plastic molded packages, the present invention is designed to prevent moisture such as water that reduces reliability not only from the bulk of the plastic package, but also from water that enters through wires and water that enters through the surface of the lead frame. It is also characterized by the provision of a highly reliable semiconductor device that has a blocking effect.

この発明は窒化珪素のファイナル・コーティングをウェ
ハ・レベルにて行うのではなく、チップをグイボンディ
ング（ダイアタッチともいう）し、さらにワイヤ・ボン
ディングを完了した後、チップ表面のみならすワイヤお
よびアルミニューム・パッドに対しても、同時に３００
　℃以下好ましくは１００〜２５０℃の温度でプラズマ
気相法、光プラズマ気相法または元気相法により行うご
とにより、これら全ての表面に窒化珪素膜コーティング
を施し、その後にプラスデック・モールド処理にょる封
止を行うことを特徴としている。Rather than performing the final coating of silicon nitride at the wafer level, the present invention involves bonding (also known as die attach) the chips, and after completing the wire bonding, the final coating of silicon nitride is not performed at the wafer level. 300 at the same time against the pad.
A silicon nitride film coating is applied to all these surfaces by plasma vapor phase method, optical plasma vapor phase method, or energetic phase method at a temperature of preferably 100 to 250 degrees Celsius or less, and then a plus deck molding process is applied. It is characterized by its sealing.

従来、チップのファイナル・コーティングは、ウェハ・
レベルにて行っていた。このため、その後工程にくるワ
イヤ・ボンディング用のパッド部のアルミニューム（一
般には１００μＸ１００μ）は、エポキシ・モールド一
部に露呈してしまっていた。Traditionally, the final coating of a chip is performed on a wafer.
I was on the level. For this reason, the aluminum (generally 100 .mu.x100 .mu.) of the pad portion for wire bonding in the subsequent process was exposed on a portion of the epoxy mold.

このため、第１図に示ずごときプラスチック製ＤＩ＋”
　　（ディアル・イン・パッケージ）において、プラス
チック（３６）のバルク（３３）がらの水（湿度）の侵
入に対しては、窒化珪素（３０）はブロッキング効果を
有するが、ワイヤを伝わる侵入（３４）、さらにリード
フレーム（３７）とモールド（３６）との界面でのクラ
ンク（３２）からの侵入（３１）に対しては、まったく
効果を有さないことが判明した。For this reason, a plastic DI+'' as shown in Figure 1 is used.
(Dial-in-Package), silicon nitride (30) has a blocking effect against water (humidity) intrusion into the bulk (33) of plastic (36), but it prevents intrusion (34) through wires. Furthermore, it was found that it had no effect at all against intrusion (31) from the crank (32) at the interface between the lead frame (37) and the mold (36).

このためアルミニューム・パッド（３８）はコロ−ジョ
ンを起こしやすく、半導体装置の特性劣化、信頼性低下
を誘発してしまっていた。For this reason, the aluminum pad (38) is prone to corrosion, leading to deterioration of characteristics and reliability of the semiconductor device.

特にモールド材例えば七−トン社の４１０Ｂ工ポキシモ
ールＦ月を用いた場合、そのモールド材中に塩素が多量
に残存し、水により塩素イオンとなりアルミニュームと
反応し、コロー−ジョン（ｗＪ食）を起こし、アルミニ
ュームが水酸化アルミニュームとなり断線してしまう。In particular, when using a molding material such as 410B Poxymol F from Nanaton Co., Ltd., a large amount of chlorine remains in the molding material, and when exposed to water, it becomes chlorine ions and reacts with aluminum, causing corrosion (wJ corrosion). The aluminum turns into aluminum hydroxide and the wire breaks.

そのためその半導体装置としての信頼性低下が著しかっ
た。As a result, the reliability of the semiconductor device was significantly lowered.

また、フレームをリード部において曲げかっタイバーを
切断する際起こりやすいリードフレームとエポキシモー
ルドとの接着面でのクラック（３２）からの水の侵入に
よるパッド部でのコロ−ジョンの発生には、まったくの
無防備であった。In addition, it completely prevents corrosion at the pad section due to water intrusion from cracks (32) at the bonding surface between the lead frame and epoxy mold, which tend to occur when bending the frame at the lead section or cutting the tie bar. was defenseless.

本発明はかかる従来のｌ）　ｌ　１１におきる信頼性の
低下を防ぐためになされたものである。The present invention has been made in order to prevent the deterioration in reliability that occurs in the conventional method.

第２図は本発明構造のプラスチックＤＩＰの縦断面図を
示す。FIG. 2 shows a longitudinal sectional view of a plastic DIP having the structure of the present invention.

図面において、グイ（２８）に密着させたチップ（２６
）と、このチップのアルミニューム・パッド（３８）と
ステム（３５）との間に金線のワイヤボンドを行い、さ
らにこのチップ（２６）表面、パッド（３８）表面、ワ
イヤ表面（特にパッド近傍表面）にりＩし、窒化珪素膜
り３０）のコーティングを行う。In the drawing, the tip (26) is in close contact with the guide (28).
) and the aluminum pad (38) of this chip and the stem (35). The surface) is coated with a silicon nitride film 30).

さらに好ましくはワイヤ全体のみならずステム（３５）
　１面およびそこにボンディングされたワイヤの表面に
対しても、コーチインクをしたものである。More preferably, not only the entire wire but also the stem (35)
Coach ink was applied to one side and also to the surface of the wire bonded thereto.

ごの窒化珪素膜は１００〜３００　’ｃ好ましくは１５
０〜２５０℃の温度におい“ζ、珪化物気体とアンモニ
アとを反応炉に導入し、そごに電気エネルギーまｔ二は
光エネルギーを供給するいわゆるプラズマ気相法、フメ
ト・プラズマ気相法またはフォトＣＶＤ法により形成セ
しめた。The silicon nitride film is preferably 100~300'c
At a temperature of 0 to 250°C, silicide gas and ammonia are introduced into the reactor, and electrical energy or light energy is supplied to the reactor using the so-called plasma vapor phase method, fumet plasma vapor phase method, or The formation was completed by photo-CVD method.

かくの如（して、窒化珪素膜を３００〜２５００人、一
般には約１０００人の）ソーさに形成した後、公知のイ
ンジェクンヨン・モールｌ−法によりエポキシ（例えば
４１０Ｂ）モールｌ−法により注入・封止さゼた。After forming the silicon nitride film in this way (300 to 2,500 people, generally about 1,000 people), epoxy (for example, 410B) is coated with epoxy (for example, 410B) by the Mohr method using the well-known Injector-Mohr method. Injected and sealed.

さらにフレームをリート部（３７）にて曲げ、かつタイ
バーを切断する。さらにリード部を酸洗いを行った後、
リードにハンダメッキを行った。Furthermore, the frame is bent at the leat portion (37) and the tie bars are cut. Furthermore, after acid-washing the lead part,
I solder plated the leads.

かかる本発明の半導体装置の構造において、信頼性が低
下をするモールドバルクからの水の侵入（３３）、ワイ
ヤ（２７）表面を伝わる侵入（３４）、クラック（３２
）からの水の侵入（３１）のすべてに対しコロ−ジョン
を防くことができるようになった。In the structure of the semiconductor device of the present invention, reliability is reduced due to water intrusion from the mold bulk (33), intrusion through the wire (27) surface (34), and cracks (32).
) Corrosion can now be prevented against all types of water intrusion (31).

特にアルミニューム・パッド（３８）の全ての表面が直
接モールド′材に露呈・接触していない、加えて窒化珪
素膜は水、塩素に夕１するブロッキング効果（マスク効
果）が大きい。このため本発明構造の半導体においては
、ＰＣＴ　　（プレッシャー・クツカー・テスト）　１
０ａｔｏｍ、１００時間、１５０°Ｃの条件下において
も、まったく不良が観察されず、従来のＩＣチップが５
０〜１００フィツトの不良率を有していたが、５〜】０
フイツトにまでその不良率を下げることが可能器こなっ
た。In particular, the entire surface of the aluminum pad (38) is not directly exposed or in contact with the mold material, and in addition, the silicon nitride film has a large blocking effect (mask effect) against water and chlorine. Therefore, in the semiconductor having the structure of the present invention, PCT (Pressure Cutcher Test) 1
Even under conditions of 0 atoms, 100 hours, and 150°C, no defects were observed, and conventional IC chips
It had a defective rate of 0 to 100 fits, but 5 to ]0
It has now become possible to reduce the defective rate to the point where it fits.

第３図は本発明のチップがフレームにボンディングされ
た構造にて、ブラスマＣＶＤ法により窒化珪素膜のコー
ティングを行うための装置の概要を示す。FIG. 3 shows an outline of an apparatus for coating a silicon nitride film by the plasma CVD method in a structure in which the chip of the present invention is bonded to a frame.

図面において、反応系（６）、ドーピング系（５）を有
している。In the drawing, it has a reaction system (6) and a doping system (5).

反応系は、反応室（１）と予備室（７）とを有し、ゲー
メ弁（９）１８　）とを有している。反応室（１）は一
対のハロゲンヒータ（２２）を有し、その内側に供給側
フードを有し、ツーＦ　（１３）のノズルより入口側（
３）よりの反応性気体を下方向に吹き出し、反応をさセ
、被膜形成を行った。反応後は排出側フード（１４）よ
り排気口（４）を経てバルブ（２１）、真空ポンプ（２
０）に至る。高周波電源（１００周波数１００〜５００
ＫＩＩｚ）より、電気エネルギーは一対の網状電極（Ｈ
ａ、（１２）により反応性気体に供給される。被膜の被
形成体（２）（以下基板（２）という）は絶縁ザボーク
（４１）上に配設された枠構造のホルダー（４０）内に
平行に一定の間隔（例えば５ｃｍ　）を有して配設され
ている。この基板（２）は、グロー放電により作られる
プラズマ中の陽極柱内に配設され、電気的にいずれの電
極（１１）、＜１２）からもフローティング構造を有し
ている。The reaction system has a reaction chamber (1), a preliminary chamber (7), and a game valve (9). The reaction chamber (1) has a pair of halogen heaters (22), has a supply side hood inside thereof, and has a side hood on the inlet side (
3) The reactive gas was blown out downward to stop the reaction and form a film. After the reaction, the discharge side hood (14) passes through the exhaust port (4) to the valve (21) and the vacuum pump (2).
0). High frequency power supply (100 frequency 100~500
KIIz), electrical energy is transferred to a pair of mesh electrodes (H
a, (12) supplies the reactive gas. The object (2) on which the film is to be formed (hereinafter referred to as the substrate (2)) is arranged in parallel at a constant interval (for example, 5 cm) in a frame-structured holder (40) disposed on the insulating Zabok (41). It is arranged. This substrate (2) is disposed within an anode column in plasma created by glow discharge, and has a floating structure electrically away from any of the electrodes (11), <12).

反応性気体はフード（１３）より枠構造のホルダ（４０
）の内側およびツーＦ　（１４）により囲まれた内側に
てプラズマ活性状態で基板上に被膜形成がなされ、フレ
ークが反応室内で作られないようにさせている。The reactive gas is transferred from the hood (13) to the frame-structured holder (40).
) and surrounded by 2F (14), a coating is formed on the substrate in a plasma active state to prevent flakes from being created in the reaction chamber.

第３図に示すごとき本発明方法におけるｐｃｖｏ法は、
基板が電極的にフローティングであるフローティング・
プラズマ気相法（ＦＴ”ＣＶＤ　）法であるため、基板
の一部に導体を用いても、放電が不安定になることはな
いという特長を有する。The pcvo method in the method of the present invention as shown in FIG.
Floating, where the substrate is electrode-floating.
Since it is a plasma vapor phase deposition (FT"CVD) method, it has the advantage that even if a conductor is used in part of the substrate, the discharge will not become unstable.

ドーピング系は珪化物気体であるシランまたはジクロー
ルシランを（１７）より、また窒化物気体であるアンモ
ニアを（１６）より、キャリアガスでる窒素または水素
を（１５）より供給している。それらは流量＠（−（１
８）、バルブ（■９）により制御している。The doping system supplies silicide gas silane or dichlorosilane from (17), nitride gas ammonia from (16), and carrier gas nitrogen or hydrogen from (15). They are the flow rate @(-(1
8) and is controlled by a valve (■9).

例えば基板温度を２２０℃±Ｈｉ’Ｃとし、Ｎｌｌ〆５
ｉｌ（４＝２０とした。さらに２００ＫＩＩｚの１ｍ波
数により１００Ｗの出力を供給した。かくして平均１ｏ
ｏｏ人（１０００人士２００人）に約１５分の被膜形成
を行った。For example, if the substrate temperature is 220℃±Hi'C, Nll〆5
il (4=20.Furthermore, a 1m wave number of 200KIIz provided an output of 100W. Thus, an average of 1o
Film formation was performed on 200 people out of 1000 people for about 15 minutes.

ホルダー（４０）は枠の内側の大きさ６０ｃｍ　Ｘ　６
０ｃｍを有し、電極間距離は３０ｃｍ　（有効２０ｃｍ
　＞としている。The holder (40) has an inside size of 60cm x 6.
0cm, and the distance between the electrodes is 30cm (effective 20cm
>.

また第３図の基板（２）の部分を拡大した図面を第４図
に示す。FIG. 4 shows an enlarged view of the substrate (2) in FIG. 3.

第４図において、（Ａ）はザボータ（２３）の両表面に
コパール製フレーム（４０）のバンドにデツプ（２６）
をダイアタッチし、さらに千ノブのアルミニューム・バ
ンドとステム（２５）間にワイヤポンド“（２７）さ（
たフレームを配設している。In Fig. 4, (A) shows that the band of the copal frame (40) has a depth (26) on both surfaces of the zabota (23).
Attach a wire pound (27) between the 1,000-knob aluminum band and the stem (25).
A frame is installed.

グー１−フレーム（４０）において、少なくともり〜ド
とする領域に対しては、フレーム（４０）の保持を兼ね
たカバー（２４）にて覆い、このリード部に窒化珪素膜
が形成されないようにしている。Goo 1 - At least the region of the frame (40) to be lead is covered with a cover (24) that also serves to hold the frame (40) to prevent a silicon nitride film from forming on this lead part. ing.

フレーム（４０）はこのカバー（２４）のため、第４図
（Ｃ）の領域（２９）のみに窒化珪素膜が形成され、領
域（２５）には窒化珪素膜を形成さセないことがきわめ
て重要である。Because the frame (40) has this cover (24), a silicon nitride film is formed only in the region (29) in FIG. 4(C), and it is extremely important that no silicon nitride film is formed in the region (25). is important.

第４図（Ｃ）は、リード部の下側を省略した１６ピンの
例を示している。しかしこの形状以外の任意のピン数、
形状を同様に有せしめることが可能であることばいうま
でもない。FIG. 4(C) shows an example of 16 pins in which the lower part of the lead part is omitted. However, any number of pins other than this shape,
Needless to say, it is possible to have a similar shape.

第４図（Ｂ）は（Ａ）におけるサボ〜り（２３）を省略
したものである。同様にチップ（２６）の近傍のみを選
択的に窒化珪素膜でコーティングをし、リード部にはコ
ーティングされないようにリードのカバー（２４）がフ
レームの保持を兼ねて設りられている。In FIG. 4(B), the skipping (23) in FIG. 4(A) is omitted. Similarly, only the vicinity of the chip (26) is selectively coated with a silicon nitride film, and a lead cover (24) is provided to also hold the frame so that the lead portions are not coated.

しかし第３図のＦＰＣＶＤ法においては、グロー放電を
させ、各フレームムこ初期の電荷がチャージアップした
後は、チャージがリークすることがないため、絶縁膜上
に被膜を形成させる場合とまったく同様に窒化珪素膜を
コーティングすることができるという特長を有する。However, in the FPCVD method shown in Figure 3, after the initial charge is charged up in each frame by glow discharge, there is no charge leakage, so it is exactly the same as when forming a film on an insulating film. It has the advantage that it can be coated with a silicon nitride film.

即ち、本発明の作製方法は、単に窒化珪素膜をワイヤポ
ンドした後にコーティングするという特長を有するのめ
ならず、パッド、チップ表面に対しても均一な膜厚をコ
ーティングするため、ＦＰＣＶＤ法を用いたことを他の
特長としている。That is, the manufacturing method of the present invention not only has the feature of simply coating the silicon nitride film after wire-pounding it, but also uses the FPCVD method to coat the pad and chip surfaces with a uniform thickness. Another feature is that

なお本発明においては、Ｆ　１１　ＣＶ　ｌ）法におい
て、電気エネルギーのみならず、１０〜１５μの波長の
遠赤外または３００ｎｍ以下の紫外光を同時に加えたフ
ローティングであって、かつ光エネルギーを用いるフλ
１〜ｃｖｎ　　＜またはフォトＦＩＩＣＶＤ　）法を用
いることは有効である。In addition, in the present invention, in the F 11 CV l) method, not only electric energy but also floating light energy, which is a floating method that simultaneously applies far infrared light with a wavelength of 10 to 15 μ or ultraviolet light of 300 nm or less, is used. λ
It is effective to use the photo-FII CVD method.

また第３図において、ハロゲンランプの加熱装置（２２
）の一部を紫外光の発生源とすることにより可能とする
ことができる。In addition, in FIG. 3, a heating device (22
) can be made possible by using a part of the ultraviolet light as a source of ultraviolet light.

【図面の簡単な説明】 第１図は従来のデュアル・イン・ライン製プラスチック
・パッケージ半導体装置を示す。 第２図は本発明のデュアル・イン・ライン製プラスチッ
ク・パッケージ半導体装置を示す。 第３図は本発明方法を実施するためのフローティング・
プラズマ気相反応装置の概要を示す。 第４図は第３図の装置のうちの基板部の拡大図を示す。 特許出願人 翠１１辺 ｊＡｐｔの タ　　　　　　　　　　　　　　　　　　　Ｃノｙ（２
） （Ａ）　　　　（β）BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a conventional dual-in-line plastic packaged semiconductor device. FIG. 2 shows a dual-in-line plastic packaged semiconductor device of the present invention. FIG. 3 shows a floating structure for carrying out the method of the present invention.
An overview of the plasma gas phase reactor is shown. FIG. 4 shows an enlarged view of the substrate portion of the apparatus shown in FIG. Patent applicant Midori 11 side jApt's Ta Cnoy (2
) (A) (β)

Claims (1)

【特許請求の範囲】 １、リードフレームに配設された半導体チップと、該チ
ップのボンディング用バンドと、前記リードフレームの
ステ広間にワイヤボンドがなされた半導体装置において
、前記半導体チップ表面、バンド表面およびワイヤ表面
を窒化珪素膜により覆うとともに、該窒化珪素膜を包ん
でプラスチック材によりモールドせしめたことを特徴と
する半導体装置。 ２、リードフレームに配設された半導体チップと、該チ
ップのボンディング用パッドと、前記リードフレームの
ステ広間にワイヤボンドがなされた半導体装置を、減圧
下の雰囲気内に保持し、珪化物気体と窒化物気体とを導
入し、電気エネルギーまたは光エネルギーを供給するこ
とにより、半導体チップ表面、バンド表面およびワイヤ
表面を窒化珪素膜により覆うとともに、該窒化珪素膜を
包んでプラスチック・モールドにて封止することを特徴
とする半導体装置作製方法。[Scope of Claims] 1. A semiconductor device in which a wire bond is made between a semiconductor chip disposed on a lead frame, a bonding band of the chip, and a step space of the lead frame, wherein the semiconductor chip surface, the band surface and a semiconductor device characterized in that the wire surface is covered with a silicon nitride film, and the silicon nitride film is wrapped and molded with a plastic material. 2. A semiconductor chip disposed on a lead frame, a semiconductor device with wire bonds made between the bonding pad of the chip and the step hole of the lead frame are held in a reduced pressure atmosphere, and a silicide gas is By introducing nitride gas and supplying electrical energy or light energy, the semiconductor chip surface, band surface, and wire surface are covered with a silicon nitride film, and the silicon nitride film is wrapped and sealed with a plastic mold. A semiconductor device manufacturing method characterized by:
JP58106452A 1983-06-14 1983-06-14 Semiconductor device and manufacture thereof Granted JPS59231840A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58106452A JPS59231840A (en) 1983-06-14 1983-06-14 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58106452A JPS59231840A (en) 1983-06-14 1983-06-14 Semiconductor device and manufacture thereof

Related Child Applications (3)

Application Number Title Priority Date Filing Date
JP63110193A Division JPS63313829A (en) 1988-05-06 1988-05-06 Manufacture of semiconductor device
JP1031960A Division JPH02346A (en) 1989-02-10 1989-02-10 Semiconductor device
JP1031959A Division JPH02345A (en) 1989-02-10 1989-02-10 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS59231840A true JPS59231840A (en) 1984-12-26
JPH0142629B2 JPH0142629B2 (en) 1989-09-13

Family

ID=14433990

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58106452A Granted JPS59231840A (en) 1983-06-14 1983-06-14 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS59231840A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01292846A (en) * 1988-05-19 1989-11-27 Semiconductor Energy Lab Co Ltd Manufacture of electronic device
EP0349318A2 (en) * 1988-07-01 1990-01-03 Gec-Marconi Limited Methods of making integrated circuit packages
EP0354056A2 (en) * 1988-08-05 1990-02-07 Semiconductor Energy Laboratory Co., Ltd. Coated electric devices and methods of manufacturing the same
JPH02102564A (en) * 1988-10-12 1990-04-16 Semiconductor Energy Lab Co Ltd Electronic device and manufacture thereof
JPH02106941A (en) * 1988-10-17 1990-04-19 Semiconductor Energy Lab Co Ltd Manufacture of electronic device
JPH02106953A (en) * 1988-10-17 1990-04-19 Semiconductor Energy Lab Co Ltd Member for electronic device
US5096851A (en) * 1988-05-19 1992-03-17 Semiconductor Energy Laboratory Co., Ltd. Method of packaging an electronic device using a common holder to carry the device in both a cvd and molding step

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5771137A (en) * 1980-10-22 1982-05-01 Oki Electric Ind Co Ltd Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5771137A (en) * 1980-10-22 1982-05-01 Oki Electric Ind Co Ltd Manufacture of semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01292846A (en) * 1988-05-19 1989-11-27 Semiconductor Energy Lab Co Ltd Manufacture of electronic device
US5096851A (en) * 1988-05-19 1992-03-17 Semiconductor Energy Laboratory Co., Ltd. Method of packaging an electronic device using a common holder to carry the device in both a cvd and molding step
EP0349318A2 (en) * 1988-07-01 1990-01-03 Gec-Marconi Limited Methods of making integrated circuit packages
EP0349318A3 (en) * 1988-07-01 1990-08-16 Gec-Marconi Limited Methods of making integrated circuit packages
EP0354056A2 (en) * 1988-08-05 1990-02-07 Semiconductor Energy Laboratory Co., Ltd. Coated electric devices and methods of manufacturing the same
JPH02102564A (en) * 1988-10-12 1990-04-16 Semiconductor Energy Lab Co Ltd Electronic device and manufacture thereof
JPH02106941A (en) * 1988-10-17 1990-04-19 Semiconductor Energy Lab Co Ltd Manufacture of electronic device
JPH02106953A (en) * 1988-10-17 1990-04-19 Semiconductor Energy Lab Co Ltd Member for electronic device

Also Published As

Publication number Publication date
JPH0142629B2 (en) 1989-09-13

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