JPH0276249A - Electronic device and manufacture thereof - Google Patents

Electronic device and manufacture thereof

Info

Publication number
JPH0276249A
JPH0276249A JP63227166A JP22716688A JPH0276249A JP H0276249 A JPH0276249 A JP H0276249A JP 63227166 A JP63227166 A JP 63227166A JP 22716688 A JP22716688 A JP 22716688A JP H0276249 A JPH0276249 A JP H0276249A
Authority
JP
Japan
Prior art keywords
electronic device
organic substance
die
lead frame
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63227166A
Other languages
Japanese (ja)
Inventor
Shunpei Yamazaki
舜平 山崎
Kazuo Urata
一男 浦田
Naoki Hirose
直樹 広瀬
Itaru Koyama
小山 到
Shinji Imato
今任 慎二
Kazuhisa Nakashita
中下 一寿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP63227166A priority Critical patent/JPH0276249A/en
Publication of JPH0276249A publication Critical patent/JPH0276249A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135Double encapsulation or coating and encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent the occurrence of re-release from an organic substance into a molding agent by fixing an electronic part and the organic substance on a substrate or a lead frame and by coating these elements including the organic substance with an inorganic protecting film. CONSTITUTION:A chip 28 made to adhere to a die 35' of a lead frame by silver paste 24 containing an organic substance, or the like, is provided, and wire- bonding of a gold wire 39 is made between an aluminum pad 38 of this chip 28 and a stem 35. An unnecessary gaseous component in organic substances 24 and 24' is deaerated from the surface of said chip 28, the surface of the pad 38, the surface of the wire 39 and the back of the die 35', the surface of metal is exposed 30 by a plasma processing of a non-produced substance gas, and coating with a protecting film of an inorganic material for preventing deterioration, silicon nitride films 27, 27', 27'', 27''' and 27'<4> in particular, by a plasma CVD method is conducted. Thereby improvement in the adhesion of molding resin and the metal and prevention of melting of the organic substance outside can be attained.

Description

【発明の詳細な説明】 「産業上の利用分野」 この発明は、半導体装置等の電子部品を基板ま  。[Detailed description of the invention] "Industrial application field" This invention can be used as a substrate for electronic components such as semiconductor devices.

たはリードフレームのダイ上に有機物を用いて固着する
電子装置の高僧φ■性化およびその作製方法に関する。
The present invention relates to high-performance φ■ of electronic devices which are fixed onto a die of a lead frame or a lead frame using an organic substance, and a method for manufacturing the same.

このため本発明は、これら全体を真空容器内に保持する
ことにより有機物中の気化成分を除去せしめるとともに
、この気化成分の基板またはダイ上への付着を防止する
ことにより、それらの上に本来密着させるべき保護膜ま
たは有機樹脂との密着性を向上させんとしたものである
For this reason, the present invention removes the vaporized components in the organic matter by holding the whole in a vacuum container, and also prevents the vaporized components from adhering to the substrate or die so that it adheres to the substrate or die. This is intended to improve the adhesion with the protective film or organic resin to be coated.

そして、グイとそれに密着する保護膜との密着性を向上
させることにより、クラック、ふくれ(ダイの裏面側の
モールド剤が半田付の際、温度上昇のためダイ近傍の水
の気化により膨れてしまう現象をいう)の発生を防がん
としたものである。
By improving the adhesion between the goo and the protective film that adheres to it, cracks and blisters (the molding agent on the back side of the die swells due to vaporization of water near the die due to temperature rise during soldering) It is intended to prevent cancer from occurring.

「従来の技術」 従来、本発明人による特許側(半導体装置作製方法 昭
和58年特許願第106452号 昭和58年6月14
日出願)が知られている。
"Prior Art" Previously, the patent side by the present inventor (Semiconductor device manufacturing method, Patent Application No. 106452, 1982, June 14, 1982)
(application filed in Japan) is known.

しかし従来は第4図にその概要を示すが、リードフレー
ム(35) 、 (35’)特にICチップがダイアタ
ッチされるダイ(35’)は銅、4270イ等の金属よ
りなり、この表面(M面)には金が印刷されている。
However, in the past, as shown in Fig. 4, the lead frames (35), (35') and especially the die (35') to which the IC chip is die-attached were made of metal such as copper or 4270I; M side) is printed with gold.

そして電子部品をダイアタッチ(24)させる際は30
0〜400 ’Cの熱処理と加圧処理により、ICチッ
プをダイ(35’)上に固着させていた。
And when die attaching electronic parts (24), 30
The IC chip was fixed on the die (35') by heat treatment at 0 to 400'C and pressure treatment.

このICチップのダイ上への他の固着方法として、室温
〜300°Cに加熱した有機物を用いる固着方法もある
。しかし、ダイアタッチ用の有機物中の不要有機ガス(
24°”)、(24′)等が脱気し、基板またはリード
フレーム上に付着してしまう。このため、この後、ただ
ちに有機樹脂のモールド(41)処理を行うと、このモ
ールド剤と銅または4270イとの間にきわめてはがれ
やすい吸着物および低級酸化物層(32)が残存してし
まう。
Another method for fixing this IC chip onto a die is a method using an organic substance heated to room temperature to 300°C. However, unnecessary organic gas (
24°"), (24'), etc. are degassed and adhere to the substrate or lead frame. Therefore, if the organic resin molding (41) treatment is performed immediately after this, this molding agent and the copper Alternatively, an adsorbent and a lower oxide layer (32), which are extremely easy to peel off, remain between the adsorbent and the 4270i.

「従来の欠点」 このため、第4図に示した如く、プラスチック・モール
ド・パッケージは、一般に信頼性を低下させる水等がリ
ードフレームのダイの裏面等に集まり、半田付(一般に
260 ’C13〜10秒の溶融半田中への浸漬を行う
)の際、急激に気化し、その結果モールド剤が膨張する
応力が働く。そのためダイ(35’)とモールド剤(4
1’)との間の密着性が悪いと、この間の界面で熱歪に
よりクラック(33)。
``Conventional drawbacks'' For this reason, as shown in Figure 4, plastic mold packages generally have water, etc. that reduce reliability, which collects on the back side of the die of the lead frame. When the molding agent is immersed in molten solder for 10 seconds), the molding agent is rapidly vaporized, resulting in stress that causes the molding agent to expand. Therefore, the die (35') and molding agent (4
1'), cracks (33) occur due to thermal strain at the interface.

(33’)およびボイド(42)の発生を誘発する。(33') and voids (42) are induced.

これまで、絶縁性基板上にリードが形成された基板また
は金属リードフレームのダイ(35”)上に電子部品(
以下チップともいう)を固着させる。
Up until now, electronic components (
(hereinafter also referred to as a chip) is fixed.

この固着材用にエポキシ系の有機樹脂またはこれと銀と
が混合した銀ペースト等の有機物を含有する固着材(2
4) 、 (24’)を用いた。この固着材により電子
部品を基板またはフレーム上に固着させる際に、初期に
溶融状態であった有機物を化学反応または熱化学反応を
伴わせて固化する。これは安価かつ大量生産にはきわめ
て優れたものである。しかしこの有機物固着材(24)
 、 (24”)は大気中の室温の状態、ないし加熱(
100〜300°C)を行うと、この固着後の有機材ま
たは気化成分が残存する。この残存物は徐々に気化し、
基板またはダイ上に吸着するため、この後に形成する保
護膜またはモールド樹脂との密着性をも害してしまう。
For this fixing material, a fixing material (2
4), (24') was used. When an electronic component is fixed onto a substrate or frame using this fixing material, organic matter that is initially in a molten state is solidified through a chemical reaction or a thermochemical reaction. This is inexpensive and extremely suitable for mass production. However, this organic matter fixing material (24)
, (24”) is the state of room temperature in the atmosphere or heating (
100 to 300°C), the fixed organic material or vaporized component remains. This residue gradually evaporates,
Since it is adsorbed onto the substrate or die, it also impairs the adhesion with the protective film or mold resin that will be formed later.

「発明の構成」 本発明は、かかる従来のDIPまたはフラットパック等
のモールド封止された半導体集積回路または複数の電子
部品が基板またはリードフレーム上に有機物を含有する
固着材で固着させたハイブリッドrc等の高信頬性の電
子装置およびその信転性の低下を防ぐための作製方法を
提供するものである。本発明は、これら基板または金属
のリードフレーム上に有機物で電子部品を固着させ、さ
らにこの有機物を覆って無機物の保護膜を設けた。同時
にこの保護膜はモールド樹脂と金属との間に耐湿性の向
上、密着性の向上および有機物の外部への溶融防止の目
的で無機材料の保護膜を形成させることを特徴としてい
る。
"Structure of the Invention" The present invention provides a hybrid RC in which a conventional DIP or flat pack molded semiconductor integrated circuit or a plurality of electronic components are fixed on a substrate or lead frame with an adhesive containing an organic substance. The present invention provides an electronic device with high reliability, such as the present invention, and a manufacturing method for preventing a decrease in reliability thereof. In the present invention, electronic components are fixed onto these substrates or metal lead frames using an organic material, and an inorganic protective film is further provided to cover the organic material. At the same time, this protective film is characterized in that a protective film of an inorganic material is formed between the mold resin and the metal for the purpose of improving moisture resistance, improving adhesion, and preventing organic matter from melting to the outside.

このため、電子装置をターボ分子ポンプで真空排気する
真空容器中に保持することにより、有機物中の不要気体
成分を脱気するとともに、排気処理中のロータリーポン
プから逆流するオイルミストをも防ぐことにより、高信
鯨性を成就するものである。
For this reason, by holding the electronic device in a vacuum container that is evacuated using a turbo molecular pump, unnecessary gas components in the organic matter are degassed, and oil mist flowing back from the rotary pump during exhaust processing is also prevented. , to achieve high confidence.

さらに必要に応じて、この後同じ反応炉で同時に外部加
熱をすることなく、好ましくは室温(プラズマによる自
己発熱は若干ある)でプラズマ気相法によりこの金属表
面を含めてこれら全ての表面を保護膜で覆ってコーティ
ングを施し、その後にプラスチック・モールド処理によ
る封止を行うことを特徴としている。
Furthermore, if necessary, all these surfaces, including this metal surface, are then protected in the same reactor without external heating at the same time, preferably at room temperature (there is some self-heating due to the plasma) using a plasma vapor phase method. It is characterized by covering it with a film and applying a coating, followed by sealing using a plastic molding process.

第1図は本発明構造のプラスチックDIP(デュアルイ
ンライン型パッケイジ)またはフラットパックパッケイ
ジの継断面図を示す。
FIG. 1 shows a cross-sectional view of a plastic DIP (dual in-line package) or flat pack package constructed according to the present invention.

図面において、リードフレームのダイ(35’)に有機
物を含有する恨ペース) (24)等で密着させたチッ
プ(28)を有する。このチップアタッチの際に固着さ
せるための有機物の不要物が(24’)として側周辺に
はみだしている。チップ(28)と、このチップのアル
ミニューム・パッド(38)とステム(35)との間に
、金線(39)のワイヤボンドがなされている。
In the drawing, a chip (28) is closely attached to a die (35') of a lead frame with a paste (24) containing an organic substance. Unwanted organic matter to be fixed during chip attachment protrudes around the side as (24'). A wire bond of gold wire (39) is made between the chip (28) and its aluminum pad (38) and stem (35).

本発明は、このチップ(28)表面、パッド(38)表
面、ワイヤ(39)表面およびグイ(35’)の裏面に
対し、有機物(24) 、 (24’)中の不要気体成
分を脱気させ、それらが前記した表面に再吸収されない
ようにしたものである。このため、固着剤を含む電子装
置を高真空下に保持する。この高真空下は5×LO−’
〜I Xl0−8torrとし、排気は第2図に示す如
く、ロータリーポンプ(23)等からの有機物気体であ
るオイルの逆流を防ぐため、ターボ分子ポンプ(20)
を用いる。このターボ分子ポンプは連続的に排気するた
め、有機物気体であるオイルミストの逆流を防ぐことか
できる。さらに非生成物気体のプラズマ処理により、ダ
イアタッチの際発生した不要有機物気体成分および低級
酸化物およびナチュラルオキサイドを除去し、金属表面
を露呈(30)させ、この後、劣化防止用無機材料の保
護膜、特に窒化珪素膜(27)、 (27’)、 (2
7”)、 (27’ ”)、 (27””°)のプラズ
マCVD法によるコーティングを行う。
The present invention degass unnecessary gas components in the organic substances (24) and (24') from the surface of the chip (28), the surface of the pad (38), the surface of the wire (39), and the back surface of the guide (35'). and prevent them from being reabsorbed by the surfaces mentioned above. For this purpose, the electronic device containing the adhesive is kept under high vacuum. Under this high vacuum, 5×LO-'
~ I
Use. Since this turbomolecular pump exhausts air continuously, it can prevent backflow of oil mist, which is an organic gas. Furthermore, by plasma treatment of non-product gas, unnecessary organic gas components, lower oxides, and natural oxides generated during die attach are removed, exposing the metal surface (30), and then protecting the inorganic material for preventing deterioration. films, especially silicon nitride films (27), (27'), (2
7"), (27'"), and (27""°) coating by plasma CVD method.

第2図は、本発明のチップがフレームにボンディングさ
れた構造の基板およびそれを複数個集合させた基体(2
)(基板および基体をまとめて基体とも以下では略記す
る)を複数配設させ、プラズマ処理方法により不要の半
固層した有機物、低級酸化物の除去および同一反応炉で
大気にこれらが触れて水等が吸着しないよう、同一反応
炉内で反応性気体を切り換えることによりプラズマCV
D法による窒化珪素膜のコーティングを行うための装置
の概要を示す。
Figure 2 shows a substrate with a structure in which the chip of the present invention is bonded to a frame, and a substrate (2
) (hereinafter abbreviated as "substrate"), and plasma treatment is used to remove unnecessary semi-solid organic substances and lower oxides, and in the same reactor, they are exposed to the atmosphere and water is removed. Plasma CV
An outline of an apparatus for coating a silicon nitride film by method D is shown.

図面において、反応系(6)、ドーピング系(5)を有
している。
In the drawing, it has a reaction system (6) and a doping system (5).

反応系は、真空容器(以下反応室ともいう)(1)と予
備室(7)とを有し、ゲート弁(8) 、 (9)  
とを有している。反応室(1)は内側に供給側フード(
13)を有し、入口側(3)よりの反応性気体をフード
(14)のノズル(13)より下方向に吹き出し、排気
せしめている。
The reaction system has a vacuum container (hereinafter also referred to as reaction chamber) (1) and a preliminary chamber (7), and gate valves (8) and (9).
It has The reaction chamber (1) has a supply side hood (
13), and the reactive gas from the inlet side (3) is blown downward from the nozzle (13) of the hood (14) and exhausted.

第2図における反応性気体は、フード(13)より枠構
造のホルダ(40)の内側およびフード(13′)によ
り囲まれた内側にてターボ分子ポンプ(20)で5XI
O−’〜I Xl0−”torr好ましくはlXl0−
’〜LX10−8Lorrに5〜30分保持することに
より、第1図における固着剤中の不要有機物ガスを真空
中に脱気し、かつ基板、フレーム等上への吸着を防いだ
In FIG. 2, the reactive gas is pumped by a turbo molecular pump (20) using a 5
O-'~IXl0-"torr preferably lXl0-
'~LX10-8 Lorr for 5 to 30 minutes, the unnecessary organic gas in the fixing agent in FIG. 1 was degassed into vacuum and prevented from being adsorbed onto the substrate, frame, etc.

本発明のプラズマ処理方法は、アルゴン、ネオン、ヘリ
ウム、クリプトン等の不活性物気体、または水素、窒素
、アンモニアを用いてもよい。しかし質量が大きくかつ
比較的安価なプラズマ化しやすい気体であるアルゴンが
好ましい。この真空中に電子装置を配設して、有機物中
の不要気体成分の脱気、電子装置表面上での有機気体成
分の再付着の防止、さらに不本意にして再付着した不要
有機物成分の除去用のプラズマ処理およびその後の無機
材料の保護膜形成を電子装置を外気に触れさせることな
く第2図の如きプラズマ処理装置を用いて行った。さら
にこの上面にプラスチックモールド(41)を行った。
The plasma processing method of the present invention may use an inert gas such as argon, neon, helium, or krypton, or hydrogen, nitrogen, or ammonia. However, argon is preferable because it has a large mass, is relatively inexpensive, and is a gas that easily turns into plasma. Electronic devices are placed in this vacuum to degas unnecessary gas components in organic matter, prevent organic gas components from re-deposition on the surface of electronic devices, and remove unnecessary organic components that have inadvertently re-deposited. The initial plasma treatment and subsequent formation of a protective film of an inorganic material were carried out using a plasma treatment apparatus as shown in FIG. 2 without exposing the electronic device to the outside air. Further, a plastic mold (41) was formed on this upper surface.

この窒化珪素膜の如き保護膜は室温において、珪化物気
体とアンモニアまたは窒素とをプラズマ反応炉に導入し
、そこに電気エネルギを供給するいわゆるプラズマ気相
法により形成せしめた。
This protective film such as a silicon nitride film was formed at room temperature by a so-called plasma vapor phase method in which silicide gas and ammonia or nitrogen were introduced into a plasma reactor and electrical energy was supplied thereto.

かくの如くして、窒化珪素膜の如き劣化防止用保護膜を
300〜5000人、一般には約1000人の厚さに形
成した後、公知のインジェクション・モールド法により
有機樹脂例えばエポキシ(例えば410B)モールド法
により注入・封止させた。さらにフレームをリード部(
37)にて曲げ、かつタイバーを切断する。さらにリー
ド部を酸洗いを行った後、リードにハンダメツキを行っ
た。
After forming a protective film for preventing deterioration such as a silicon nitride film to a thickness of 300 to 5,000 layers, generally about 1,000 layers, an organic resin such as epoxy (for example, 410B) is coated by a known injection molding method. It was injected and sealed using a molding method. Furthermore, attach the frame to the lead part (
37) and cut the tie bar. Furthermore, after acid-washing the lead portion, the lead was solder-plated.

この反応容器を用い、プラズマ反応をさせ、基板または
基体(2)上での不要有機物、半有機物、低級酸化物の
除去および保護膜形成を行った。プラズマ処理または反
応後は排出側フード(14’)のノズル(13’)より
排気口(4)を経てバルブ(21)。
Using this reaction vessel, a plasma reaction was carried out to remove unnecessary organic substances, semi-organic substances, and lower oxides and to form a protective film on the substrate or substrate (2). After plasma treatment or reaction, the valve (21) is passed through the exhaust port (4) from the nozzle (13') of the discharge side hood (14').

ターボ分子ポンプ(20)さらにロータリー型真空ポン
プまたはドライ真空ポンプ(23)に至る。
The turbomolecular pump (20) further leads to a rotary vacuum pump or dry vacuum pump (23).

高周波電源(10)よりの電気エネルギは、マツチング
トランス(26)をへて、1〜500MH2例えば13
.56FIHzの周波数を上下間の一対の同じ大きさの
網状型+m(11)、 (11’)に加える。マツチン
グトランスの中点(25’)は接地レベル(25)とし
た。また周辺の枠構造のホルダ(40)は導体の場合は
接地レベル(22)とし、また絶縁体であってもよい。
The electric energy from the high frequency power source (10) passes through the matching transformer (26) and is transmitted to a power of 1 to 500 MH2, for example
.. A frequency of 56 FIHz is applied to a pair of equal-sized mesh molds +m(11), (11') between the upper and lower sides. The middle point (25') of the matching transformer was set at the ground level (25). Further, if the peripheral frame structure holder (40) is a conductor, it is at the ground level (22), or it may be an insulator.

反応性気体は、一対の電1(11)、 (12)により
供給された高周波エネルギにより励起させている。
The reactive gas is excited by high frequency energy supplied by a pair of electrons 1 (11) and (12).

また同一反応炉内における真空処理による脱気、プラズ
マ処理およびプラズマCVD法において、被形成体(2
)(以下基体(2)という)はサポータ(40’)上に
配設された枠構造のホルダ(40)内に一対の電極間の
電界の方向に平行に、さらに、いずれの電極(11) 
、 (12)からも離間させている。複数の基体(2)
は互いに一定の間隔(2〜13cm例えば6cm)また
は概略一定の間隔を有して配設されている。この多数の
基体(2)は、グロー放電により作られるプラズマ中の
陽光柱内に配設される。
In addition, in deaeration by vacuum treatment, plasma treatment, and plasma CVD methods in the same reactor, the object to be formed (2
) (hereinafter referred to as the base (2)) is placed in a frame-structured holder (40) disposed on a supporter (40') parallel to the direction of the electric field between the pair of electrodes, and furthermore, either electrode (11).
, (12). Multiple substrates (2)
are arranged at a constant interval (2 to 13 cm, for example 6 cm) or approximately at a constant interval from each other. This large number of substrates (2) is arranged in a positive column in plasma created by glow discharge.

この基体の要部を第3図(C)に示す。The main part of this base body is shown in FIG. 3(C).

第3図(A)は基体(2)において基体(35) 、 
(35“)を複数個一体化したリードフレーム上(45
)に半導体装置(28”)がボンディングされた電子装
置(29)を5〜25ケ、ユニット化した基体(45)
を有する。
FIG. 3(A) shows the base body (35) in the base body (2),
(35") on a lead frame that integrates multiple pieces (45")
) with a semiconductor device (28") bonded to a base (45) in which 5 to 25 electronic devices (29) are unitized.
has.

複数の半導体チップがボンディングされた1本のリード
フレーム(45)における1つのリードフレーム(基板
)を第3図(B)に示す。
FIG. 3B shows one lead frame (substrate) in one lead frame (45) to which a plurality of semiconductor chips are bonded.

図面ではリードを左側のみ簡単のため示す。このA−A
″での縦断面図を第3図(C)の(29)に示す。
In the drawing, only the left side of the lead is shown for simplicity. This A-A
A vertical cross-sectional view at `` is shown in (29) of FIG. 3(C).

第3図(C)において、リードフレーム(35)、グイ
(35’)、半導体チップ(28)、金属線(39)よ
りなる基板(45)をさらに5〜300本集め、ジグ(
44)により一体化し、基体(2)として構成させてい
る。この基体(2)が第2図における基体(2)に対応
している。これをさらに5〜50枚(図面では7枚)陽
光社内に第2図では配設している。
In FIG. 3(C), further 5 to 300 substrates (45) made of lead frames (35), guides (35'), semiconductor chips (28), and metal wires (39) are collected, and jigs (
44) to form a base body (2). This base body (2) corresponds to the base body (2) in FIG. In addition, 5 to 50 of these (7 in the drawing) are installed inside the Yoko company as shown in Figure 2.

第2図に示すごとき本発明方法における有機物の脱気方
法は、室温の条件下での5X10−’〜l×10−”t
orrに保持することに従った。
The method for degassing organic matter in the method of the present invention as shown in FIG. 2 is as follows:
Followed to hold at orr.

本発明において、この高真空脱気の後、反応容器内圧力
を中真空の5X10−’〜5 X 10− ’ tor
r例えば1 xlo−3〜I Xl0−3〜5×10−
1torrにおいて、プラズマを発生させ、窒化珪素膜
を形成するに際し、外部より加熱をしなくても充分に緻
密な絶縁膜を作ることができる。
In the present invention, after this high vacuum degassing, the internal pressure of the reaction vessel is reduced to a medium vacuum of 5X10-' to 5X10-' tor.
rFor example, 1xlo-3~IXl0-3~5x10-
When plasma is generated at 1 torr and a silicon nitride film is formed, a sufficiently dense insulating film can be formed without external heating.

そのプロセス上の1例を以下に示す。An example of this process is shown below.

「実施例IJ 第2図の高真空下に保持することによる不要有機物の脱
気、プラズマ処理装置およびプラズマCVD装置におい
て、ドーピング系(5)は珪化物気体であるジシラン(
SiJJ を(17)より、また窒化物気体であるアン
モニアまたは窒素を(16)より、プラズマ処理用の非
生成物気体であるアルゴンを(15)より供給している
。それらは流量計(1B) 、バルブ(19)により制
御されている。
"Example IJ In the deaeration of unnecessary organic matter by holding under high vacuum in FIG. 2, plasma processing equipment, and plasma CVD equipment, the doping system (5) is disilane (a silicide gas)
SiJJ is supplied from (17), ammonia or nitrogen, which is a nitride gas, is supplied from (16), and argon, which is a non-product gas for plasma processing, is supplied from (15). They are controlled by a flow meter (1B) and a valve (19).

例えば、大量生産のため基板温度は外部加熱を特に積極
的に行わない室温(プラズマによる自己加熱を含む)と
した。
For example, for mass production, the substrate temperature was set to room temperature (including self-heating by plasma) without any active external heating.

まず反応空間(1)を1×1o弓〜l×1O−8tor
rに5〜15分保持し、有機物中の不要物気体を脱気さ
せるとともに、これを速やかに外部に排気した。
First, the reaction space (1) is 1 x 1o bow ~ l x 1O-8tor
The reactor was held at a temperature of R for 5 to 15 minutes to degas the unnecessary gases in the organic matter, and this was promptly exhausted to the outside.

さらにその後5 Xl0−2torrにアルゴンを導入
しつつ、同時に排気し、電気エネルギを与え、プラズマ
化し基体(2)の表面のプラズマ処理を行った。
Furthermore, after that, argon was introduced to 5 Xl0-2 torr and at the same time it was evacuated, and electrical energy was applied to generate plasma and perform plasma treatment on the surface of the substrate (2).

即ちこれらアルゴンに対し、13.56MHzの周波数
ニよりIKWの出力を一対の電極(11)、 (11”
)に10〜30分供給してプラズマ化した。するとこの
ダイの裏面に付着しているオイルミスト、不要有機物お
よび水分、低級酸化物を除去し、新たな金属面を露呈さ
せることができ、成膜する被膜の密着性を向上させるこ
とができた。
That is, for these argon, the output of IKW is applied from a frequency of 13.56 MHz to a pair of electrodes (11), (11"
) for 10 to 30 minutes to generate plasma. This removed the oil mist, unnecessary organic matter, moisture, and lower oxides adhering to the back side of the die, exposing a new metal surface and improving the adhesion of the film being formed. .

次にこのプラズマ処理がなされた被形成面上に保護膜を
同一反応炉で大気にふれさせることなく形成する。即ち
窒化珪素膜を形成する場合、反応性気体は例えば、5i
J6/Nz = 115とした。これらアルゴンに対し
、13.56MHzの周波数によりIKHの出力を一対
の電極(11)、 (11’)に供給した。かくして平
均1000人(1000人±200人)に約10分(平
均速度3A/秒)の被膜形成を行った。
Next, a protective film is formed on the plasma-treated surface in the same reactor without exposing it to the atmosphere. That is, when forming a silicon nitride film, the reactive gas is, for example, 5i
J6/Nz = 115. For these argon, IKH output was supplied to a pair of electrodes (11) and (11') at a frequency of 13.56 MHz. In this way, coatings were formed on an average of 1000 people (1000±200 people) for about 10 minutes (average speed 3 A/sec).

窒化珪素膜はその絶縁耐圧8 X 106V/cm以上
を有し、比抵抗は2X10”Ωcmであった。赤外線吸
収スペクトルでは864cm −’の5i−N結合の吸
収ピークを有し、屈折率は2.0であった。
The silicon nitride film had a dielectric strength voltage of 8 x 106 V/cm or more, and a specific resistance of 2 x 10'' Ωcm.The infrared absorption spectrum had an absorption peak of 5i-N bond at 864 cm -', and the refractive index was 2. It was .0.

5χNaC1で溶解させた塩水中(95°C)に保有し
てところ、20時間を経ても何らの劣化も見られなかっ
た。このため、本発明の劣化防止用保護膜として用いる
ことを証明することができた。
When kept in saline solution (95°C) in which 5χNaCl was dissolved, no deterioration was observed even after 20 hours. Therefore, it was possible to prove that the film can be used as a protective film for preventing deterioration of the present invention.

かかる本発明方法で作られた電子装置に対し、85°C
/85χ(相対温度)で1000時間放置して、その後
、半田付けを260°C5秒行った。しかしこのモール
ドには何らのクラックもまたふくれも発生しなかった。
For electronic devices manufactured by the method of the present invention, 85°C
/85χ (relative temperature) for 1000 hours, and then soldering was performed at 260°C for 5 seconds. However, this mold did not develop any cracks or blisters.

さらに85°C/85χで300ケ放置しプラスチック
モールドに吸水させ、その後260°C13秒の加熱を
行う条件の信頼性テストを行った。
Furthermore, a reliability test was conducted under the conditions that 300 molds were left at 85°C/85χ to absorb water into the plastic mold, and then heated at 260°C for 13 seconds.

その−例を以下の表に示す。Examples are shown in the table below.

その結果、真空処理、プラズマ処理および保護膜の形成
を行うと100ケ中不良品零とすべて良品(No、 1
〜5)であり、また真空処理と保護膜形成の工程でもま
ったく不良品はなかった。(No、6〜10)シかし保
護膜がない場合は20ケ中4〜20ケが不良品(No、
13〜15)であり、また保護膜があっても真空処理が
十分でないと一部に不良品が発生してしまった。(No
、11〜12) さらに一般にアルミニューム・パッドの表面はモールド
材と密着性が悪い。しかし本発明の如くこのアルミパッ
ド(第1図(3B))上に保護膜を形成すると、ここで
の密着性が向上し、加えて窒化珪素膜は水、塩素に対す
るブロッキング効果(マスク効果)が大きい。このため
本発明構造の電子装置(例えば半導体集積回路)におい
ては、PCT(プレッシャー・クツカー・テスト) 2
atom、120°Cの条件下で20時間おいても、ま
ったく不良が観察されず、従来のICチップが50〜1
00フイツトの不良率を有していたが、5〜10フイツ
トにまでその不良率を下げることが可能になった。
As a result, after vacuum treatment, plasma treatment, and protective film formation, there were no defective items out of 100 and all were good (No. 1).
~5), and there were no defective products at all during the vacuum treatment and protective film formation steps. (No. 6 to 10) If there is no stain protection film, 4 to 20 out of 20 products are defective (No.
13 to 15), and even with a protective film, if the vacuum treatment was not sufficient, some products were defective. (No
, 11-12) Furthermore, the surface of the aluminum pad generally has poor adhesion to the molding material. However, when a protective film is formed on this aluminum pad (Fig. 1 (3B)) as in the present invention, the adhesion here is improved, and in addition, the silicon nitride film has a blocking effect (mask effect) against water and chlorine. big. Therefore, in electronic devices (for example, semiconductor integrated circuits) having the structure of the present invention, PCT (Pressure Cutcher Test) 2
Atom, even after 20 hours at 120°C, no defects were observed, and conventional IC chips were 50 to 1
The defective rate was 0.00 fits, but now it has become possible to lower the defective rate to 5 to 10 fits.

なお本発明においては、高真空下に保持すること、およ
びプラズマ処理方法およびPCVD法において、電気エ
ネルギのみならず、10〜15μの波長の遠赤外線また
は300nm以下の紫外光を同時に加えた光エネルギを
用い有機物除去用のフォトクリーニング法を併用するこ
とは有効である。
In addition, in the present invention, it is necessary to maintain under a high vacuum, and in the plasma processing method and PCVD method, not only electric energy but also light energy in which far infrared rays with a wavelength of 10 to 15 μm or ultraviolet light of 300 nm or less are simultaneously added. It is effective to use a photo-cleaning method for removing organic matter.

「効果J 本発明において、基板またはリードフレーム上に電子部
品と有機物とを固着し、有機物を含むこれらを無機の保
護膜で覆ったため、この有機物中よりモールド剤への再
放出を防くことができ、その中に添加されている銀のマ
イグレイジョンも防ぎ得た。またフレームとモールド剤
との間の密着性を防ぐことも可能となった。また加熱に
必要な電力、時間がいらず、生産性に優れている。ダイ
の裏面に対しても、吸着有機物、低級酸化物を除去して
いるため、有機樹脂の密着性を向上させることができた
。また保護膜を形成すると、長期間たっても、有機樹脂
中の水分、塩素とダイの金属との間で反応を起こして低
級酸化物ができ、信頬性を低下させるという欠点がない
。そして裏面からの水分の侵入を防ぐことができる。こ
の電子装置のPCBへの半導体による装着の際、従来例
に示す如く、モールド材が加熱により膨れてしまうこと
を防くことができた。
"Effect J" In the present invention, electronic components and organic substances are fixed on a substrate or lead frame, and these containing organic substances are covered with an inorganic protective film, so that it is possible to prevent the organic substances from being re-released into the molding agent. It was also possible to prevent the migration of the silver added therein. It was also possible to prevent the adhesion between the frame and the molding agent. Also, there was no need for electricity or time for heating. , it has excellent productivity.Since adsorbed organic substances and lower oxides are removed from the back side of the die, the adhesion of the organic resin can be improved.Also, when a protective film is formed, it can be used for a long time. Even after a period of time, there is no disadvantage that lower oxides are formed due to the reaction between the moisture in the organic resin, chlorine, and the metal of the die, reducing reliability.Also, it prevents moisture from entering from the back side. When mounting this electronic device on a PCB using a semiconductor, it was possible to prevent the mold material from swelling due to heating, as shown in the conventional example.

本発明における保護膜は窒化珪素膜とした。しかしこれ
をDLC(ダイヤモンド・ライク・カーボン)膜、酸化
珪素膜、その他の絶縁膜の単層または多層膜であっても
よい。
The protective film in the present invention was a silicon nitride film. However, this may be a single layer or multilayer film of a DLC (diamond-like carbon) film, a silicon oxide film, or other insulating film.

さらに本発明において、電子部品チップは半導体素子と
して示したが、その他、絶縁基板上に金属導体が設けら
れ、これらに抵抗、コンデンサを固着させたハイブリッ
ドICであってもよく、ボンディングもワイヤボンディ
ングのみならずフリップチップボンディング、ハンダバ
ンプボンディングでもよい。
Further, in the present invention, the electronic component chip is shown as a semiconductor element, but it may also be a hybrid IC in which a metal conductor is provided on an insulating substrate and a resistor and a capacitor are fixed to these, and bonding can be performed only by wire bonding. Alternatively, flip chip bonding or solder bump bonding may be used.

本発明において、チップの大きさが大きくなって、ダイ
を用いることなしにモールドする場合がある。しかしそ
の場合も基体としての基板またはリードフレーム、チッ
プのすべてを覆って保護膜を設けることは有効である。
In the present invention, the size of the chip may be increased and it may be molded without using a die. However, even in that case, it is effective to provide a protective film covering all of the substrate, lead frame, and chip.

上述した説明においては、リードフレーム上に半導体チ
ップを載置した場合について述べているが、本発明は特
にデュアルインライン型のリードフレームに限るもので
はなく、フラットパック型のリードフレームおよびその
他のリードフレームに対しても同様の機能を持つもので
あっても、同様の効果が期待できるものである。
Although the above description describes the case where a semiconductor chip is mounted on a lead frame, the present invention is not limited to a dual-in-line type lead frame, but is applicable to a flat pack type lead frame and other lead frames. Even if it has a similar function, similar effects can be expected.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の耐湿テストおよび半田付はテストをし
た後のプラスチック・パッケージ半導体装置の縦断面部
の要部を示す。 第2図は本発明方法を実施するだめのプラズマ気相反応
装置の概要を示す。 第3図は第2図の装置のうちの基体部の拡大図を示す。 第4図は従来例のプラスチックパッケージを耐湿テスト
および半田付はテストをした後の縦断面図の要部を示す
。 87′ 茗IC ニ工■プ下1(A) ゝ、 0°’   E 3 (B 不 41”71
FIG. 1 shows a main part of a plastic package semiconductor device in longitudinal section after the moisture resistance test and soldering test of the present invention. FIG. 2 shows an outline of a plasma gas phase reactor for carrying out the method of the present invention. FIG. 3 shows an enlarged view of the base portion of the device of FIG. FIG. 4 shows a main part of a conventional plastic package in a vertical sectional view after being subjected to a moisture resistance test and a soldering test. 87' Mei IC Nitech ■P 1 (A) ゝ, 0°' E 3 (B Not 41"71

Claims (4)

【特許請求の範囲】[Claims] 1.電子部品を基板またはリードフレームのダイ上に有
機物を含有する固着材により固着せしめた電子装置にお
いて、前記固着材の表面を覆うとともに、前記基板また
はリードフレームの表面をも覆って無機材料の保護膜を
設けることを特徴とする電子装置。
1. In an electronic device in which an electronic component is fixed to a die of a substrate or a lead frame using a bonding material containing an organic substance, a protective film of an inorganic material is provided, covering the surface of the bonding material and also covering the surface of the substrate or lead frame. An electronic device characterized by being provided with.
2.特許請求の範囲第1項において、保護膜を覆って有
機樹脂封止処理を行うことを特徴とする電子装置。
2. An electronic device according to claim 1, characterized in that the protective film is covered with an organic resin sealing process.
3.電子部品を基板またはリードフレームのダイ上に有
機物を含有する固着材により固着せしめる電子装置の作
製方法において、前記電子装置を高真空中に保持するこ
とにより、前記有機物中の気体成分を脱気する工程と、
前記電子装置を5×10^−^3〜5×10^−^1t
orrの圧力下で非生成物気体でプラズマ処理する工程
と、5×10^−^3〜5×10^−^1torrの圧
力下で保護膜をプラズマ気相反応法により形成する工程
とを有し、これら工程は同一真空容器内で処理すること
を特徴とする電子装置作製方法。
3. In a method for manufacturing an electronic device in which an electronic component is fixed onto a die of a substrate or a lead frame using a bonding material containing an organic substance, gas components in the organic substance are degassed by holding the electronic device in a high vacuum. process and
The electronic device is 5×10^-^3~5×10^-^1t
The process includes a process of plasma treatment with a non-product gas under a pressure of 1 torr and a process of forming a protective film by a plasma vapor phase reaction method under a pressure of 5 x 10^-^3 to 5 x 10^-^1 torr. The electronic device manufacturing method is characterized in that these steps are performed in the same vacuum container.
4.特許請求の範囲第3項において、電子装置は外部加
熱することなく、高真空中は5×10^−^4〜1×1
0^−^8torrに保持されたことを特徴とする電子
装置作製方法。
4. In claim 3, the electronic device is heated at 5 x 10^-^4 to 1 x 1 in high vacuum without external heating.
A method for manufacturing an electronic device, characterized in that the pressure is maintained at 0^-^8 torr.
JP63227166A 1988-09-10 1988-09-10 Electronic device and manufacture thereof Pending JPH0276249A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63227166A JPH0276249A (en) 1988-09-10 1988-09-10 Electronic device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63227166A JPH0276249A (en) 1988-09-10 1988-09-10 Electronic device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH0276249A true JPH0276249A (en) 1990-03-15

Family

ID=16856524

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63227166A Pending JPH0276249A (en) 1988-09-10 1988-09-10 Electronic device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH0276249A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0383365A (en) * 1989-08-28 1991-04-09 Semiconductor Energy Lab Co Ltd Electronic device
US5685071A (en) * 1995-06-05 1997-11-11 Hughes Electronics Method of constructing a sealed chip-on-board electronic module
WO2015000592A1 (en) * 2013-07-03 2015-01-08 Rosenberger Hochfrequenztechnik Gmbh & Co. Kg Coated bond wires for die packages and methods of manufacturing said coated bond wires

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0383365A (en) * 1989-08-28 1991-04-09 Semiconductor Energy Lab Co Ltd Electronic device
US5685071A (en) * 1995-06-05 1997-11-11 Hughes Electronics Method of constructing a sealed chip-on-board electronic module
WO2015000592A1 (en) * 2013-07-03 2015-01-08 Rosenberger Hochfrequenztechnik Gmbh & Co. Kg Coated bond wires for die packages and methods of manufacturing said coated bond wires
US9997489B2 (en) 2013-07-03 2018-06-12 Rosenberger Hochfrequenztechnik Gmbh & Co. Kg Coated bond wires for die packages and methods of manufacturing said coated bond wires

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